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tic80.h
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00001 /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
00002    Copyright 1996, 1997, 2003 Free Software Foundation, Inc.
00003    Written by Fred Fish (fnf@cygnus.com), Cygnus Support
00004 
00005 This file is part of GDB, GAS, and the GNU binutils.
00006 
00007 GDB, GAS, and the GNU binutils are free software; you can redistribute
00008 them and/or modify them under the terms of the GNU General Public
00009 License as published by the Free Software Foundation; either version
00010 1, or (at your option) any later version.
00011 
00012 GDB, GAS, and the GNU binutils are distributed in the hope that they
00013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015 the GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this file; see the file COPYING.  If not, write to the Free
00019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 #ifndef TIC80_H
00022 #define TIC80_H
00023 
00024 /* The opcode table is an array of struct tic80_opcode.  */
00025 
00026 struct tic80_opcode
00027 {
00028   /* The opcode name.  */
00029 
00030   const char *name;
00031 
00032   /* The opcode itself.  Those bits which will be filled in with operands
00033      are zeroes.  */
00034 
00035   unsigned long opcode;
00036 
00037   /* The opcode mask.  This is used by the disassembler.  This is a mask
00038      containing ones indicating those bits which must match the opcode
00039      field, and zeroes indicating those bits which need not match (and are
00040      presumably filled in by operands).  */
00041 
00042   unsigned long mask;
00043 
00044   /* Special purpose flags for this opcode. */
00045 
00046   unsigned char flags;
00047 
00048   /* An array of operand codes.  Each code is an index into the operand
00049      table.  They appear in the order which the operands must appear in
00050      assembly code, and are terminated by a zero.  FIXME: Adjust size to
00051      match actual requirements when TIc80 support is complete */
00052 
00053   unsigned char operands[8];
00054 };
00055 
00056 /* The table itself is sorted by major opcode number, and is otherwise in
00057    the order in which the disassembler should consider instructions.
00058    FIXME: This isn't currently true. */
00059 
00060 extern const struct tic80_opcode tic80_opcodes[];
00061 extern const int tic80_num_opcodes;
00062 
00063 
00064 /* The operands table is an array of struct tic80_operand.  */
00065 
00066 struct tic80_operand
00067 {
00068   /* The number of bits in the operand.  */
00069 
00070   int bits;
00071 
00072   /* How far the operand is left shifted in the instruction.  */
00073 
00074   int shift;
00075 
00076   /* Insertion function.  This is used by the assembler.  To insert an
00077      operand value into an instruction, check this field.
00078 
00079      If it is NULL, execute
00080          i |= (op & ((1 << o->bits) - 1)) << o->shift;
00081      (i is the instruction which we are filling in, o is a pointer to
00082      this structure, and op is the opcode value; this assumes twos
00083      complement arithmetic).
00084 
00085      If this field is not NULL, then simply call it with the
00086      instruction and the operand value.  It will return the new value
00087      of the instruction.  If the ERRMSG argument is not NULL, then if
00088      the operand value is illegal, *ERRMSG will be set to a warning
00089      string (the operand will be inserted in any case).  If the
00090      operand value is legal, *ERRMSG will be unchanged (most operands
00091      can accept any value).  */
00092 
00093   unsigned long (*insert)
00094     (unsigned long instruction, long op, const char **errmsg);
00095 
00096   /* Extraction function.  This is used by the disassembler.  To
00097      extract this operand type from an instruction, check this field.
00098 
00099      If it is NULL, compute
00100          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
00101         if ((o->flags & TIC80_OPERAND_SIGNED) != 0
00102             && (op & (1 << (o->bits - 1))) != 0)
00103           op -= 1 << o->bits;
00104      (i is the instruction, o is a pointer to this structure, and op
00105      is the result; this assumes twos complement arithmetic).
00106 
00107      If this field is not NULL, then simply call it with the
00108      instruction value.  It will return the value of the operand.  If
00109      the INVALID argument is not NULL, *INVALID will be set to
00110      non-zero if this operand type can not actually be extracted from
00111      this operand (i.e., the instruction does not match).  If the
00112      operand is valid, *INVALID will not be changed.  */
00113 
00114   long (*extract) (unsigned long instruction, int *invalid);
00115 
00116   /* One bit syntax flags.  */
00117 
00118   unsigned long flags;
00119 };
00120 
00121 /* Elements in the table are retrieved by indexing with values from
00122    the operands field of the tic80_opcodes table.  */
00123 
00124 extern const struct tic80_operand tic80_operands[];
00125 
00126 
00127 /* Values defined for the flags field of a struct tic80_operand.
00128 
00129    Note that flags for all predefined symbols, such as the general purpose
00130    registers (ex: r10), control registers (ex: FPST), condition codes (ex:
00131    eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
00132    or'd into an int where the lower bits contain the actual numeric value
00133    that correponds to this predefined symbol.  This way a single int can
00134    contain both the value of the symbol and it's type.
00135  */
00136 
00137 /* This operand must be an even register number.  Floating point numbers
00138    for example are stored in even/odd register pairs. */
00139 
00140 #define TIC80_OPERAND_EVEN  (1 << 0)
00141 
00142 /* This operand must be an odd register number and must be one greater than
00143    the register number of the previous operand.  I.E. the second register in
00144    an even/odd register pair. */
00145 
00146 #define TIC80_OPERAND_ODD   (1 << 1)
00147 
00148 /* This operand takes signed values.  */
00149 
00150 #define TIC80_OPERAND_SIGNED       (1 << 2)
00151 
00152 /* This operand may be either a predefined constant name or a numeric value.
00153    An example would be a condition code like "eq0.b" which has the numeric
00154    value 0x2. */
00155 
00156 #define TIC80_OPERAND_NUM   (1 << 3)
00157 
00158 /* This operand should be wrapped in parentheses rather than separated
00159    from the previous one by a comma.  This is used for various
00160    instructions, like the load and store instructions, which want
00161    their operands to look like "displacement(reg)" */
00162 
00163 #define TIC80_OPERAND_PARENS       (1 << 4)
00164 
00165 /* This operand is a PC relative branch offset.  The disassembler prints
00166    these symbolically if possible.  Note that the offsets are taken as word
00167    offsets. */
00168 
00169 #define TIC80_OPERAND_PCREL (1 << 5)
00170 
00171 /* This flag is a hint to the disassembler for using hex as the prefered
00172    printing format, even for small positive or negative immediate values.
00173    Normally values in the range -999 to 999 are printed as signed decimal
00174    values and other values are printed in hex. */
00175 
00176 #define TIC80_OPERAND_BITFIELD     (1 << 6)
00177 
00178 /* This operand may have a ":m" modifier specified by bit 17 in a short
00179    immediate form instruction. */
00180 
00181 #define TIC80_OPERAND_M_SI  (1 << 7)
00182 
00183 /* This operand may have a ":m" modifier specified by bit 15 in a long
00184    immediate or register form instruction. */
00185 
00186 #define TIC80_OPERAND_M_LI  (1 << 8)
00187 
00188 /* This operand may have a ":s" modifier specified in bit 11 in a long
00189    immediate or register form instruction. */
00190 
00191 #define TIC80_OPERAND_SCALED       (1 << 9)
00192 
00193 /* This operand is a floating point value */
00194 
00195 #define TIC80_OPERAND_FLOAT (1 << 10)
00196 
00197 /* This operand is an byte offset from a base relocation. The lower
00198  two bits of the final relocated address are ignored when the value is
00199  written to the program counter. */
00200 
00201 #define TIC80_OPERAND_BASEREL      (1 << 11)
00202 
00203 /* This operand is an "endmask" field for a shift instruction.
00204    It is treated special in that it can have values of 0-32,
00205    where 0 and 32 result in the same instruction.  The assembler
00206    must be able to accept both endmask values.  This disassembler
00207    has no way of knowing from the instruction which value was 
00208    given at assembly time, so it just uses '0'. */
00209 
00210 #define TIC80_OPERAND_ENDMASK      (1 << 12)
00211 
00212 /* This operand is one of the 32 general purpose registers.
00213    The disassembler prints these with a leading 'r'. */
00214 
00215 #define TIC80_OPERAND_GPR   (1 << 27)
00216 
00217 /* This operand is a floating point accumulator register.
00218    The disassembler prints these with a leading 'a'. */
00219 
00220 #define TIC80_OPERAND_FPA   ( 1 << 28)
00221 
00222 /* This operand is a control register number, either numeric or
00223    symbolic (like "EIF", "EPC", etc).
00224    The disassembler prints these symbolically. */
00225 
00226 #define TIC80_OPERAND_CR    (1 << 29)
00227 
00228 /* This operand is a condition code, either numeric or
00229    symbolic (like "eq0.b", "ne0.w", etc).
00230    The disassembler prints these symbolically. */
00231 
00232 #define TIC80_OPERAND_CC    (1 << 30)
00233 
00234 /* This operand is a bit number, either numeric or
00235    symbolic (like "eq.b", "or.f", etc).
00236    The disassembler prints these symbolically.
00237    Note that they appear in the instruction in 1's complement relative
00238    to the values given in the manual. */
00239 
00240 #define TIC80_OPERAND_BITNUM       (1 << 31)
00241 
00242 /* This mask is used to strip operand bits from an int that contains
00243    both operand bits and a numeric value in the lsbs. */
00244 
00245 #define TIC80_OPERAND_MASK  (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
00246 
00247 
00248 /* Flag bits for the struct tic80_opcode flags field. */
00249 
00250 #define TIC80_VECTOR        01     /* Is a vector instruction */
00251 #define TIC80_NO_R0_DEST    02     /* Register r0 cannot be a destination register */
00252 
00253 
00254 /* The opcodes library contains a table that allows translation from predefined
00255    symbol names to numeric values, and vice versa. */
00256 
00257 /* Structure to hold information about predefined symbols.  */
00258 
00259 struct predefined_symbol
00260 {
00261   char *name;        /* name to recognize */
00262   int value;
00263 };
00264 
00265 #define PDS_NAME(pdsp) ((pdsp) -> name)
00266 #define PDS_VALUE(pdsp) ((pdsp) -> value)
00267 
00268 /* Translation array.  */
00269 extern const struct predefined_symbol tic80_predefined_symbols[];
00270 /* How many members in the array.  */
00271 extern const int tic80_num_predefined_symbols;
00272 
00273 /* Translate value to symbolic name.  */
00274 const char *tic80_value_to_symbol (int val, int class);
00275 
00276 /* Translate symbolic name to value.  */
00277 int tic80_symbol_to_value (char *name, int class);
00278 
00279 const struct predefined_symbol *tic80_next_predefined_symbol
00280   (const struct predefined_symbol *);
00281 
00282 #endif /* TIC80_H */