Back to index

cell-binutils  2.17cvs20070401
tic4x.h
Go to the documentation of this file.
00001 /* Table of opcodes for the Texas Instruments TMS320C[34]X family.
00002 
00003    Copyright (C) 2002, 2003 Free Software Foundation.
00004   
00005    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
00006    
00007    This program is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2 of the License, or
00010    (at your option) any later version.
00011 
00012    This program is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with this program; if not, write to the Free Software
00019    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00020 */
00021 
00022 #define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
00023 #define IS_CPU_TIC4X(v) ((v) ==  0 || (v) == 40 || (v) == 44)
00024 
00025 /* Define some bitfield extraction/insertion macros.  */
00026 #define EXTR(inst, m, l)          ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) 
00027 #define EXTRU(inst, m, l)         EXTR ((unsigned long)(inst), (m), (l))
00028 #define EXTRS(inst, m, l)         EXTR ((long)(inst), (m), (l))
00029 #define INSERTU(inst, val, m, l)  (inst |= ((val) << (l))) 
00030 #define INSERTS(inst, val, m, l)  INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)
00031 
00032 /* Define register numbers.  */
00033 typedef enum
00034   {
00035     REG_R0, REG_R1, REG_R2, REG_R3,
00036     REG_R4, REG_R5, REG_R6, REG_R7,
00037     REG_AR0, REG_AR1, REG_AR2, REG_AR3,
00038     REG_AR4, REG_AR5, REG_AR6, REG_AR7,
00039     REG_DP, REG_IR0, REG_IR1, REG_BK,
00040     REG_SP, REG_ST, REG_DIE, REG_IIE,
00041     REG_IIF, REG_RS, REG_RE, REG_RC,
00042     REG_R8, REG_R9, REG_R10, REG_R11,
00043     REG_IVTP, REG_TVTP
00044   }
00045 c4x_reg_t;
00046 
00047 /* Note that the actual register numbers for IVTP is 0 and TVTP is 1.  */
00048 
00049 #define REG_IE REG_DIE             /* C3x only */
00050 #define REG_IF REG_IIE             /* C3x only */
00051 #define REG_IOF REG_IIF            /* C3x only */
00052 
00053 #define TIC3X_REG_MAX REG_RC
00054 #define TIC4X_REG_MAX REG_TVTP
00055 
00056 /* Register table size including C4x expansion regs.  */
00057 #define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
00058 
00059 struct tic4x_register
00060 {
00061   char *        name;
00062   unsigned long regno;
00063 };
00064 
00065 typedef struct tic4x_register tic4x_register_t;
00066 
00067 /* We could store register synonyms here.  */
00068 static const tic4x_register_t tic3x_registers[] =
00069 {
00070   {"f0",  REG_R0},
00071   {"r0",  REG_R0},
00072   {"f1",  REG_R1},
00073   {"r1",  REG_R1},
00074   {"f2",  REG_R2},
00075   {"r2",  REG_R2},
00076   {"f3",  REG_R3},
00077   {"r3",  REG_R3},
00078   {"f4",  REG_R4},
00079   {"r4",  REG_R4},
00080   {"f5",  REG_R5},
00081   {"r5",  REG_R5},
00082   {"f6",  REG_R6},
00083   {"r6",  REG_R6},
00084   {"f7",  REG_R7},
00085   {"r7",  REG_R7},
00086   {"ar0", REG_AR0},
00087   {"ar1", REG_AR1},
00088   {"ar2", REG_AR2},
00089   {"ar3", REG_AR3},
00090   {"ar4", REG_AR4},
00091   {"ar5", REG_AR5},
00092   {"ar6", REG_AR6},
00093   {"ar7", REG_AR7},
00094   {"dp",  REG_DP},
00095   {"ir0", REG_IR0},
00096   {"ir1", REG_IR1},
00097   {"bk",  REG_BK},
00098   {"sp",  REG_SP},
00099   {"st",  REG_ST},
00100   {"ie",  REG_IE},
00101   {"if",  REG_IF},
00102   {"iof", REG_IOF},
00103   {"rs",  REG_RS},
00104   {"re",  REG_RE},
00105   {"rc",  REG_RC},
00106   {"", 0}
00107 };
00108 
00109 const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
00110 
00111 /* Define C4x registers in addition to C3x registers.  */
00112 static const tic4x_register_t tic4x_registers[] =
00113 {
00114   {"die", REG_DIE},         /* Clobbers C3x REG_IE */
00115   {"iie", REG_IIE},         /* Clobbers C3x REG_IF */
00116   {"iif", REG_IIF},         /* Clobbers C3x REG_IOF */
00117   {"f8",  REG_R8},
00118   {"r8",  REG_R8},
00119   {"f9",  REG_R9},
00120   {"r9",  REG_R9},
00121   {"f10", REG_R10},
00122   {"r10", REG_R10},
00123   {"f11", REG_R11},
00124   {"r11", REG_R11},
00125   {"ivtp", REG_IVTP},
00126   {"tvtp", REG_TVTP},
00127   {"", 0}
00128 };
00129 
00130 const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
00131 
00132 struct tic4x_cond
00133 {
00134   char *        name;
00135   unsigned long cond;
00136 };
00137 
00138 typedef struct tic4x_cond tic4x_cond_t;
00139 
00140 /* Define conditional branch/load suffixes.  Put desired form for
00141    disassembler last.  */
00142 static const tic4x_cond_t tic4x_conds[] =
00143 {
00144   { "u",    0x00 },
00145   { "c",    0x01 }, { "lo",  0x01 },
00146   { "ls",   0x02 },
00147   { "hi",   0x03 },
00148   { "nc",   0x04 }, { "hs",  0x04 },
00149   { "z",    0x05 }, { "eq",  0x05 },
00150   { "nz",   0x06 }, { "ne",  0x06 },
00151   { "n",    0x07 }, { "l",   0x07 }, { "lt",  0x07 },
00152   { "le",   0x08 },
00153   { "p",    0x09 }, { "gt",  0x09 },
00154   { "nn",   0x0a }, { "ge",  0x0a },
00155   { "nv",   0x0c },
00156   { "v",    0x0d },
00157   { "nuf",  0x0e },
00158   { "uf",   0x0f },
00159   { "nlv",  0x10 },
00160   { "lv",   0x11 },
00161   { "nluf", 0x12 },
00162   { "luf",  0x13 },
00163   { "zuf",  0x14 },
00164   /* Dummy entry, not included in num_conds.  This
00165      lets code examine entry i+1 without checking
00166      if we've run off the end of the table.  */
00167   { "",      0x0}
00168 };
00169 
00170 const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
00171 
00172 struct tic4x_indirect
00173 {
00174   char *        name;
00175   unsigned long modn;
00176 };
00177 
00178 typedef struct tic4x_indirect tic4x_indirect_t;
00179 
00180 /* Define indirect addressing modes where:
00181    d displacement (signed)
00182    y ir0
00183    z ir1  */
00184 
00185 static const tic4x_indirect_t tic4x_indirects[] =
00186 {
00187   { "*+a(d)",   0x00 },
00188   { "*-a(d)",   0x01 },
00189   { "*++a(d)",  0x02 },
00190   { "*--a(d)",  0x03 },
00191   { "*a++(d)",  0x04 },
00192   { "*a--(d)",  0x05 },
00193   { "*a++(d)%", 0x06 },
00194   { "*a--(d)%", 0x07 },
00195   { "*+a(y)",   0x08 },
00196   { "*-a(y)",   0x09 },
00197   { "*++a(y)",  0x0a },
00198   { "*--a(y)",  0x0b },
00199   { "*a++(y)",  0x0c },
00200   { "*a--(y)",  0x0d },
00201   { "*a++(y)%", 0x0e },
00202   { "*a--(y)%", 0x0f },
00203   { "*+a(z)",   0x10 },
00204   { "*-a(z)",   0x11 },
00205   { "*++a(z)",  0x12 },
00206   { "*--a(z)",  0x13 },
00207   { "*a++(z)",  0x14 },
00208   { "*a--(z)",  0x15 },
00209   { "*a++(z)%", 0x16 },
00210   { "*a--(z)%", 0x17 },
00211   { "*a",       0x18 },
00212   { "*a++(y)b", 0x19 },
00213   /* Dummy entry, not included in num_indirects.  This
00214      lets code examine entry i+1 without checking
00215      if we've run off the end of the table.  */
00216   { "",      0x0}
00217 };
00218 
00219 #define TIC3X_MODN_MAX 0x19
00220 
00221 const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
00222 
00223 /* Instruction template.  */
00224 struct tic4x_inst
00225 {
00226   char *        name;
00227   unsigned long opcode;
00228   unsigned long opmask;
00229   char *        args;
00230   unsigned long oplevel;
00231 };
00232 
00233 typedef struct tic4x_inst tic4x_inst_t;
00234 
00235 /* Opcode infix
00236    B  condition              16--20   U,C,Z,LO,HI, etc.
00237    C  condition              23--27   U,C,Z,LO,HI, etc.
00238 
00239    Arguments
00240    ,  required arg follows
00241    ;  optional arg follows
00242 
00243    Argument types             bits    [classes] - example
00244    -----------------------------------------------------------
00245    *  indirect (all)          0--15   [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
00246    #  direct (for LDP)        0--15   [Z] - @start, start
00247    @  direct                  0--15   [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
00248    A  address register       22--24   [D] - AR0, AR7
00249    B  unsigned integer        0--23   [I,I2] - @start, start  (absolute on C3x, relative on C4x)
00250    C  indirect (disp - C4x)   0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
00251    E  register (all)          0--7    [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
00252    e  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11
00253    F  short float immediate   0--15   [AF,B,BA,BB] - 3.5, 0e-3.5e-1
00254    G  register (all)          8--15   [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
00255    g  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11
00256    H  register (0-7)         18--16   [LS,M,P,Q] - R0, R7
00257    I  indirect (no disp)      0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
00258    i  indirect (enhanced)     0--7    [LL,LS,M,P,Q,QC] - *+AR0(1), R5
00259    J  indirect (no disp)      8--15   [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
00260    j  indirect (enhanced)     8--15   [M] - *+AR0(1), R5
00261    K  register               19--21   [LL,M,Q,QC] - R0, R7
00262    L  register               22--24   [LL,LS,P,Q,QC] - R0, R7
00263    M  register (R2,R3)       22--22   [M] R2, R3
00264    N  register (R0,R1)       23--23   [M] R0, R1
00265    O  indirect(disp - C4x)    8--15   [S,SC,S2,T,TC,T2] - *+AR0(5)
00266    P  displacement (PC Rel)   0--15   [D,J,JS] - @start, start
00267    Q  register (all)          0--15   [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
00268    q  register (0-11)         0--15   [AF,B,BB] - R0, R7, R11
00269    R  register (all)         16--20   [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
00270    r  register (0-11)        16--20   [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
00271    S  short int immediate     0--15   [A,AB,AY,BI] - -5, 5
00272    T  integer (C4x)          16--20   [Z] - -5, 12
00273    U  unsigned integer        0--15   [AU,A3] - 0, 65535
00274    V  vector (C4x: 0--8)      0--4    [Z] - 25, 7
00275    W  short int (C4x)         0--7    [T,TC,T2,T2C] - -3, 5
00276    X  expansion reg (C4x)     0--4    [Z] - IVTP, TVTP
00277    Y  address reg (C4x)      16--20   [Z] - AR0, DP, SP, IR0
00278    Z  expansion reg (C4x)    16--20   [Z] - IVTP, TVTP
00279 */
00280 
00281 #define TIC4X_OPERANDS_MAX 7       /* Max number of operands for an inst.  */
00282 #define TIC4X_NAME_MAX 16   /* Max number of chars in parallel name.  */
00283 
00284 /* Define the instruction level */
00285 #define OP_C3X   0x1   /* C30 support - supported by all */
00286 #define OP_C4X   0x2   /* C40 support - C40, C44 */
00287 #define OP_ENH   0x4   /* Class LL,LS,M,P,Q,QC enhancements. Argument type
00288                           I and J is enhanced in these classes - C31>=6.0,
00289                           C32>=2.0, C33 */
00290 #define OP_LPWR  0x8   /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
00291                           LC31, C31>=5.0, C32 */
00292 #define OP_IDLE2 0x10  /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
00293                           C32, C33, C40>=5.0, C44 */
00294 
00295 /* The following class definition is a classification scheme for
00296    putting instructions with similar type of arguments together. It
00297    simplifies the op-code definitions significantly, as we then only
00298    need to use the class macroes for 95% of the DSP's opcodes.
00299 */
00300 
00301 /* A: General 2-operand integer operations
00302    Syntax: <i> src, dst
00303       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
00304       dst = Register (R)
00305    Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
00306                 SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
00307                 MBn, MHn, MPYSHI, MPYUHI
00308 */
00309 #define A_CLASS_INSN(name, opcode, level) \
00310   { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
00311   { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
00312   { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
00313   { name, opcode|0x00600000, 0xffe00000, "S,R", level }
00314 
00315 /* AB: General 2-operand integer operation with condition
00316    Syntax: <i>c src, dst
00317        c   = Condition
00318        src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
00319        dst = Register (R)
00320    Instr: 1/0 - LDIc
00321 */
00322 #define AB_CLASS_INSN(name, opcode, level) \
00323   { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
00324   { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
00325   { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
00326   { name, opcode|0x40600000, 0xf0600000, "S,R", level }
00327 
00328 /* AU: General 2-operand unsigned integer operation
00329    Syntax: <i> src, dst
00330         src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
00331         dst = Register (R)
00332    Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
00333 */
00334 #define AU_CLASS_INSN(name, opcode, level) \
00335   { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
00336   { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
00337   { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
00338   { name, opcode|0x00600000, 0xffe00000, "U,R", level }
00339 
00340 /* AF: General 2-operand float to integer operation
00341    Syntax: <i> src, dst
00342         src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
00343         dst = Register (R)
00344    Instr: 1/0 - FIX
00345 */
00346 #define AF_CLASS_INSN(name, opcode, level) \
00347   { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
00348   { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
00349   { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
00350   { name, opcode|0x00600000, 0xffe00000, "F,R", level }
00351 
00352 /* A2: Limited 1-operand (integer) operation
00353    Syntax: <i> src
00354        src = Register (Q), Indirect (*), None
00355    Instr: 1/0 - NOP
00356 */
00357 #define A2_CLASS_INSN(name, opcode, level) \
00358   { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
00359   { name, opcode|0x00400000, 0xffe00000, "*", level }, \
00360   { name, opcode|0x00000000, 0xffe00000, "" , level }
00361 
00362 /* A3: General 1-operand unsigned integer operation
00363    Syntax: <i> src
00364         src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
00365    Instr: 1/0 - RPTS
00366 */
00367 #define A3_CLASS_INSN(name, opcode, level) \
00368   { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
00369   { name, opcode|0x00200000, 0xffff0000, "@", level }, \
00370   { name, opcode|0x00400000, 0xffff0000, "*", level }, \
00371   { name, opcode|0x00600000, 0xffff0000, "U", level }
00372 
00373 /* A6: Limited 2-operand integer operation
00374    Syntax: <i> src, dst
00375        src = Direct (@), Indirect (*)
00376        dst = Register (R)
00377    Instr: 1/1 - LDII, C4x: SIGI
00378 */
00379 #define A6_CLASS_INSN(name, opcode, level) \
00380   { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
00381   { name, opcode|0x00400000, 0xffe00000, "*,R", level }
00382 
00383 /* A7: Limited 2-operand integer store operation
00384    Syntax: <i> src, dst
00385        src = Register (R)
00386        dst = Direct (@), Indirect (*)
00387    Instr: 2/0 - STI, STII
00388 */
00389 #define A7_CLASS_INSN(name, opcode, level) \
00390   { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
00391   { name, opcode|0x00400000, 0xffe00000, "R,*", level }
00392 
00393 /* AY: General 2-operand signed address load operation
00394    Syntax: <i> src, dst
00395         src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
00396         dst = Address register - ARx, IRx, DP, BK, SP (Y)
00397    Instr: 0/1 - C4x: LDA
00398    Note: Q and Y should *never* be the same register
00399 */
00400 #define AY_CLASS_INSN(name, opcode, level) \
00401   { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
00402   { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
00403   { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
00404   { name, opcode|0x00600000, 0xffe00000, "S,Y", level }
00405 
00406 /* B: General 2-operand float operation
00407    Syntax: <i> src, dst
00408        src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
00409        dst = Register 0-11 (r)
00410    Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
00411                  SUBF, SUBRF, C4x: RSQRF, TOIEEE
00412 */
00413 #define B_CLASS_INSN(name, opcode, level) \
00414   { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
00415   { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
00416   { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
00417   { name, opcode|0x00600000, 0xffe00000, "F,r", level }
00418 
00419 /* BA: General 2-operand integer to float operation
00420    Syntax: <i> src, dst
00421        src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
00422        dst = Register 0-11 (r)
00423    Instr: 0/1 - C4x: CRCPF
00424 */
00425 #define BA_CLASS_INSN(name, opcode, level) \
00426   { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
00427   { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
00428   { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
00429   { name, opcode|0x00600000, 0xffe00000, "F,r", level }
00430 
00431 /* BB: General 2-operand conditional float operation
00432    Syntax: <i>c src, dst
00433        c   = Condition
00434        src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
00435        dst = Register 0-11 (r)
00436    Instr: 1/0 - LDFc
00437 */
00438 #define BB_CLASS_INSN(name, opcode, level) \
00439   { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
00440   { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
00441   { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
00442   { name, opcode|0x40600000, 0xf0600000, "F,r", level }
00443 
00444 /* BI: General 2-operand integer to float operation (yet different to BA)
00445    Syntax: <i> src, dst
00446        src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
00447        dst = Register 0-11 (r)
00448    Instr: 1/0 - FLOAT
00449 */
00450 #define BI_CLASS_INSN(name, opcode, level) \
00451   { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
00452   { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
00453   { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
00454   { name, opcode|0x00600000, 0xffe00000, "S,r", level }
00455 
00456 /* B6: Limited 2-operand float operation 
00457    Syntax: <i> src, dst
00458        src = Direct (@), Indirect (*)
00459        dst = Register 0-11 (r)
00460    Instr: 1/1 - LDFI, C4x: FRIEEE
00461 */
00462 #define B6_CLASS_INSN(name, opcode, level) \
00463   { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
00464   { name, opcode|0x00400000, 0xffe00000, "*,r", level }
00465 
00466 /* B7: Limited 2-operand float store operation
00467    Syntax: <i> src, dst
00468        src = Register 0-11 (r)
00469        dst = Direct (@), Indirect (*)
00470    Instr: 2/0 - STF, STFI
00471 */
00472 #define B7_CLASS_INSN(name, opcode, level) \
00473   { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
00474   { name, opcode|0x00400000, 0xffe00000, "r,*", level }
00475 
00476 /* D: Decrement and brach operations
00477    Syntax: <i>c ARn, dst
00478        c   = condition
00479        ARn = AR register 0-7 (A)
00480        dst = Register (Q), PC-relative (P)
00481    Instr: 2/0 - DBc, DBcD
00482    Alias: <name1> <name2>
00483 */
00484 #define D_CLASS_INSN(name1, name2, opcode, level) \
00485   { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
00486   { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
00487   { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
00488   { name2, opcode|0x02000000, 0xfe200000, "A,P", level }
00489 
00490 /* I: General branch operations
00491    Syntax: <i> dst
00492        dst = Address (B)
00493    Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
00494 */
00495 
00496 /* I2: General branch operations (C4x addition)
00497    Syntax: <i> dst
00498        dst = Address (B), C4x: Register (Q)
00499    Instr: 2/0 - RPTB, RPTBD
00500 */
00501 
00502 /* J: General conditional branch operations
00503    Syntax: <i>c dst
00504        c   = Condition
00505        dst = Register (Q), PC-relative (P)
00506    Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
00507    Alias: <name1> <name2>
00508 */
00509 #define J_CLASS_INSN(name1, name2, opcode, level) \
00510   { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
00511   { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
00512   { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
00513   { name2, opcode|0x02000000, 0xffe00000, "P", level }
00514 
00515 /* JS: General conditional branch operations
00516    Syntax: <i>c dst
00517        c   = Condition
00518        dst = Register (Q), PC-relative (P)
00519    Instr: 1/1 - CALLc, C4X: LAJc
00520 */
00521 
00522 /* LL: Load-load parallell operation
00523    Syntax: <i> src2, dst2 || <i> src1, dst1
00524        src1 = Indirect 0,1,IR0,IR1 (J)
00525        dst1 = Register 0-7 (K)
00526        src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
00527        dst2 = Register 0-7 (L)
00528    Instr: 2/0 - LDF||LDF, LDI||LDI
00529    Alias: i||i, i1||i2, i2||i1
00530 */
00531 #define LL_CLASS_INSN(name, opcode, level) \
00532   { name "_"  name    , opcode, 0xfe000000, "i;L|J,K", level }, \
00533   { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
00534   { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
00535 
00536 /* LS: Store-store parallell operation
00537    Syntax: <i> src2, dst2 || <i> src1, dst1
00538        src1 = Register 0-7 (H)
00539        dst1 = Indirect 0,1,IR0,IR1 (J)
00540        src2 = Register 0-7 (L)
00541        dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
00542    Instr: 2/0 - STF||STF, STI||STI
00543    Alias: i||i, i1||i2, i2||i1.
00544 */
00545 #define LS_CLASS_INSN(name, opcode, level) \
00546   { name "_"  name    , opcode, 0xfe000000, "L;i|H,J", level }, \
00547   { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
00548   { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
00549 
00550 /* M: General multiply and add/sub operations
00551    Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
00552            <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
00553            <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
00554            <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
00555            <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
00556            <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
00557        src1 = Register 0-7 (K)
00558        src2 = Register 0-7 (H)
00559        src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
00560        src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
00561        dst1 = Register 0-1 (N)
00562        dst2 = Register 2-3 (M)
00563    Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
00564    Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
00565 */
00566 #define M_CLASS_INSN(namea, nameb, opcode, level) \
00567   { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
00568   { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
00569   { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
00570   { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
00571   { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
00572   { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
00573   { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
00574   { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
00575   { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
00576   { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
00577   { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
00578   { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
00579   { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
00580   { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
00581   { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
00582   { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
00583   { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
00584   { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
00585   { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
00586   { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
00587   { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
00588   { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
00589   { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
00590   { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
00591   { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
00592   { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
00593   { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
00594   { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
00595   { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
00596   { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
00597   { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
00598   { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
00599   { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
00600   { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
00601   { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
00602   { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
00603   { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
00604   { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
00605   { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
00606   { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
00607   { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
00608   { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
00609   { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
00610   { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
00611   { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
00612   { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
00613   { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
00614   { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
00615 
00616 /* P: General 2-operand operation with parallell store
00617    Syntax: <ia> src2, dst1 || <ib> src3, dst2
00618        src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
00619        dst1 = Register 0-7 (L)
00620        src3 = Register 0-7 (H)
00621        dst2 = Indirect 0,1,IR0,IR1 (J)
00622    Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
00623                 LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
00624                 TOIEEE||STF
00625    Alias: a||b, b||a
00626 */
00627 #define P_CLASS_INSN(namea, nameb, opcode, level) \
00628   { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
00629   { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
00630 
00631 /* Q: General 3-operand operation with parallell store
00632    Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
00633        src1 = Register 0-7 (K)
00634        src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
00635        dst1 = Register 0-7 (L)
00636        src3 = Register 0-7 (H)
00637        dst2 = Indirect 0,1,IR0,IR1 (J)
00638    Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
00639    Alias: a||b, b||a, a3||b, b||a3
00640 */
00641 #define Q_CLASS_INSN(namea, nameb, opcode, level) \
00642   { namea "_"  nameb    , opcode, 0xfe000000, "K,i;L|H,J", level }, \
00643   { nameb "_"  namea    , opcode, 0xfe000000, "H,J|K,i;L", level }, \
00644   { namea "3_" nameb    , opcode, 0xfe000000, "K,i;L|H,J", level }, \
00645   { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
00646 
00647 /* QC: General commutative 3-operand operation with parallell store
00648    Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
00649            <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
00650        src1 = Register 0-7 (K)
00651        src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
00652        dst1 = Register 0-7 (L)
00653        src3 = Register 0-7 (H)
00654        dst2 = Indirect 0,1,IR0,IR1 (J)
00655    Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
00656                 OR3||STI, XOR3||STI
00657    Alias: a||b, b||a, a3||b, b||a3
00658 */
00659 #define QC_CLASS_INSN(namea, nameb, opcode, level) \
00660   { namea "_"  nameb    , opcode, 0xfe000000, "i;K;L|H,J", level }, \
00661   { namea "_"  nameb    , opcode, 0xfe000000, "K;i;L|H,J", level }, \
00662   { nameb "_"  namea    , opcode, 0xfe000000, "H,J|i;K;L", level }, \
00663   { nameb "_"  namea    , opcode, 0xfe000000, "H,J|K;i;L", level }, \
00664   { namea "3_" nameb    , opcode, 0xfe000000, "i;K;L|H,J", level }, \
00665   { namea "3_" nameb    , opcode, 0xfe000000, "K;i;L|H,J", level }, \
00666   { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
00667   { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
00668 
00669 /* R: General register integer operation
00670    Syntax: <i> dst
00671        dst = Register (R)
00672    Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
00673 */
00674 #define R_CLASS_INSN(name, opcode, level) \
00675   { name, opcode, 0xffe0ffff, "R", level }
00676 
00677 /* RF: General register float operation
00678    Syntax: <i> dst
00679        dst = Register 0-11 (r)
00680    Instr: 2/0 - POPF, PUSHF
00681 */
00682 #define RF_CLASS_INSN(name, opcode, level) \
00683   { name, opcode, 0xffe0ffff, "r", level }
00684 
00685 /* S: General 3-operand float operation
00686    Syntax: <i> src2, src1, dst
00687        src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
00688        src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
00689        dst  = Register 0-11 (r)
00690    Instr: 1/0 - SUBF3
00691    Alias: i, i3
00692 */
00693 #define S_CLASS_INSN(name, opcode, level) \
00694   { name, opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
00695   { name, opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
00696   { name, opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
00697   { name, opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
00698   { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
00699   { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
00700   { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
00701   { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
00702   { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
00703   { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
00704   { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
00705   { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
00706 
00707 /* SC: General commutative 3-operand float operation
00708    Syntax: <i> src2, src1, dst - Manual
00709            <i> src1, src2, dst
00710        src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
00711        src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
00712        dst  = Register 0-11 (r)
00713    Instr: 2/0 - ADDF3, MPYF3
00714    Alias: i, i3
00715 */
00716 #define SC_CLASS_INSN(name, opcode, level) \
00717   { name, opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
00718   { name, opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
00719   { name, opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
00720   { name, opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
00721   { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
00722   { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
00723   { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
00724   { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
00725   { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
00726   { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
00727   { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
00728   { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
00729   { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
00730   { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
00731 
00732 /* S2: General 3-operand float operation with 2 args
00733    Syntax: <i> src2, src1
00734        src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
00735        src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
00736    Instr: 1/0 - CMPF3
00737    Alias: i, i3
00738 */
00739 #define S2_CLASS_INSN(name, opcode, level) \
00740   { name, opcode|0x20000000, 0xffe00000, "e,g", level  }, \
00741   { name, opcode|0x20200000, 0xffe00000, "e,J", level  }, \
00742   { name, opcode|0x20400000, 0xffe00000, "I,g", level  }, \
00743   { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
00744   { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
00745   { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
00746   { name "3", opcode|0x20000000, 0xffe00000, "e,g", level  }, \
00747   { name "3", opcode|0x20200000, 0xffe00000, "e,J", level  }, \
00748   { name "3", opcode|0x20400000, 0xffe00000, "I,g", level  }, \
00749   { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
00750   { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
00751   { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
00752 
00753 /* T: General 3-operand integer operand
00754    Syntax: <i> src2, src1, dst
00755        src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
00756        src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
00757        dst  = Register (R)
00758    Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
00759    Alias: i, i3
00760 */
00761 #define T_CLASS_INSN(name, opcode, level) \
00762   { name, opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
00763   { name, opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
00764   { name, opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
00765   { name, opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
00766   { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
00767   { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
00768   { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
00769   { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
00770   { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
00771   { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
00772   { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
00773   { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
00774   { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
00775   { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
00776   { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
00777   { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
00778 
00779 /* TC: General commutative 3-operand integer operation
00780    Syntax: <i> src2, src1, dst
00781            <i> src1, src2, dst
00782        src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
00783        src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
00784        dst  = Register (R)
00785    Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
00786    Alias: i, i3
00787 */
00788 #define TC_CLASS_INSN(name, opcode, level) \
00789   { name, opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
00790   { name, opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
00791   { name, opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
00792   { name, opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
00793   { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
00794   { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
00795   { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
00796   { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
00797   { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
00798   { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
00799   { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
00800   { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
00801   { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
00802   { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
00803   { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
00804   { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
00805   { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
00806   { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
00807   { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
00808   { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
00809   { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
00810   { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
00811 
00812 /* T2: General 3-operand integer operation with 2 args
00813    Syntax: <i> src2, src1
00814        src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
00815        src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
00816    Instr: 1/0 - CMPI3
00817    Alias: i, i3
00818 */
00819 #define T2_CLASS_INSN(name, opcode, level) \
00820   { name, opcode|0x20000000, 0xffe00000, "E,G", level  }, \
00821   { name, opcode|0x20200000, 0xffe00000, "E,J", level  }, \
00822   { name, opcode|0x20400000, 0xffe00000, "I,G", level  }, \
00823   { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
00824   { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
00825   { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
00826   { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
00827   { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
00828   { name "3", opcode|0x20000000, 0xffe00000, "E,G", level  }, \
00829   { name "3", opcode|0x20200000, 0xffe00000, "E,J", level  }, \
00830   { name "3", opcode|0x20400000, 0xffe00000, "I,G", level  }, \
00831   { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
00832   { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
00833   { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
00834   { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
00835   { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
00836 
00837 /* T2C: General commutative 3-operand integer operation with 2 args 
00838    Syntax: <i> src2, src1 - Manual
00839            <i> src1, src2 
00840        src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
00841        src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
00842    Instr: 1/0 - TSTB3
00843    Alias: i, i3
00844 */
00845 #define T2C_CLASS_INSN(name, opcode, level) \
00846   { name, opcode|0x20000000, 0xffe00000, "E,G", level  }, \
00847   { name, opcode|0x20200000, 0xffe00000, "E,J", level  }, \
00848   { name, opcode|0x20400000, 0xffe00000, "I,G", level  }, \
00849   { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
00850   { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
00851   { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
00852   { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
00853   { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
00854   { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
00855   { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
00856   { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
00857   { name "3", opcode|0x20000000, 0xffe00000, "E,G", level  }, \
00858   { name "3", opcode|0x20200000, 0xffe00000, "E,J", level  }, \
00859   { name "3", opcode|0x20400000, 0xffe00000, "I,G", level  }, \
00860   { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
00861   { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
00862   { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
00863   { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
00864   { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
00865   { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
00866   { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
00867   { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
00868 
00869 /* Z: Misc operations with or without arguments
00870    Syntax: <i> <arg1>,...
00871    Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, 
00872                TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK
00873 */
00874 
00875 
00876 /* Define tic4x opcodes for assembler and disassembler.  */
00877 static const tic4x_inst_t tic4x_insts[] =
00878 {
00879   /* Put synonyms after the desired forms in table so that they get
00880      overwritten in the lookup table.  The disassembler will thus
00881      print the `proper' mnemonics.  Note that the disassembler
00882      only decodes the 11 MSBs, so instructions like ldp @0x500 will
00883      be printed as ldiu 5, dp.  Note that with parallel instructions,
00884      the second part is executed before the first part, unless
00885      the sti1||sti2 form is used.  We also allow sti2||sti1
00886      which is equivalent to the default sti||sti form.
00887   */
00888   B_CLASS_INSN(  "absf",          0x00000000, OP_C3X   ),
00889   P_CLASS_INSN(  "absf",  "stf",  0xc8000000, OP_C3X   ),
00890   A_CLASS_INSN(  "absi",          0x00800000, OP_C3X   ),
00891   P_CLASS_INSN(  "absi",  "sti",  0xca000000, OP_C3X   ),
00892   A_CLASS_INSN(  "addc",          0x01000000, OP_C3X   ),
00893   TC_CLASS_INSN( "addc",          0x00000000, OP_C3X   ),
00894   B_CLASS_INSN(  "addf",          0x01800000, OP_C3X   ),
00895   SC_CLASS_INSN( "addf",          0x00800000, OP_C3X   ),
00896   QC_CLASS_INSN( "addf",  "stf",  0xcc000000, OP_C3X   ),
00897   A_CLASS_INSN(  "addi",          0x02000000, OP_C3X   ),
00898   TC_CLASS_INSN( "addi",          0x01000000, OP_C3X   ),
00899   QC_CLASS_INSN( "addi",  "sti",  0xce000000, OP_C3X   ),
00900   AU_CLASS_INSN( "and",           0x02800000, OP_C3X   ),
00901   TC_CLASS_INSN( "and",           0x01800000, OP_C3X   ),
00902   QC_CLASS_INSN( "and",   "sti",  0xd0000000, OP_C3X   ),
00903   AU_CLASS_INSN( "andn",          0x03000000, OP_C3X   ),
00904   T_CLASS_INSN(  "andn",          0x02000000, OP_C3X   ),
00905   A_CLASS_INSN(  "ash",           0x03800000, OP_C3X   ),
00906   T_CLASS_INSN(  "ash",           0x02800000, OP_C3X   ),
00907   Q_CLASS_INSN(  "ash",   "sti",  0xd2000000, OP_C3X   ),
00908   J_CLASS_INSN(  "bB",    "b",    0x68000000, OP_C3X   ),
00909   J_CLASS_INSN(  "bBd",   "bd",   0x68200000, OP_C3X   ),
00910   J_CLASS_INSN(  "bBaf",  "baf",  0x68a00000, OP_C4X   ),
00911   J_CLASS_INSN(  "bBat",  "bat",  0x68600000, OP_C4X   ),
00912   { "br",     0x60000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
00913   { "brd",    0x61000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
00914   { "call",   0x62000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
00915   { "callB",  0x70000000, 0xffe00000, "Q"   , OP_C3X   },  /* JS_CLASS */
00916   { "callB",  0x72000000, 0xffe00000, "P"   , OP_C3X   },  /* JS_CLASS */
00917   B_CLASS_INSN(  "cmpf",          0x04000000, OP_C3X   ),
00918   S2_CLASS_INSN( "cmpf",          0x03000000, OP_C3X   ),
00919   A_CLASS_INSN(  "cmpi",          0x04800000, OP_C3X   ),
00920   T2_CLASS_INSN( "cmpi",          0x03800000, OP_C3X   ),
00921   D_CLASS_INSN(  "dbB",   "db",   0x6c000000, OP_C3X   ),
00922   D_CLASS_INSN(  "dbBd",  "dbd",  0x6c200000, OP_C3X   ),
00923   AF_CLASS_INSN( "fix",           0x05000000, OP_C3X   ),
00924   P_CLASS_INSN(  "fix",   "sti",  0xd4000000, OP_C3X   ),
00925   BI_CLASS_INSN( "float",         0x05800000, OP_C3X   ),
00926   P_CLASS_INSN(  "float", "stf",  0xd6000000, OP_C3X   ),
00927   B6_CLASS_INSN( "frieee",        0x1c000000, OP_C4X   ),
00928   P_CLASS_INSN(  "frieee","stf",  0xf2000000, OP_C4X   ),
00929   { "iack",   0x1b200000, 0xffe00000, "@"   , OP_C3X   },  /* Z_CLASS */
00930   { "iack",   0x1b400000, 0xffe00000, "*"   , OP_C3X   },  /* Z_CLASS */
00931   { "idle",   0x06000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
00932   { "idlez",  0x06000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
00933   { "idle2",  0x06000001, 0xffffffff, ""    , OP_IDLE2 },  /* Z_CLASS */
00934   { "laj",    0x63000000, 0xff000000, "B"   , OP_C4X   },  /* I_CLASS */
00935   { "lajB",   0x70200000, 0xffe00000, "Q"   , OP_C4X   },  /* JS_CLASS */
00936   { "lajB",   0x72200000, 0xffe00000, "P"   , OP_C4X   },  /* JS_CLASS */
00937   { "latB",   0x74800000, 0xffe00000, "V"   , OP_C4X   },  /* Z_CLASS */
00938   A_CLASS_INSN(  "lb0",           0xb0000000, OP_C4X   ),
00939   A_CLASS_INSN(  "lb1",           0xb0800000, OP_C4X   ),
00940   A_CLASS_INSN(  "lb2",           0xb1000000, OP_C4X   ),
00941   A_CLASS_INSN(  "lb3",           0xb1800000, OP_C4X   ),
00942   AU_CLASS_INSN( "lbu0",          0xb2000000, OP_C4X   ),
00943   AU_CLASS_INSN( "lbu1",          0xb2800000, OP_C4X   ),
00944   AU_CLASS_INSN( "lbu2",          0xb3000000, OP_C4X   ),
00945   AU_CLASS_INSN( "lbu3",          0xb3800000, OP_C4X   ),
00946   AY_CLASS_INSN( "lda",           0x1e800000, OP_C4X   ),
00947   B_CLASS_INSN(  "lde",           0x06800000, OP_C3X   ),
00948   { "ldep",   0x76000000, 0xffe00000, "X,R" , OP_C4X   },  /* Z_CLASS */
00949   B_CLASS_INSN(  "ldf",           0x07000000, OP_C3X   ),
00950   LL_CLASS_INSN( "ldf",           0xc4000000, OP_C3X   ),
00951   P_CLASS_INSN(  "ldf",   "stf",  0xd8000000, OP_C3X   ),
00952   BB_CLASS_INSN( "ldfC",          0x00000000, OP_C3X   ),
00953   B6_CLASS_INSN( "ldfi",          0x07800000, OP_C3X   ),
00954   { "ldhi",   0x1fe00000, 0xffe00000, "U,R" , OP_C4X   },  /* Z_CLASS */
00955   { "ldhi",   0x1fe00000, 0xffe00000, "#,R" , OP_C4X   },  /* Z_CLASS */
00956   A_CLASS_INSN(  "ldi",           0x08000000, OP_C3X   ),
00957   LL_CLASS_INSN( "ldi",           0xc6000000, OP_C3X   ),
00958   P_CLASS_INSN(  "ldi",   "sti",  0xda000000, OP_C3X   ),
00959   AB_CLASS_INSN( "ldiC",          0x10000000, OP_C3X   ),
00960   A6_CLASS_INSN( "ldii",          0x08800000, OP_C3X   ),
00961   { "ldp",    0x50700000, 0xffff0000, "#"   , OP_C3X   },  /* Z_CLASS - synonym for ldiu #,dp */
00962   B_CLASS_INSN(  "ldm",           0x09000000, OP_C3X   ),
00963   { "ldpe",   0x76800000, 0xffe00000, "Q,Z" , OP_C4X   },  /* Z_CLASS */
00964   { "ldpk",   0x1F700000, 0xffff0000, "#"   , OP_C4X   },  /* Z_CLASS */
00965   A_CLASS_INSN(  "lh0",           0xba000000, OP_C4X   ),
00966   A_CLASS_INSN(  "lh1",           0xba800000, OP_C4X   ),
00967   AU_CLASS_INSN( "lhu0",          0xbb000000, OP_C4X   ),
00968   AU_CLASS_INSN( "lhu1",          0xbb800000, OP_C4X   ),
00969   { "lopower", 0x10800001,0xffffffff, ""    , OP_LPWR  },  /* Z_CLASS */
00970   A_CLASS_INSN(  "lsh",           0x09800000, OP_C3X   ),
00971   T_CLASS_INSN(  "lsh",           0x04000000, OP_C3X   ),
00972   Q_CLASS_INSN(  "lsh",   "sti",  0xdc000000, OP_C3X   ),
00973   A_CLASS_INSN(  "lwl0",          0xb4000000, OP_C4X   ),
00974   A_CLASS_INSN(  "lwl1",          0xb4800000, OP_C4X   ),
00975   A_CLASS_INSN(  "lwl2",          0xb5000000, OP_C4X   ),
00976   A_CLASS_INSN(  "lwl3",          0xb5800000, OP_C4X   ),
00977   A_CLASS_INSN(  "lwr0",          0xb6000000, OP_C4X   ),
00978   A_CLASS_INSN(  "lwr1",          0xb6800000, OP_C4X   ),
00979   A_CLASS_INSN(  "lwr2",          0xb7000000, OP_C4X   ),
00980   A_CLASS_INSN(  "lwr3",          0xb7800000, OP_C4X   ),
00981   { "maxspeed",0x10800000,0xffffffff, ""    , OP_LPWR  },  /* Z_CLASS */
00982   A_CLASS_INSN(  "mb0",           0xb8000000, OP_C4X   ),
00983   A_CLASS_INSN(  "mb1",           0xb8800000, OP_C4X   ),
00984   A_CLASS_INSN(  "mb2",           0xb9000000, OP_C4X   ),
00985   A_CLASS_INSN(  "mb3",           0xb9800000, OP_C4X   ),
00986   A_CLASS_INSN(  "mh0",           0xbc000000, OP_C4X   ),
00987   A_CLASS_INSN(  "mh1",           0xbc800000, OP_C4X   ),
00988   A_CLASS_INSN(  "mh2",           0xbd000000, OP_C4X   ),
00989   A_CLASS_INSN(  "mh3",           0xbd800000, OP_C4X   ),
00990   B_CLASS_INSN(  "mpyf",          0x0a000000, OP_C3X   ),
00991   SC_CLASS_INSN( "mpyf",          0x04800000, OP_C3X   ),
00992   M_CLASS_INSN(  "mpyf",  "addf", 0x80000000, OP_C3X   ),
00993   QC_CLASS_INSN( "mpyf",  "stf",  0xde000000, OP_C3X   ),
00994   M_CLASS_INSN(  "mpyf",  "subf", 0x84000000, OP_C3X   ),
00995   A_CLASS_INSN(  "mpyi",          0x0a800000, OP_C3X   ),
00996   TC_CLASS_INSN( "mpyi",          0x05000000, OP_C3X   ),
00997   M_CLASS_INSN(  "mpyi",  "addi", 0x88000000, OP_C3X   ),
00998   QC_CLASS_INSN( "mpyi",  "sti",  0xe0000000, OP_C3X   ),
00999   M_CLASS_INSN(  "mpyi",  "subi", 0x8c000000, OP_C3X   ),
01000   A_CLASS_INSN(  "mpyshi",        0x1d800000, OP_C4X   ),
01001   TC_CLASS_INSN( "mpyshi",        0x28800000, OP_C4X   ),
01002   A_CLASS_INSN(  "mpyuhi",        0x1e000000, OP_C4X   ),
01003   TC_CLASS_INSN( "mpyuhi",        0x29000000, OP_C4X   ),
01004   A_CLASS_INSN(  "negb",          0x0b000000, OP_C3X   ),
01005   B_CLASS_INSN(  "negf",          0x0b800000, OP_C3X   ),
01006   P_CLASS_INSN(  "negf",  "stf",  0xe2000000, OP_C3X   ),
01007   A_CLASS_INSN(  "negi",          0x0c000000, OP_C3X   ),
01008   P_CLASS_INSN(  "negi",  "sti",  0xe4000000, OP_C3X   ),
01009   A2_CLASS_INSN( "nop",           0x0c800000, OP_C3X   ),
01010   B_CLASS_INSN(  "norm",          0x0d000000, OP_C3X   ),
01011   AU_CLASS_INSN( "not",           0x0d800000, OP_C3X   ),
01012   P_CLASS_INSN(  "not",   "sti",  0xe6000000, OP_C3X   ),
01013   AU_CLASS_INSN( "or",            0x10000000, OP_C3X   ),
01014   TC_CLASS_INSN( "or",            0x05800000, OP_C3X   ),
01015   QC_CLASS_INSN( "or",    "sti",  0xe8000000, OP_C3X   ),
01016   R_CLASS_INSN(  "pop",           0x0e200000, OP_C3X   ),
01017   RF_CLASS_INSN( "popf",          0x0ea00000, OP_C3X   ),
01018   R_CLASS_INSN(  "push",          0x0f200000, OP_C3X   ),
01019   RF_CLASS_INSN( "pushf",         0x0fa00000, OP_C3X   ),
01020   BA_CLASS_INSN( "rcpf",          0x1d000000, OP_C4X   ),
01021   { "retiB",  0x78000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
01022   { "reti",   0x78000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS  - Alias for retiu */
01023   { "retiBd", 0x78200000, 0xffe00000, ""    , OP_C4X   },  /* Z_CLASS */
01024   { "retid",  0x78200000, 0xffe00000, ""    , OP_C4X   },  /* Z_CLASS - Alias for retiud */
01025   { "retsB",  0x78800000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
01026   { "rets",   0x78800000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS  - Alias for retsu */
01027   B_CLASS_INSN(  "rnd",           0x11000000, OP_C3X   ),
01028   R_CLASS_INSN(  "rol",           0x11e00001, OP_C3X   ),
01029   R_CLASS_INSN(  "rolc",          0x12600001, OP_C3X   ),
01030   R_CLASS_INSN(  "ror",           0x12e0ffff, OP_C3X   ),
01031   R_CLASS_INSN(  "rorc",          0x1360ffff, OP_C3X   ),
01032   { "rptb",   0x64000000, 0xff000000, "B"   , OP_C3X   },  /* I2_CLASS */
01033   { "rptb",   0x79000000, 0xff000000, "Q"   , OP_C4X   },  /* I2_CLASS */
01034   { "rptbd",  0x65000000, 0xff000000, "B"   , OP_C4X   },  /* I2_CLASS */ 
01035   { "rptbd",  0x79800000, 0xff000000, "Q"   , OP_C4X   },  /* I2_CLASS */
01036   A3_CLASS_INSN( "rpts",          0x139b0000, OP_C3X   ),
01037   B_CLASS_INSN(  "rsqrf",         0x1c800000, OP_C4X   ),
01038   { "sigi",   0x16000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
01039   A6_CLASS_INSN( "sigi",          0x16000000, OP_C4X   ),
01040   B7_CLASS_INSN( "stf",           0x14000000, OP_C3X   ),
01041   LS_CLASS_INSN( "stf",           0xc0000000, OP_C3X   ),
01042   B7_CLASS_INSN( "stfi",          0x14800000, OP_C3X   ),
01043   A7_CLASS_INSN( "sti",           0x15000000, OP_C3X   ),
01044   { "sti",    0x15000000, 0xffe00000, "T,@" , OP_C4X   },  /* Class A7 - Alias for stik */
01045   { "sti",    0x15600000, 0xffe00000, "T,*" , OP_C4X   },  /* Class A7 */
01046   LS_CLASS_INSN( "sti",           0xc2000000, OP_C3X   ),
01047   A7_CLASS_INSN( "stii",          0x15800000, OP_C3X   ),
01048   { "stik",   0x15000000, 0xffe00000, "T,@" , OP_C4X   },  /* Z_CLASS */
01049   { "stik",   0x15600000, 0xffe00000, "T,*" , OP_C4X   },  /* Z_CLASS */
01050   A_CLASS_INSN(  "subb",          0x16800000, OP_C3X   ),
01051   T_CLASS_INSN(  "subb",          0x06000000, OP_C3X   ),
01052   A_CLASS_INSN(  "subc",          0x17000000, OP_C3X   ),
01053   B_CLASS_INSN(  "subf",          0x17800000, OP_C3X   ),
01054   S_CLASS_INSN(  "subf",          0x06800000, OP_C3X   ),
01055   Q_CLASS_INSN(  "subf",  "stf",  0xea000000, OP_C3X   ),
01056   A_CLASS_INSN(  "subi",          0x18000000, OP_C3X   ),
01057   T_CLASS_INSN(  "subi",          0x07000000, OP_C3X   ),
01058   Q_CLASS_INSN(  "subi",  "sti",  0xec000000, OP_C3X   ),
01059   A_CLASS_INSN(  "subrb",         0x18800000, OP_C3X   ),
01060   B_CLASS_INSN(  "subrf",         0x19000000, OP_C3X   ),
01061   A_CLASS_INSN(  "subri",         0x19800000, OP_C3X   ),
01062   { "swi",    0x66000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
01063   B_CLASS_INSN(  "toieee",        0x1b800000, OP_C4X   ),
01064   P_CLASS_INSN(  "toieee","stf",  0xf0000000, OP_C4X   ),
01065   { "trapB",  0x74000000, 0xffe00000, "V"   , OP_C3X   },  /* Z_CLASS */
01066   { "trap",   0x74000000, 0xffe00000, "V"   , OP_C3X   },  /* Z_CLASS - Alias for trapu */
01067   AU_CLASS_INSN( "tstb",          0x1a000000, OP_C3X   ),
01068   T2C_CLASS_INSN("tstb",          0x07800000, OP_C3X   ),
01069   AU_CLASS_INSN( "xor",           0x1a800000, OP_C3X   ),
01070   TC_CLASS_INSN( "xor",           0x08000000, OP_C3X   ),
01071   QC_CLASS_INSN( "xor",   "sti",  0xee000000, OP_C3X   ),
01072 
01073   /* Dummy entry, not included in tic4x_num_insts.  This
01074      lets code examine entry i + 1 without checking
01075      if we've run off the end of the table.  */
01076   { "",      0x0, 0x00, "", 0 }
01077 };
01078 
01079 const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);