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cell-binutils  2.17cvs20070401
tic30.h
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00001 /* tic30.h -- Header file for TI TMS320C30 opcode table
00002    Copyright 1998 Free Software Foundation, Inc.
00003    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
00004 
00005 This file is part of GDB, GAS, and the GNU binutils.
00006 
00007 GDB, GAS, and the GNU binutils are free software; you can redistribute
00008 them and/or modify them under the terms of the GNU General Public
00009 License as published by the Free Software Foundation; either version
00010 1, or (at your option) any later version.
00011 
00012 GDB, GAS, and the GNU binutils are distributed in the hope that they
00013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015 the GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this file; see the file COPYING.  If not, write to the Free
00019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00020 02110-1301, USA.  */
00021 
00022 /* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
00023    header file.  */
00024 
00025 #ifndef _TMS320_H_
00026 #define _TMS320_H_
00027 
00028 struct _register
00029 {
00030   char *name;
00031   unsigned char opcode;
00032   unsigned char regtype;
00033 };
00034 
00035 typedef struct _register reg;
00036 
00037 #define REG_Rn    0x01
00038 #define REG_ARn   0x02
00039 #define REG_DP    0x03
00040 #define REG_OTHER 0x04
00041 
00042 static const reg tic30_regtab[] = {
00043   { "r0", 0x00, REG_Rn },
00044   { "r1", 0x01, REG_Rn },
00045   { "r2", 0x02, REG_Rn },
00046   { "r3", 0x03, REG_Rn },
00047   { "r4", 0x04, REG_Rn },
00048   { "r5", 0x05, REG_Rn },
00049   { "r6", 0x06, REG_Rn },
00050   { "r7", 0x07, REG_Rn },
00051   { "ar0",0x08, REG_ARn },
00052   { "ar1",0x09, REG_ARn },
00053   { "ar2",0x0A, REG_ARn },
00054   { "ar3",0x0B, REG_ARn },
00055   { "ar4",0x0C, REG_ARn },
00056   { "ar5",0x0D, REG_ARn },
00057   { "ar6",0x0E, REG_ARn },
00058   { "ar7",0x0F, REG_ARn },
00059   { "dp", 0x10, REG_DP },
00060   { "ir0",0x11, REG_OTHER },
00061   { "ir1",0x12, REG_OTHER },
00062   { "bk", 0x13, REG_OTHER },
00063   { "sp", 0x14, REG_OTHER },
00064   { "st", 0x15, REG_OTHER },
00065   { "ie", 0x16, REG_OTHER },
00066   { "if", 0x17, REG_OTHER },
00067   { "iof",0x18, REG_OTHER },
00068   { "rs", 0x19, REG_OTHER },
00069   { "re", 0x1A, REG_OTHER },
00070   { "rc", 0x1B, REG_OTHER },
00071   { "R0", 0x00, REG_Rn },
00072   { "R1", 0x01, REG_Rn },
00073   { "R2", 0x02, REG_Rn },
00074   { "R3", 0x03, REG_Rn },
00075   { "R4", 0x04, REG_Rn },
00076   { "R5", 0x05, REG_Rn },
00077   { "R6", 0x06, REG_Rn },
00078   { "R7", 0x07, REG_Rn },
00079   { "AR0",0x08, REG_ARn },
00080   { "AR1",0x09, REG_ARn },
00081   { "AR2",0x0A, REG_ARn },
00082   { "AR3",0x0B, REG_ARn },
00083   { "AR4",0x0C, REG_ARn },
00084   { "AR5",0x0D, REG_ARn },
00085   { "AR6",0x0E, REG_ARn },
00086   { "AR7",0x0F, REG_ARn },
00087   { "DP", 0x10, REG_DP },
00088   { "IR0",0x11, REG_OTHER },
00089   { "IR1",0x12, REG_OTHER },
00090   { "BK", 0x13, REG_OTHER },
00091   { "SP", 0x14, REG_OTHER },
00092   { "ST", 0x15, REG_OTHER },
00093   { "IE", 0x16, REG_OTHER },
00094   { "IF", 0x17, REG_OTHER },
00095   { "IOF",0x18, REG_OTHER },
00096   { "RS", 0x19, REG_OTHER },
00097   { "RE", 0x1A, REG_OTHER },
00098   { "RC", 0x1B, REG_OTHER },
00099   { "",   0, 0 }
00100 };
00101 
00102 static const reg *const tic30_regtab_end
00103   = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);
00104 
00105 /* Indirect Addressing Modes Modification Fields */
00106 /* Indirect Addressing with Displacement */
00107 #define PreDisp_Add        0x00
00108 #define PreDisp_Sub        0x01
00109 #define PreDisp_Add_Mod    0x02
00110 #define PreDisp_Sub_Mod    0x03
00111 #define PostDisp_Add_Mod   0x04
00112 #define PostDisp_Sub_Mod   0x05
00113 #define PostDisp_Add_Circ  0x06
00114 #define PostDisp_Sub_Circ  0x07
00115 /* Indirect Addressing with Index Register IR0 */
00116 #define PreIR0_Add         0x08
00117 #define PreIR0_Sub         0x09
00118 #define PreIR0_Add_Mod     0x0A
00119 #define PreIR0_Sub_Mod     0x0B
00120 #define PostIR0_Add_Mod    0x0C
00121 #define PostIR0_Sub_Mod    0x0D
00122 #define PostIR0_Add_Circ   0x0E
00123 #define PostIR0_Sub_Circ   0x0F
00124 /* Indirect Addressing with Index Register IR1 */
00125 #define PreIR1_Add         0x10
00126 #define PreIR1_Sub         0x11
00127 #define PreIR1_Add_Mod     0x12
00128 #define PreIR1_Sub_Mod     0x13
00129 #define PostIR1_Add_Mod    0x14
00130 #define PostIR1_Sub_Mod    0x15
00131 #define PostIR1_Add_Circ   0x16
00132 #define PostIR1_Sub_Circ   0x17
00133 /* Indirect Addressing (Special Cases) */
00134 #define IndirectOnly       0x18
00135 #define PostIR0_Add_BitRev 0x19
00136 
00137 typedef struct {
00138   char *syntax;
00139   unsigned char modfield;
00140   unsigned char displacement;
00141 } ind_addr_type;
00142 
00143 #define IMPLIED_DISP  0x01
00144 #define DISP_REQUIRED 0x02
00145 #define NO_DISP       0x03
00146 
00147 static const ind_addr_type tic30_indaddr_tab[] = {
00148   { "*+ar",       PreDisp_Add,        IMPLIED_DISP },
00149   { "*-ar",       PreDisp_Sub,        IMPLIED_DISP },
00150   { "*++ar",      PreDisp_Add_Mod,    IMPLIED_DISP },
00151   { "*--ar",      PreDisp_Sub_Mod,    IMPLIED_DISP },
00152   { "*ar++",      PostDisp_Add_Mod,   IMPLIED_DISP },
00153   { "*ar--",      PostDisp_Sub_Mod,   IMPLIED_DISP },
00154   { "*ar++%",     PostDisp_Add_Circ,  IMPLIED_DISP },
00155   { "*ar--%",     PostDisp_Sub_Circ,  IMPLIED_DISP },
00156   { "*+ar()",     PreDisp_Add,        DISP_REQUIRED },
00157   { "*-ar()",     PreDisp_Sub,        DISP_REQUIRED },
00158   { "*++ar()",    PreDisp_Add_Mod,    DISP_REQUIRED },
00159   { "*--ar()",    PreDisp_Sub_Mod,    DISP_REQUIRED },
00160   { "*ar++()",    PostDisp_Add_Mod,   DISP_REQUIRED },
00161   { "*ar--()",    PostDisp_Sub_Mod,   DISP_REQUIRED },
00162   { "*ar++()%",   PostDisp_Add_Circ,  DISP_REQUIRED },
00163   { "*ar--()%",   PostDisp_Sub_Circ,  DISP_REQUIRED },
00164   { "*+ar(ir0)",  PreIR0_Add,         NO_DISP },
00165   { "*-ar(ir0)",  PreIR0_Sub,         NO_DISP },
00166   { "*++ar(ir0)", PreIR0_Add_Mod,     NO_DISP },
00167   { "*--ar(ir0)", PreIR0_Sub_Mod,     NO_DISP },
00168   { "*ar++(ir0)", PostIR0_Add_Mod,    NO_DISP },
00169   { "*ar--(ir0)", PostIR0_Sub_Mod,    NO_DISP },
00170   { "*ar++(ir0)%",PostIR0_Add_Circ,   NO_DISP },
00171   { "*ar--(ir0)%",PostIR0_Sub_Circ,   NO_DISP },
00172   { "*+ar(ir1)",  PreIR1_Add,         NO_DISP },
00173   { "*-ar(ir1)",  PreIR1_Sub,         NO_DISP },
00174   { "*++ar(ir1)", PreIR1_Add_Mod,     NO_DISP },
00175   { "*--ar(ir1)", PreIR1_Sub_Mod,     NO_DISP },
00176   { "*ar++(ir1)", PostIR1_Add_Mod,    NO_DISP },
00177   { "*ar--(ir1)", PostIR1_Sub_Mod,    NO_DISP },
00178   { "*ar++(ir1)%",PostIR1_Add_Circ,   NO_DISP },
00179   { "*ar--(ir1)%",PostIR1_Sub_Circ,   NO_DISP },
00180   { "*ar",        IndirectOnly,       NO_DISP },
00181   { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
00182   { "",           0,0 }
00183 };
00184 
00185 static const ind_addr_type *const tic30_indaddrtab_end
00186   = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);
00187 
00188 /* Possible operand types */
00189 /* Register types */
00190 #define Rn       0x0001
00191 #define ARn      0x0002
00192 #define DPReg    0x0004
00193 #define OtherReg 0x0008
00194 /* Addressing mode types */
00195 #define Direct   0x0010
00196 #define Indirect 0x0020
00197 #define Imm16    0x0040
00198 #define Disp     0x0080
00199 #define Imm24    0x0100
00200 #define Abs24    0x0200
00201 /* 3 operand addressing mode types */
00202 #define op3T1    0x0400
00203 #define op3T2    0x0800
00204 /* Interrupt vector */
00205 #define IVector  0x1000
00206 /* Not required */
00207 #define NotReq   0x2000
00208 
00209 #define GAddr1   Rn | Direct | Indirect | Imm16
00210 #define GAddr2   GAddr1 | AllReg
00211 #define TAddr1   op3T1 | Rn | Indirect
00212 #define TAddr2   op3T2 | Rn | Indirect
00213 #define Reg      Rn | ARn
00214 #define AllReg   Reg | DPReg | OtherReg
00215 
00216 typedef struct _template
00217 {
00218   char *name;
00219   unsigned int operands; /* how many operands */
00220   unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
00221   /* the bits in opcode_modifier are used to generate the final opcode from
00222      the base_opcode.  These bits also are used to detect alternate forms of
00223      the same instruction */
00224   unsigned int opcode_modifier;
00225 
00226   /* opcode_modifier bits: */
00227 #define AddressMode 0x00600000
00228 #define PCRel       0x02000000
00229 #define StackOp     0x001F0000
00230 #define Rotate      StackOp
00231   
00232   /* operand_types[i] describes the type of operand i.  This is made
00233      by OR'ing together all of the possible type masks.  (e.g.
00234      'operand_types[i] = Reg|Imm' specifies that operand i can be
00235      either a register or an immediate operand */
00236   unsigned int operand_types[3];
00237   /* This defines the number type of an immediate argument to an instruction. */
00238   int imm_arg_type;
00239 #define Imm_None  0
00240 #define Imm_Float 1
00241 #define Imm_SInt  2
00242 #define Imm_UInt  3
00243 }
00244 template;
00245 
00246 static const template tic30_optab[] = {
00247   { "absf"   ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00248   { "absi"   ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00249   { "addc"   ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00250   { "addc3"  ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00251   { "addf"   ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00252   { "addf3"  ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
00253   { "addi"   ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00254   { "addi3"  ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00255   { "and"    ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00256   { "and3"   ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00257   { "andn"   ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00258   { "andn3"  ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00259   { "ash"    ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00260   { "ash3"   ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00261   { "b"      ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00262   { "bu"     ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00263   { "blo"    ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00264   { "bls"    ,1,0x68020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00265   { "bhi"    ,1,0x68030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00266   { "bhs"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00267   { "beq"    ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00268   { "bne"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00269   { "blt"    ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00270   { "ble"    ,1,0x68080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00271   { "bgt"    ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00272   { "bge"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00273   { "bz"     ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00274   { "bnz"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00275   { "bp"     ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00276   { "bn"     ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00277   { "bnn"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00278   { "bnv"    ,1,0x680C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00279   { "bv"     ,1,0x680D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00280   { "bnuf"   ,1,0x680E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00281   { "buf"    ,1,0x680F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00282   { "bnc"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00283   { "bc"     ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00284   { "bnlv"   ,1,0x68100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00285   { "blv"    ,1,0x68110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00286   { "bnluf"  ,1,0x68120000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00287   { "bluf"   ,1,0x68130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00288   { "bzuf"   ,1,0x68140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00289   { "bd"     ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00290   { "bud"    ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00291   { "blod"   ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00292   { "blsd"   ,1,0x68220000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00293   { "bhid"   ,1,0x68230000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00294   { "bhsd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00295   { "beqd"   ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00296   { "bned"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00297   { "bltd"   ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00298   { "bled"   ,1,0x68280000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00299   { "bgtd"   ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00300   { "bged"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00301   { "bzd"    ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00302   { "bnzd"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00303   { "bpd"    ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00304   { "bnd"    ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00305   { "bnnd"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00306   { "bnvd"   ,1,0x682C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00307   { "bvd"    ,1,0x682D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00308   { "bnufd"  ,1,0x682E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00309   { "bufd"   ,1,0x682F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00310   { "bncd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00311   { "bcd"    ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00312   { "bnlvd"  ,1,0x68300000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00313   { "blvd"   ,1,0x68310000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00314   { "bnlufd" ,1,0x68320000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00315   { "blufd"  ,1,0x68330000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00316   { "bzufd"  ,1,0x68340000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
00317   { "br"     ,1,0x60000000,0,           { Imm24, 0, 0 }, Imm_UInt },
00318   { "brd"    ,1,0x61000000,0,           { Imm24, 0, 0 }, Imm_UInt },
00319   { "call"   ,1,0x62000000,0,           { Imm24, 0, 0 }, Imm_UInt },
00320   { "callu"  ,1,0x70000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00321   { "calllo" ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00322   { "callls" ,1,0x70020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00323   { "callhi" ,1,0x70030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00324   { "callhs" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00325   { "calleq" ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00326   { "callne" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00327   { "calllt" ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00328   { "callle" ,1,0x70080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00329   { "callgt" ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00330   { "callge" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00331   { "callz"  ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00332   { "callnz" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00333   { "callp"  ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00334   { "calln"  ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00335   { "callnn" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00336   { "callnv" ,1,0x700C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00337   { "callv"  ,1,0x700D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00338   { "callnuf",1,0x700E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00339   { "calluf" ,1,0x700F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00340   { "callnc" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00341   { "callc"  ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00342   { "callnlv",1,0x70100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00343   { "calllv" ,1,0x70110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00344   { "callnluf",1,0x70120000,PCRel,      { AllReg|Disp, 0, 0 }, Imm_UInt },
00345   { "callluf",1,0x70130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00346   { "callzuf",1,0x70140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
00347   { "cmpf"   ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00348   { "cmpf3"  ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None },
00349   { "cmpi"   ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00350   { "cmpi3"  ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
00351   { "db"     ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00352   { "dbu"    ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00353   { "dblo"   ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00354   { "dbls"   ,2,0x6C020000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00355   { "dbhi"   ,2,0x6C030000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00356   { "dbhs"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00357   { "dbeq"   ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00358   { "dbne"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00359   { "dblt"   ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00360   { "dble"   ,2,0x6C080000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00361   { "dbgt"   ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00362   { "dbge"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00363   { "dbz"    ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00364   { "dbnz"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00365   { "dbp"    ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00366   { "dbn"    ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00367   { "dbnn"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00368   { "dbnv"   ,2,0x6C0C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00369   { "dbv"    ,2,0x6C0D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00370   { "dbnuf"  ,2,0x6C0E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00371   { "dbuf"   ,2,0x6C0F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00372   { "dbnc"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00373   { "dbc"    ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00374   { "dbnlv"  ,2,0x6C100000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00375   { "dblv"   ,2,0x6C110000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00376   { "dbnluf" ,2,0x6C120000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00377   { "dbluf"  ,2,0x6C130000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00378   { "dbzuf"  ,2,0x6C140000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00379   { "dbd"    ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00380   { "dbud"   ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00381   { "dblod"  ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00382   { "dblsd"  ,2,0x6C220000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00383   { "dbhid"  ,2,0x6C230000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00384   { "dbhsd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00385   { "dbeqd"  ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00386   { "dbned"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00387   { "dbltd"  ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00388   { "dbled"  ,2,0x6C280000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00389   { "dbgtd"  ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00390   { "dbged"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00391   { "dbzd"   ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00392   { "dbnzd"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00393   { "dbpd"   ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00394   { "dbnd"   ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00395   { "dbnnd"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00396   { "dbnvd"  ,2,0x6C2C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00397   { "dbvd"   ,2,0x6C2D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00398   { "dbnufd" ,2,0x6C2E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00399   { "dbufd"  ,2,0x6C2F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00400   { "dbncd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00401   { "dbcd"   ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00402   { "dbnlvd" ,2,0x6C300000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00403   { "dblvd"  ,2,0x6C310000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00404   { "dbnlufd",2,0x6C320000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00405   { "dblufd" ,2,0x6C330000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00406   { "dbzufd" ,2,0x6C340000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
00407   { "fix"    ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float },
00408   { "float"  ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt },
00409   { "iack"   ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None },
00410   { "idle"   ,0,0x06000000,0,           { 0, 0, 0 }, Imm_None },
00411   { "idle2"  ,0,0x06000001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
00412   { "lde"    ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00413   { "ldf"    ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00414   { "ldfu"   ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00415   { "ldflo"  ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00416   { "ldfls"  ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00417   { "ldfhi"  ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00418   { "ldfhs"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00419   { "ldfeq"  ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00420   { "ldfne"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00421   { "ldflt"  ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00422   { "ldfle"  ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00423   { "ldfgt"  ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00424   { "ldfge"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00425   { "ldfz"   ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00426   { "ldfnz"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00427   { "ldfp"   ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00428   { "ldfn"   ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00429   { "ldfnn"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00430   { "ldfnv"  ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00431   { "ldfv"   ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00432   { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00433   { "ldfuf"  ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00434   { "ldfnc"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00435   { "ldfc"   ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00436   { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00437   { "ldflv"  ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00438   { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00439   { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00440   { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00441   { "ldfi"   ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None },
00442   { "ldi"    ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00443   { "ldiu"   ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00444   { "ldilo"  ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00445   { "ldils"  ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00446   { "ldihi"  ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00447   { "ldihs"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00448   { "ldieq"  ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00449   { "ldine"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00450   { "ldilt"  ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00451   { "ldile"  ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00452   { "ldigt"  ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00453   { "ldige"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00454   { "ldiz"   ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00455   { "ldinz"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00456   { "ldip"   ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00457   { "ldin"   ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00458   { "ldinn"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00459   { "ldinv"  ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00460   { "ldiv"   ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00461   { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00462   { "ldiuf"  ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00463   { "ldinc"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00464   { "ldic"   ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00465   { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00466   { "ldilv"  ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00467   { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00468   { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00469   { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00470   { "ldii"   ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None },
00471   { "ldm"    ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00472   { "ldp"    ,2,0x08700000,0,           { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt },
00473   { "lopower",0,0x10800001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
00474   { "lsh"    ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00475   { "lsh3"   ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00476   { "maxspeed",0,0x10800000,0,          { 0, 0, 0 }, Imm_None }, /* LC31 Only */
00477   { "mpyf"   ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00478   { "mpyf3"  ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
00479   { "mpyi"   ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00480   { "mpyi3"  ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00481   { "negb"   ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00482   { "negf"   ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00483   { "negi"   ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00484   { "nop"    ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None },
00485   { "norm"   ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/
00486   { "not"    ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00487   { "or"     ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00488   { "or3"    ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00489   { "pop"    ,1,0x0E200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
00490   { "popf"   ,1,0x0EA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
00491   { "push"   ,1,0x0F200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
00492   { "pushf"  ,1,0x0FA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
00493   { "reti"   ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
00494   { "retiu"  ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
00495   { "retilo" ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
00496   { "retils" ,0,0x78020000,0,           { 0, 0, 0 }, Imm_None },
00497   { "retihi" ,0,0x78030000,0,           { 0, 0, 0 }, Imm_None },
00498   { "retihs" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
00499   { "retieq" ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
00500   { "retine" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
00501   { "retilt" ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
00502   { "retile" ,0,0x78080000,0,           { 0, 0, 0 }, Imm_None },
00503   { "retigt" ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
00504   { "retige" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
00505   { "retiz"  ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
00506   { "retinz" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
00507   { "retip"  ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
00508   { "retin"  ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
00509   { "retinn" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
00510   { "retinv" ,0,0x780C0000,0,           { 0, 0, 0 }, Imm_None },
00511   { "retiv"  ,0,0x780D0000,0,           { 0, 0, 0 }, Imm_None },
00512   { "retinuf",0,0x780E0000,0,           { 0, 0, 0 }, Imm_None },
00513   { "retiuf" ,0,0x780F0000,0,           { 0, 0, 0 }, Imm_None },
00514   { "retinc" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
00515   { "retic"  ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
00516   { "retinlv",0,0x78100000,0,           { 0, 0, 0 }, Imm_None },
00517   { "retilv" ,0,0x78110000,0,           { 0, 0, 0 }, Imm_None },
00518   { "retinluf",0,0x78120000,0,          { 0, 0, 0 }, Imm_None },
00519   { "retiluf",0,0x78130000,0,           { 0, 0, 0 }, Imm_None },
00520   { "retizuf",0,0x78140000,0,           { 0, 0, 0 }, Imm_None },
00521   { "rets"   ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
00522   { "retsu"  ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
00523   { "retslo" ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
00524   { "retsls" ,0,0x78820000,0,           { 0, 0, 0 }, Imm_None },
00525   { "retshi" ,0,0x78830000,0,           { 0, 0, 0 }, Imm_None },
00526   { "retshs" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
00527   { "retseq" ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
00528   { "retsne" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
00529   { "retslt" ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
00530   { "retsle" ,0,0x78880000,0,           { 0, 0, 0 }, Imm_None },
00531   { "retsgt" ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
00532   { "retsge" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
00533   { "retsz"  ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
00534   { "retsnz" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
00535   { "retsp"  ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
00536   { "retsn"  ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
00537   { "retsnn" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
00538   { "retsnv" ,0,0x788C0000,0,           { 0, 0, 0 }, Imm_None },
00539   { "retsv"  ,0,0x788D0000,0,           { 0, 0, 0 }, Imm_None },
00540   { "retsnuf",0,0x788E0000,0,           { 0, 0, 0 }, Imm_None },
00541   { "retsuf" ,0,0x788F0000,0,           { 0, 0, 0 }, Imm_None },
00542   { "retsnc" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
00543   { "retsc"  ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
00544   { "retsnlv",0,0x78900000,0,           { 0, 0, 0 }, Imm_None },
00545   { "retslv" ,0,0x78910000,0,           { 0, 0, 0 }, Imm_None },
00546   { "retsnluf",0,0x78920000,0,          { 0, 0, 0 }, Imm_None },
00547   { "retsluf",0,0x78930000,0,           { 0, 0, 0 }, Imm_None },
00548   { "retszuf",0,0x78940000,0,           { 0, 0, 0 }, Imm_None },
00549   { "rnd"    ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00550   { "rol"    ,1,0x11E00001,Rotate,      { AllReg, 0, 0 }, Imm_None },
00551   { "rolc"   ,1,0x12600001,Rotate,      { AllReg, 0, 0 }, Imm_None },
00552   { "ror"    ,1,0x12E0FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
00553   { "rorc"   ,1,0x1360FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
00554   { "rptb"   ,1,0x64000000,0,           { Imm24, 0, 0 }, Imm_UInt },
00555   { "rpts"   ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt },
00556   { "sigi"   ,0,0x16000000,0,           { 0, 0, 0 }, Imm_None },
00557   { "stf"    ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
00558   { "stfi"   ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
00559   { "sti"    ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
00560   { "stii"   ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
00561   { "subb"   ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00562   { "subb3"  ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00563   { "subc"   ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00564   { "subf"   ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00565   { "subf3"  ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
00566   { "subi"   ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00567   { "subi3"  ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00568   { "subrb"  ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00569   { "subrf"  ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
00570   { "subri"  ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
00571   { "swi"    ,0,0x66000000,0,           { 0, 0, 0 }, Imm_None },
00572   { "trap"   ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
00573   { "trapu"  ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
00574   { "traplo" ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
00575   { "trapls" ,1,0x74820020,0,           { IVector, 0, 0 }, Imm_None },
00576   { "traphi" ,1,0x74830020,0,           { IVector, 0, 0 }, Imm_None },
00577   { "traphs" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
00578   { "trapeq" ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
00579   { "trapne" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
00580   { "traplt" ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
00581   { "traple" ,1,0x74880020,0,           { IVector, 0, 0 }, Imm_None },
00582   { "trapgt" ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
00583   { "trapge" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
00584   { "trapz"  ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
00585   { "trapnz" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
00586   { "trapp"  ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
00587   { "trapn"  ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
00588   { "trapnn" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
00589   { "trapnv" ,1,0x748C0020,0,           { IVector, 0, 0 }, Imm_None },
00590   { "trapv"  ,1,0x748D0020,0,           { IVector, 0, 0 }, Imm_None },
00591   { "trapnuf",1,0x748E0020,0,           { IVector, 0, 0 }, Imm_None },
00592   { "trapuf" ,1,0x748F0020,0,           { IVector, 0, 0 }, Imm_None },
00593   { "trapnc" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
00594   { "trapc"  ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
00595   { "trapnlv",1,0x74900020,0,           { IVector, 0, 0 }, Imm_None },
00596   { "traplv" ,1,0x74910020,0,           { IVector, 0, 0 }, Imm_None },
00597   { "trapnluf",1,0x74920020,0,          { IVector, 0, 0 }, Imm_None },
00598   { "trapluf",1,0x74930020,0,           { IVector, 0, 0 }, Imm_None },
00599   { "trapzuf",1,0x74940020,0,           { IVector, 0, 0 }, Imm_None },
00600   { "tstb"   ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00601   { "tstb3"  ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
00602   { "xor"    ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
00603   { "xor3"   ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
00604   { ""       ,0,0x00000000,0,           { 0, 0, 0 }, 0 }
00605 };
00606 
00607 static const template *const tic30_optab_end =
00608   tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
00609 
00610 typedef struct {
00611   char *name;
00612   unsigned int operands_1;
00613   unsigned int operands_2;
00614   unsigned int base_opcode;
00615   unsigned int operand_types[2][3];
00616   /* Which operand fits into which part of the final opcode word. */
00617   int oporder;
00618 } partemplate;
00619 
00620 /* oporder defines - not very descriptive. */
00621 #define OO_4op1   0
00622 #define OO_4op2   1
00623 #define OO_4op3   2
00624 #define OO_5op1   3
00625 #define OO_5op2   4
00626 #define OO_PField 5
00627 
00628 static const partemplate tic30_paroptab[] = {
00629   { "q_absf_stf",   2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00630        OO_4op1 },
00631   { "q_absi_sti",   2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00632        OO_4op1 },
00633   { "q_addf3_stf",  3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00634        OO_5op1 },
00635   { "q_addi3_sti",  3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00636        OO_5op1 },
00637   { "q_and3_sti",   3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00638        OO_5op1 },
00639   { "q_ash3_sti",   3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
00640        OO_5op2 },
00641   { "q_fix_sti",    2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00642        OO_4op1 },
00643   { "q_float_stf",  2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00644        OO_4op1 },
00645   { "q_ldf_ldf",    2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
00646        OO_4op2 },
00647   { "q_ldf_stf",    2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00648        OO_4op1 },
00649   { "q_ldi_ldi",    2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
00650        OO_4op2 },
00651   { "q_ldi_sti",    2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00652        OO_4op1 },
00653   { "q_lsh3_sti",   3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
00654        OO_5op2 },
00655   { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn },
00656                                      { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
00657   { "q_mpyf3_stf",  3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00658        OO_5op1 },
00659   { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn },
00660                                      { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
00661   { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn },
00662                                      { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
00663   { "q_mpyi3_sti",  3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00664        OO_5op1 },
00665   { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn },
00666                                      { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
00667   { "q_negf_stf",   2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00668        OO_4op1 },
00669   { "q_negi_sti",   2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00670        OO_4op1 },
00671   { "q_not_sti",    2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
00672        OO_4op1 },
00673   { "q_or3_sti",    3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00674        OO_5op1 },
00675   { "q_stf_stf",    2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
00676        OO_4op3 },
00677   { "q_sti_sti",    2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
00678        OO_4op3 },
00679   { "q_subf3_stf",  3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
00680        OO_5op2 },
00681   { "q_subi3_sti",  3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
00682        OO_5op2 },
00683   { "q_xor3_sti",   3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
00684        OO_5op1 },
00685   { "",             0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 }
00686 };
00687 
00688 static const partemplate *const tic30_paroptab_end =
00689   tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]);
00690 
00691 #endif