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cell-binutils  2.17cvs20070401
sparc.h
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00001 /* Definitions for opcode table for the sparc.
00002    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
00003    2003, 2005 Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
00006    the GNU Binutils.
00007 
00008    GAS/GDB is free software; you can redistribute it and/or modify
00009    it under the terms of the GNU General Public License as published by
00010    the Free Software Foundation; either version 2, or (at your option)
00011    any later version.
00012 
00013    GAS/GDB is distributed in the hope that it will be useful,
00014    but WITHOUT ANY WARRANTY; without even the implied warranty of
00015    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
00016    GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with GAS or GDB; see the file COPYING.  If not, write to
00020    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
00021    Boston, MA 02110-1301, USA.  */
00022 
00023 #include "ansidecl.h"
00024 
00025 /* The SPARC opcode table (and other related data) is defined in
00026    the opcodes library in sparc-opc.c.  If you change anything here, make
00027    sure you fix up that file, and vice versa.  */
00028 
00029  /* FIXME-someday: perhaps the ,a's and such should be embedded in the
00030     instruction's name rather than the args.  This would make gas faster, pinsn
00031     slower, but would mess up some macros a bit.  xoxorich. */
00032 
00033 /* List of instruction sets variations.
00034    These values are such that each element is either a superset of a
00035    preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
00036    returns non-zero.
00037    The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
00038    Don't change this without updating sparc-opc.c.  */
00039 
00040 enum sparc_opcode_arch_val
00041 {
00042   SPARC_OPCODE_ARCH_V6 = 0,
00043   SPARC_OPCODE_ARCH_V7,
00044   SPARC_OPCODE_ARCH_V8,
00045   SPARC_OPCODE_ARCH_SPARCLET,
00046   SPARC_OPCODE_ARCH_SPARCLITE,
00047   /* V9 variants must appear last.  */
00048   SPARC_OPCODE_ARCH_V9,
00049   SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
00050   SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
00051   SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
00052 };
00053 
00054 /* The highest architecture in the table.  */
00055 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
00056 
00057 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
00058    insn encoding/decoding.  */
00059 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
00060 
00061 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
00062 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
00063 
00064 /* Table of cpu variants.  */
00065 
00066 typedef struct sparc_opcode_arch
00067 {
00068   const char *name;
00069   /* Mask of sparc_opcode_arch_val's supported.
00070      EG: For v7 this would be
00071      (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
00072      These are short's because sparc_opcode.architecture is.  */
00073   short supported;
00074 } sparc_opcode_arch;
00075 
00076 extern const struct sparc_opcode_arch sparc_opcode_archs[];
00077 
00078 /* Given architecture name, look up it's sparc_opcode_arch_val value.  */
00079 extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
00080 
00081 /* Return the bitmask of supported architectures for ARCH.  */
00082 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
00083 
00084 /* Non-zero if ARCH1 conflicts with ARCH2.
00085    IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
00086 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
00087  (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
00088    != SPARC_OPCODE_SUPPORTED (ARCH1)) \
00089   && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
00090      != SPARC_OPCODE_SUPPORTED (ARCH2)))
00091 
00092 /* Structure of an opcode table entry.  */
00093 
00094 typedef struct sparc_opcode
00095 {
00096   const char *name;
00097   unsigned long match;      /* Bits that must be set.  */
00098   unsigned long lose;       /* Bits that must not be set.  */
00099   const char *args;
00100   /* This was called "delayed" in versions before the flags.  */
00101   char flags;
00102   short architecture;       /* Bitmask of sparc_opcode_arch_val's.  */
00103 } sparc_opcode;
00104 
00105 #define       F_DELAYED     1      /* Delayed branch.  */
00106 #define       F_ALIAS              2      /* Alias for a "real" instruction.  */
00107 #define       F_UNBR        4      /* Unconditional branch.  */
00108 #define       F_CONDBR      8      /* Conditional branch.  */
00109 #define       F_JSR         16     /* Subroutine call.  */
00110 #define F_FLOAT             32     /* Floating point instruction (not a branch).  */
00111 #define F_FBR        64     /* Floating point branch.  */
00112 /* FIXME: Add F_ANACHRONISTIC flag for v9.  */
00113 
00114 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
00115    macro), which is 64 bits. It is handled as a special case.
00116 
00117    The match component is a mask saying which bits must match a particular
00118    opcode in order for an instruction to be an instance of that opcode.
00119 
00120    The args component is a string containing one character for each operand of the
00121    instruction.
00122 
00123    Kinds of operands:
00124        #      Number used by optimizer.   It is ignored.
00125        1      rs1 register.
00126        2      rs2 register.
00127        d      rd register.
00128        e      frs1 floating point register.
00129        v      frs1 floating point register (double/even).
00130        V      frs1 floating point register (quad/multiple of 4).
00131        f      frs2 floating point register.
00132        B      frs2 floating point register (double/even).
00133        R      frs2 floating point register (quad/multiple of 4).
00134        g      frsd floating point register.
00135        H      frsd floating point register (double/even).
00136        J      frsd floating point register (quad/multiple of 4).
00137        b      crs1 coprocessor register
00138        c      crs2 coprocessor register
00139        D      crsd coprocessor register
00140        m      alternate space register (asr) in rd
00141        M      alternate space register (asr) in rs1
00142        h      22 high bits.
00143        X      5 bit unsigned immediate
00144        Y      6 bit unsigned immediate
00145        3      SIAM mode (3 bits). (v9b)
00146        K      MEMBAR mask (7 bits). (v9)
00147        j      10 bit Immediate. (v9)
00148        I      11 bit Immediate. (v9)
00149        i      13 bit Immediate.
00150        n      22 bit immediate.
00151        k      2+14 bit PC relative immediate. (v9)
00152        G      19 bit PC relative immediate. (v9)
00153        l      22 bit PC relative immediate.
00154        L      30 bit PC relative immediate.
00155        a      Annul. The annul bit is set.
00156        A      Alternate address space. Stored as 8 bits.
00157        C      Coprocessor state register.
00158        F      floating point state register.
00159        p      Processor state register.
00160        N      Branch predict clear ",pn" (v9)
00161        T      Branch predict set ",pt" (v9)
00162        z      %icc. (v9)
00163        Z      %xcc. (v9)
00164        q      Floating point queue.
00165        r      Single register that is both rs1 and rd.
00166        O      Single register that is both rs2 and rd.
00167        Q      Coprocessor queue.
00168        S      Special case.
00169        t      Trap base register.
00170        w      Window invalid mask register.
00171        y      Y register.
00172        u      sparclet coprocessor registers in rd position
00173        U      sparclet coprocessor registers in rs1 position
00174        E      %ccr. (v9)
00175        s      %fprs. (v9)
00176        P      %pc.  (v9)
00177        W      %tick. (v9)
00178        o      %asi. (v9)
00179        6      %fcc0. (v9)
00180        7      %fcc1. (v9)
00181        8      %fcc2. (v9)
00182        9      %fcc3. (v9)
00183        !      Privileged Register in rd (v9)
00184        ?      Privileged Register in rs1 (v9)
00185        *      Prefetch function constant. (v9)
00186        x      OPF field (v9 impdep).
00187        0      32/64 bit immediate for set or setx (v9) insns
00188        _      Ancillary state register in rd (v9a)
00189        /      Ancillary state register in rs1 (v9a)
00190 
00191   The following chars are unused: (note: ,[] are used as punctuation)
00192   [45].  */
00193 
00194 #define OP2(x)              (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
00195 #define OP3(x)              (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
00196 #define OP(x)        ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
00197 #define OPF(x)              (((x) & 0x1ff) << 5) /* Opf field of float insns.  */
00198 #define OPF_LOW5(x)  OPF ((x) & 0x1f)     /* V9.  */
00199 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
00200 #define F3I(x)              (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
00201 #define F2(x, y)     (OP (x) | OP2(y))    /* Format 2 insns.  */
00202 #define F3(x, y, z)  (OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
00203 #define F1(x)        (OP (x))
00204 #define DISP30(x)    ((x) & 0x3fffffff)
00205 #define ASI(x)              (((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
00206 #define RS2(x)              ((x) & 0x1f)         /* Rs2 field.  */
00207 #define SIMM13(x)    ((x) & 0x1fff)       /* Simm13 field.  */
00208 #define RD(x)        (((x) & 0x1f) << 25) /* Destination register field.  */
00209 #define RS1(x)              (((x) & 0x1f) << 14) /* Rs1 field.  */
00210 #define ASI_RS2(x)   (SIMM13 (x))
00211 #define MEMBAR(x)    ((x) & 0x7f)
00212 #define SLCPOP(x)    (((x) & 0x7f) << 6)  /* Sparclet cpop.  */
00213 
00214 #define ANNUL (1 << 29)
00215 #define BPRED (1 << 19)     /* V9.  */
00216 #define       IMMED  F3I (1)
00217 #define RD_G0 RD (~0)
00218 #define       RS1_G0 RS1 (~0)
00219 #define       RS2_G0 RS2 (~0)
00220 
00221 extern const struct sparc_opcode sparc_opcodes[];
00222 extern const int sparc_num_opcodes;
00223 
00224 extern int sparc_encode_asi (const char *);
00225 extern const char *sparc_decode_asi (int);
00226 extern int sparc_encode_membar (const char *);
00227 extern const char *sparc_decode_membar (int);
00228 extern int sparc_encode_prefetch (const char *);
00229 extern const char *sparc_decode_prefetch (int);
00230 extern int sparc_encode_sparclet_cpreg (const char *);
00231 extern const char *sparc_decode_sparclet_cpreg (int);
00232 
00233 /* Local Variables:
00234    fill-column: 131
00235    comment-column: 0
00236    End: */
00237