Back to index

cell-binutils  2.17cvs20070401
ppc.h
Go to the documentation of this file.
00001 /* ppc.h -- Header file for PowerPC opcode table
00002    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
00003    Free Software Foundation, Inc.
00004    Written by Ian Lance Taylor, Cygnus Support
00005 
00006 This file is part of GDB, GAS, and the GNU binutils.
00007 
00008 GDB, GAS, and the GNU binutils are free software; you can redistribute
00009 them and/or modify them under the terms of the GNU General Public
00010 License as published by the Free Software Foundation; either version
00011 1, or (at your option) any later version.
00012 
00013 GDB, GAS, and the GNU binutils are distributed in the hope that they
00014 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016 the GNU General Public License for more details.
00017 
00018 You should have received a copy of the GNU General Public License
00019 along with this file; see the file COPYING.  If not, write to the Free
00020 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00021 
00022 #ifndef PPC_H
00023 #define PPC_H
00024 
00025 /* The opcode table is an array of struct powerpc_opcode.  */
00026 
00027 struct powerpc_opcode
00028 {
00029   /* The opcode name.  */
00030   const char *name;
00031 
00032   /* The opcode itself.  Those bits which will be filled in with
00033      operands are zeroes.  */
00034   unsigned long opcode;
00035 
00036   /* The opcode mask.  This is used by the disassembler.  This is a
00037      mask containing ones indicating those bits which must match the
00038      opcode field, and zeroes indicating those bits which need not
00039      match (and are presumably filled in by operands).  */
00040   unsigned long mask;
00041 
00042   /* One bit flags for the opcode.  These are used to indicate which
00043      specific processors support the instructions.  The defined values
00044      are listed below.  */
00045   unsigned long flags;
00046 
00047   /* An array of operand codes.  Each code is an index into the
00048      operand table.  They appear in the order which the operands must
00049      appear in assembly code, and are terminated by a zero.  */
00050   unsigned char operands[8];
00051 };
00052 
00053 /* The table itself is sorted by major opcode number, and is otherwise
00054    in the order in which the disassembler should consider
00055    instructions.  */
00056 extern const struct powerpc_opcode powerpc_opcodes[];
00057 extern const int powerpc_num_opcodes;
00058 
00059 /* Values defined for the flags field of a struct powerpc_opcode.  */
00060 
00061 /* Opcode is defined for the PowerPC architecture.  */
00062 #define PPC_OPCODE_PPC                     1
00063 
00064 /* Opcode is defined for the POWER (RS/6000) architecture.  */
00065 #define PPC_OPCODE_POWER            2
00066 
00067 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
00068 #define PPC_OPCODE_POWER2           4
00069 
00070 /* Opcode is only defined on 32 bit architectures.  */
00071 #define PPC_OPCODE_32                      8
00072 
00073 /* Opcode is only defined on 64 bit architectures.  */
00074 #define PPC_OPCODE_64                    0x10
00075 
00076 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
00077    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
00078    but it also supports many additional POWER instructions.  */
00079 #define PPC_OPCODE_601                   0x20
00080 
00081 /* Opcode is supported in both the Power and PowerPC architectures
00082    (ie, compiler's -mcpu=common or assembler's -mcom).  */
00083 #define PPC_OPCODE_COMMON         0x40
00084 
00085 /* Opcode is supported for any Power or PowerPC platform (this is
00086    for the assembler's -many option, and it eliminates duplicates).  */
00087 #define PPC_OPCODE_ANY                   0x80
00088 
00089 /* Opcode is supported as part of the 64-bit bridge.  */
00090 #define PPC_OPCODE_64_BRIDGE            0x100
00091 
00092 /* Opcode is supported by Altivec Vector Unit */
00093 #define PPC_OPCODE_ALTIVEC       0x200
00094 
00095 /* Opcode is supported by PowerPC 403 processor.  */
00096 #define PPC_OPCODE_403                  0x400
00097 
00098 /* Opcode is supported by PowerPC BookE processor.  */
00099 #define PPC_OPCODE_BOOKE         0x800
00100 
00101 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
00102 #define PPC_OPCODE_BOOKE64      0x1000
00103 
00104 /* Opcode is supported by PowerPC 440 processor.  */
00105 #define PPC_OPCODE_440                 0x2000
00106 
00107 /* Opcode is only supported by Power4 architecture.  */
00108 #define PPC_OPCODE_POWER4       0x4000
00109 
00110 /* Opcode isn't supported by Power4 architecture.  */
00111 #define PPC_OPCODE_NOPOWER4     0x8000
00112 
00113 /* Opcode is only supported by POWERPC Classic architecture.  */
00114 #define PPC_OPCODE_CLASSIC     0x10000
00115 
00116 /* Opcode is only supported by e500x2 Core.  */
00117 #define PPC_OPCODE_SPE                0x20000
00118 
00119 /* Opcode is supported by e500x2 Integer select APU.  */
00120 #define PPC_OPCODE_ISEL               0x40000
00121 
00122 /* Opcode is an e500 SPE floating point instruction.  */
00123 #define PPC_OPCODE_EFS                0x80000
00124 
00125 /* Opcode is supported by branch locking APU.  */
00126 #define PPC_OPCODE_BRLOCK     0x100000
00127 
00128 /* Opcode is supported by performance monitor APU.  */
00129 #define PPC_OPCODE_PMR               0x200000
00130 
00131 /* Opcode is supported by cache locking APU.  */
00132 #define PPC_OPCODE_CACHELCK   0x400000
00133 
00134 /* Opcode is supported by machine check APU.  */
00135 #define PPC_OPCODE_RFMCI      0x800000
00136 
00137 /* Opcode is only supported by Power5 architecture.  */
00138 #define PPC_OPCODE_POWER5    0x1000000
00139 
00140 /* Opcode is supported by PowerPC e300 family.  */
00141 #define PPC_OPCODE_E300          0x2000000
00142 
00143 /* Opcode is only supported by Power6 architecture.  */
00144 #define PPC_OPCODE_POWER6    0x4000000
00145 
00146 /* Opcode is only supported by PowerPC Cell family.  */
00147 #define PPC_OPCODE_CELL             0x8000000
00148 
00149 /* A macro to extract the major opcode from an instruction.  */
00150 #define PPC_OP(i) (((i) >> 26) & 0x3f)
00151 
00152 /* The operands table is an array of struct powerpc_operand.  */
00153 
00154 struct powerpc_operand
00155 {
00156   /* The number of bits in the operand.  */
00157   int bits;
00158 
00159   /* How far the operand is left shifted in the instruction.  */
00160   int shift;
00161 
00162   /* Insertion function.  This is used by the assembler.  To insert an
00163      operand value into an instruction, check this field.
00164 
00165      If it is NULL, execute
00166         i |= (op & ((1 << o->bits) - 1)) << o->shift;
00167      (i is the instruction which we are filling in, o is a pointer to
00168      this structure, and op is the opcode value; this assumes twos
00169      complement arithmetic).
00170 
00171      If this field is not NULL, then simply call it with the
00172      instruction and the operand value.  It will return the new value
00173      of the instruction.  If the ERRMSG argument is not NULL, then if
00174      the operand value is illegal, *ERRMSG will be set to a warning
00175      string (the operand will be inserted in any case).  If the
00176      operand value is legal, *ERRMSG will be unchanged (most operands
00177      can accept any value).  */
00178   unsigned long (*insert)
00179     (unsigned long instruction, long op, int dialect, const char **errmsg);
00180 
00181   /* Extraction function.  This is used by the disassembler.  To
00182      extract this operand type from an instruction, check this field.
00183 
00184      If it is NULL, compute
00185         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
00186         if ((o->flags & PPC_OPERAND_SIGNED) != 0
00187             && (op & (1 << (o->bits - 1))) != 0)
00188           op -= 1 << o->bits;
00189      (i is the instruction, o is a pointer to this structure, and op
00190      is the result; this assumes twos complement arithmetic).
00191 
00192      If this field is not NULL, then simply call it with the
00193      instruction value.  It will return the value of the operand.  If
00194      the INVALID argument is not NULL, *INVALID will be set to
00195      non-zero if this operand type can not actually be extracted from
00196      this operand (i.e., the instruction does not match).  If the
00197      operand is valid, *INVALID will not be changed.  */
00198   long (*extract) (unsigned long instruction, int dialect, int *invalid);
00199 
00200   /* One bit syntax flags.  */
00201   unsigned long flags;
00202 };
00203 
00204 /* Elements in the table are retrieved by indexing with values from
00205    the operands field of the powerpc_opcodes table.  */
00206 
00207 extern const struct powerpc_operand powerpc_operands[];
00208 
00209 /* Values defined for the flags field of a struct powerpc_operand.  */
00210 
00211 /* This operand takes signed values.  */
00212 #define PPC_OPERAND_SIGNED (01)
00213 
00214 /* This operand takes signed values, but also accepts a full positive
00215    range of values when running in 32 bit mode.  That is, if bits is
00216    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
00217    this flag is ignored.  */
00218 #define PPC_OPERAND_SIGNOPT (02)
00219 
00220 /* This operand does not actually exist in the assembler input.  This
00221    is used to support extended mnemonics such as mr, for which two
00222    operands fields are identical.  The assembler should call the
00223    insert function with any op value.  The disassembler should call
00224    the extract function, ignore the return value, and check the value
00225    placed in the valid argument.  */
00226 #define PPC_OPERAND_FAKE (04)
00227 
00228 /* The next operand should be wrapped in parentheses rather than
00229    separated from this one by a comma.  This is used for the load and
00230    store instructions which want their operands to look like
00231        reg,displacement(reg)
00232    */
00233 #define PPC_OPERAND_PARENS (010)
00234 
00235 /* This operand may use the symbolic names for the CR fields, which
00236    are
00237        lt  0  gt  1  eq  2  so  3  un  3
00238        cr0 0  cr1 1  cr2 2  cr3 3
00239        cr4 4  cr5 5  cr6 6  cr7 7
00240    These may be combined arithmetically, as in cr2*4+gt.  These are
00241    only supported on the PowerPC, not the POWER.  */
00242 #define PPC_OPERAND_CR (020)
00243 
00244 /* This operand names a register.  The disassembler uses this to print
00245    register names with a leading 'r'.  */
00246 #define PPC_OPERAND_GPR (040)
00247 
00248 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
00249 #define PPC_OPERAND_GPR_0 (0100)
00250 
00251 /* This operand names a floating point register.  The disassembler
00252    prints these with a leading 'f'.  */
00253 #define PPC_OPERAND_FPR (0200)
00254 
00255 /* This operand is a relative branch displacement.  The disassembler
00256    prints these symbolically if possible.  */
00257 #define PPC_OPERAND_RELATIVE (0400)
00258 
00259 /* This operand is an absolute branch address.  The disassembler
00260    prints these symbolically if possible.  */
00261 #define PPC_OPERAND_ABSOLUTE (01000)
00262 
00263 /* This operand is optional, and is zero if omitted.  This is used for
00264    example, in the optional BF field in the comparison instructions.  The
00265    assembler must count the number of operands remaining on the line,
00266    and the number of operands remaining for the opcode, and decide
00267    whether this operand is present or not.  The disassembler should
00268    print this operand out only if it is not zero.  */
00269 #define PPC_OPERAND_OPTIONAL (02000)
00270 
00271 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
00272    is omitted, then for the next operand use this operand value plus
00273    1, ignoring the next operand field for the opcode.  This wretched
00274    hack is needed because the Power rotate instructions can take
00275    either 4 or 5 operands.  The disassembler should print this operand
00276    out regardless of the PPC_OPERAND_OPTIONAL field.  */
00277 #define PPC_OPERAND_NEXT (04000)
00278 
00279 /* This operand should be regarded as a negative number for the
00280    purposes of overflow checking (i.e., the normal most negative
00281    number is disallowed and one more than the normal most positive
00282    number is allowed).  This flag will only be set for a signed
00283    operand.  */
00284 #define PPC_OPERAND_NEGATIVE (010000)
00285 
00286 /* This operand names a vector unit register.  The disassembler
00287    prints these with a leading 'v'.  */
00288 #define PPC_OPERAND_VR (020000)
00289 
00290 /* This operand is for the DS field in a DS form instruction.  */
00291 #define PPC_OPERAND_DS (040000)
00292 
00293 /* This operand is for the DQ field in a DQ form instruction.  */
00294 #define PPC_OPERAND_DQ (0100000)
00295 
00296 /* The POWER and PowerPC assemblers use a few macros.  We keep them
00297    with the operands table for simplicity.  The macro table is an
00298    array of struct powerpc_macro.  */
00299 
00300 struct powerpc_macro
00301 {
00302   /* The macro name.  */
00303   const char *name;
00304 
00305   /* The number of operands the macro takes.  */
00306   unsigned int operands;
00307 
00308   /* One bit flags for the opcode.  These are used to indicate which
00309      specific processors support the instructions.  The values are the
00310      same as those for the struct powerpc_opcode flags field.  */
00311   unsigned long flags;
00312 
00313   /* A format string to turn the macro into a normal instruction.
00314      Each %N in the string is replaced with operand number N (zero
00315      based).  */
00316   const char *format;
00317 };
00318 
00319 extern const struct powerpc_macro powerpc_macros[];
00320 extern const int powerpc_num_macros;
00321 
00322 #endif /* PPC_H */