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mips.h
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00001 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
00002    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
00003    2003, 2004, 2005
00004    Free Software Foundation, Inc.
00005    Contributed by Ralph Campbell and OSF
00006    Commented and modified by Ian Lance Taylor, Cygnus Support
00007 
00008 This file is part of GDB, GAS, and the GNU binutils.
00009 
00010 GDB, GAS, and the GNU binutils are free software; you can redistribute
00011 them and/or modify them under the terms of the GNU General Public
00012 License as published by the Free Software Foundation; either version
00013 1, or (at your option) any later version.
00014 
00015 GDB, GAS, and the GNU binutils are distributed in the hope that they
00016 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00017 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00018 the GNU General Public License for more details.
00019 
00020 You should have received a copy of the GNU General Public License
00021 along with this file; see the file COPYING.  If not, write to the Free
00022 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00023 
00024 #ifndef _MIPS_H_
00025 #define _MIPS_H_
00026 
00027 /* These are bit masks and shift counts to use to access the various
00028    fields of an instruction.  To retrieve the X field of an
00029    instruction, use the expression
00030        (i >> OP_SH_X) & OP_MASK_X
00031    To set the same field (to j), use
00032        i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
00033 
00034    Make sure you use fields that are appropriate for the instruction,
00035    of course.
00036 
00037    The 'i' format uses OP, RS, RT and IMMEDIATE.
00038 
00039    The 'j' format uses OP and TARGET.
00040 
00041    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
00042 
00043    The 'b' format uses OP, RS, RT and DELTA.
00044 
00045    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
00046 
00047    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
00048 
00049    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
00050    breakpoint instruction are not defined; Kane says the breakpoint
00051    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
00052    only use ten bits).  An optional two-operand form of break/sdbbp
00053    allows the lower ten bits to be set too, and MIPS32 and later
00054    architectures allow 20 bits to be set with a signal operand
00055    (using CODE20).
00056 
00057    The syscall instruction uses CODE20.
00058 
00059    The general coprocessor instructions use COPZ.  */
00060 
00061 #define OP_MASK_OP          0x3f
00062 #define OP_SH_OP            26
00063 #define OP_MASK_RS          0x1f
00064 #define OP_SH_RS            21
00065 #define OP_MASK_FR          0x1f
00066 #define OP_SH_FR            21
00067 #define OP_MASK_FMT         0x1f
00068 #define OP_SH_FMT           21
00069 #define OP_MASK_BCC         0x7
00070 #define OP_SH_BCC           18
00071 #define OP_MASK_CODE        0x3ff
00072 #define OP_SH_CODE          16
00073 #define OP_MASK_CODE2              0x3ff
00074 #define OP_SH_CODE2         6
00075 #define OP_MASK_RT          0x1f
00076 #define OP_SH_RT            16
00077 #define OP_MASK_FT          0x1f
00078 #define OP_SH_FT            16
00079 #define OP_MASK_CACHE              0x1f
00080 #define OP_SH_CACHE         16
00081 #define OP_MASK_RD          0x1f
00082 #define OP_SH_RD            11
00083 #define OP_MASK_FS          0x1f
00084 #define OP_SH_FS            11
00085 #define OP_MASK_PREFX              0x1f
00086 #define OP_SH_PREFX         11
00087 #define OP_MASK_CCC         0x7
00088 #define OP_SH_CCC           8
00089 #define OP_MASK_CODE20             0xfffff /* 20 bit syscall/breakpoint code.  */
00090 #define OP_SH_CODE20        6
00091 #define OP_MASK_SHAMT              0x1f
00092 #define OP_SH_SHAMT         6
00093 #define OP_MASK_FD          0x1f
00094 #define OP_SH_FD            6
00095 #define OP_MASK_TARGET             0x3ffffff
00096 #define OP_SH_TARGET        0
00097 #define OP_MASK_COPZ        0x1ffffff
00098 #define OP_SH_COPZ          0
00099 #define OP_MASK_IMMEDIATE   0xffff
00100 #define OP_SH_IMMEDIATE            0
00101 #define OP_MASK_DELTA              0xffff
00102 #define OP_SH_DELTA         0
00103 #define OP_MASK_FUNCT              0x3f
00104 #define OP_SH_FUNCT         0
00105 #define OP_MASK_SPEC        0x3f
00106 #define OP_SH_SPEC          0
00107 #define OP_SH_LOCC              8       /* FP condition code.  */
00108 #define OP_SH_HICC              18      /* FP condition code.  */
00109 #define OP_MASK_CC              0x7
00110 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
00111 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
00112 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
00113 #define OP_MASK_COP1SPEC        0xf
00114 #define OP_MASK_COP1SCLR        0x4
00115 #define OP_MASK_COP1CMP         0x3
00116 #define OP_SH_COP1CMP           4
00117 #define OP_SH_FORMAT            21      /* FP short format field.  */
00118 #define OP_MASK_FORMAT          0x7
00119 #define OP_SH_TRUE              16
00120 #define OP_MASK_TRUE            0x1
00121 #define OP_SH_GE                17
00122 #define OP_MASK_GE              0x01
00123 #define OP_SH_UNSIGNED          16
00124 #define OP_MASK_UNSIGNED        0x1
00125 #define OP_SH_HINT              16
00126 #define OP_MASK_HINT            0x1f
00127 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
00128 #define OP_MASK_MMI             0x3f
00129 #define OP_SH_MMISUB            6
00130 #define OP_MASK_MMISUB          0x1f
00131 #define OP_MASK_PERFREG            0x1f   /* Performance monitoring.  */
00132 #define OP_SH_PERFREG              1
00133 #define OP_SH_SEL           0      /* Coprocessor select field.  */
00134 #define OP_MASK_SEL         0x7    /* The sel field of mfcZ and mtcZ.  */
00135 #define OP_SH_CODE19        6       /* 19 bit wait code.  */
00136 #define OP_MASK_CODE19             0x7ffff
00137 #define OP_SH_ALN           21
00138 #define OP_MASK_ALN         0x7
00139 #define OP_SH_VSEL          21
00140 #define OP_MASK_VSEL        0x1f
00141 #define OP_MASK_VECBYTE            0x7    /* Selector field is really 4 bits,
00142                                       but 0x8-0xf don't select bytes.  */
00143 #define OP_SH_VECBYTE              22
00144 #define OP_MASK_VECALIGN    0x7    /* Vector byte-align (alni.ob) op.  */
00145 #define OP_SH_VECALIGN             21
00146 #define OP_MASK_INSMSB             0x1f   /* "ins" MSB.  */
00147 #define OP_SH_INSMSB        11
00148 #define OP_MASK_EXTMSBD            0x1f   /* "ext" MSBD.  */
00149 #define OP_SH_EXTMSBD              11
00150 
00151 /* MIPS DSP ASE */
00152 #define OP_SH_DSPACC        11
00153 #define OP_MASK_DSPACC      0x3
00154 #define OP_SH_DSPACC_S      21
00155 #define OP_MASK_DSPACC_S    0x3
00156 #define OP_SH_DSPSFT        20
00157 #define OP_MASK_DSPSFT      0x3f
00158 #define OP_SH_DSPSFT_7      19
00159 #define OP_MASK_DSPSFT_7    0x7f
00160 #define OP_SH_SA3           21
00161 #define OP_MASK_SA3         0x7
00162 #define OP_SH_SA4           21
00163 #define OP_MASK_SA4         0xf
00164 #define OP_SH_IMM8          16
00165 #define OP_MASK_IMM8        0xff
00166 #define OP_SH_IMM10         16
00167 #define OP_MASK_IMM10              0x3ff
00168 #define OP_SH_WRDSP         11
00169 #define OP_MASK_WRDSP              0x3f
00170 #define OP_SH_RDDSP         16
00171 #define OP_MASK_RDDSP              0x3f
00172 #define OP_SH_BP            11
00173 #define OP_MASK_BP          0x3
00174 
00175 /* MIPS MT ASE */
00176 #define OP_SH_MT_U          5
00177 #define OP_MASK_MT_U        0x1
00178 #define OP_SH_MT_H          4
00179 #define OP_MASK_MT_H        0x1
00180 #define OP_SH_MTACC_T              18
00181 #define OP_MASK_MTACC_T            0x3
00182 #define OP_SH_MTACC_D              13
00183 #define OP_MASK_MTACC_D            0x3
00184 
00185 #define       OP_OP_COP0           0x10
00186 #define       OP_OP_COP1           0x11
00187 #define       OP_OP_COP2           0x12
00188 #define       OP_OP_COP3           0x13
00189 #define       OP_OP_LWC1           0x31
00190 #define       OP_OP_LWC2           0x32
00191 #define       OP_OP_LWC3           0x33   /* a.k.a. pref */
00192 #define       OP_OP_LDC1           0x35
00193 #define       OP_OP_LDC2           0x36
00194 #define       OP_OP_LDC3           0x37   /* a.k.a. ld */
00195 #define       OP_OP_SWC1           0x39
00196 #define       OP_OP_SWC2           0x3a
00197 #define       OP_OP_SWC3           0x3b
00198 #define       OP_OP_SDC1           0x3d
00199 #define       OP_OP_SDC2           0x3e
00200 #define       OP_OP_SDC3           0x3f   /* a.k.a. sd */
00201 
00202 /* Values in the 'VSEL' field.  */
00203 #define MDMX_FMTSEL_IMM_QH  0x1d
00204 #define MDMX_FMTSEL_IMM_OB  0x1e
00205 #define MDMX_FMTSEL_VEC_QH  0x15
00206 #define MDMX_FMTSEL_VEC_OB  0x16
00207 
00208 /* UDI */
00209 #define OP_SH_UDI1          6
00210 #define OP_MASK_UDI1        0x1f
00211 #define OP_SH_UDI2          6
00212 #define OP_MASK_UDI2        0x3ff
00213 #define OP_SH_UDI3          6
00214 #define OP_MASK_UDI3        0x7fff
00215 #define OP_SH_UDI4          6
00216 #define OP_MASK_UDI4        0xfffff
00217 
00218 /* This structure holds information for a particular instruction.  */
00219 
00220 struct mips_opcode
00221 {
00222   /* The name of the instruction.  */
00223   const char *name;
00224   /* A string describing the arguments for this instruction.  */
00225   const char *args;
00226   /* The basic opcode for the instruction.  When assembling, this
00227      opcode is modified by the arguments to produce the actual opcode
00228      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
00229   unsigned long match;
00230   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
00231      relevant portions of the opcode when disassembling.  If the
00232      actual opcode anded with the match field equals the opcode field,
00233      then we have found the correct instruction.  If pinfo is
00234      INSN_MACRO, then this field is the macro identifier.  */
00235   unsigned long mask;
00236   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
00237      of bits describing the instruction, notably any relevant hazard
00238      information.  */
00239   unsigned long pinfo;
00240   /* A collection of additional bits describing the instruction. */
00241   unsigned long pinfo2;
00242   /* A collection of bits describing the instruction sets of which this
00243      instruction or macro is a member. */
00244   unsigned long membership;
00245 };
00246 
00247 /* These are the characters which may appear in the args field of an
00248    instruction.  They appear in the order in which the fields appear
00249    when the instruction is used.  Commas and parentheses in the args
00250    string are ignored when assembling, and written into the output
00251    when disassembling.
00252 
00253    Each of these characters corresponds to a mask field defined above.
00254 
00255    "<" 5 bit shift amount (OP_*_SHAMT)
00256    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
00257    "a" 26 bit target address (OP_*_TARGET)
00258    "b" 5 bit base register (OP_*_RS)
00259    "c" 10 bit breakpoint code (OP_*_CODE)
00260    "d" 5 bit destination register specifier (OP_*_RD)
00261    "h" 5 bit prefx hint (OP_*_PREFX)
00262    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
00263    "j" 16 bit signed immediate (OP_*_DELTA)
00264    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
00265        Also used for immediate operands in vr5400 vector insns.
00266    "o" 16 bit signed offset (OP_*_DELTA)
00267    "p" 16 bit PC relative branch target address (OP_*_DELTA)
00268    "q" 10 bit extra breakpoint code (OP_*_CODE2)
00269    "r" 5 bit same register used as both source and target (OP_*_RS)
00270    "s" 5 bit source register specifier (OP_*_RS)
00271    "t" 5 bit target register (OP_*_RT)
00272    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
00273    "v" 5 bit same register used as both source and destination (OP_*_RS)
00274    "w" 5 bit same register used as both target and destination (OP_*_RT)
00275    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
00276        (used by clo and clz)
00277    "C" 25 bit coprocessor function code (OP_*_COPZ)
00278    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
00279    "J" 19 bit wait function code (OP_*_CODE19)
00280    "x" accept and ignore register name
00281    "z" must be zero register
00282    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
00283    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
00284         LSB (OP_*_SHAMT).
00285        Enforces: 0 <= pos < 32.
00286    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
00287        Requires that "+A" or "+E" occur first to set position.
00288        Enforces: 0 < (pos+size) <= 32.
00289    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
00290        Requires that "+A" or "+E" occur first to set position.
00291        Enforces: 0 < (pos+size) <= 32.
00292        (Also used by "dext" w/ different limits, but limits for
00293        that are checked by the M_DEXT macro.)
00294    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
00295        Enforces: 32 <= pos < 64.
00296    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
00297        Requires that "+A" or "+E" occur first to set position.
00298        Enforces: 32 < (pos+size) <= 64.
00299    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
00300        Requires that "+A" or "+E" occur first to set position.
00301        Enforces: 32 < (pos+size) <= 64.
00302    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
00303        Requires that "+A" or "+E" occur first to set position.
00304        Enforces: 32 < (pos+size) <= 64.
00305 
00306    Floating point instructions:
00307    "D" 5 bit destination register (OP_*_FD)
00308    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
00309    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
00310    "S" 5 bit fs source 1 register (OP_*_FS)
00311    "T" 5 bit ft source 2 register (OP_*_FT)
00312    "R" 5 bit fr source 3 register (OP_*_FR)
00313    "V" 5 bit same register used as floating source and destination (OP_*_FS)
00314    "W" 5 bit same register used as floating target and destination (OP_*_FT)
00315 
00316    Coprocessor instructions:
00317    "E" 5 bit target register (OP_*_RT)
00318    "G" 5 bit destination register (OP_*_RD)
00319    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
00320    "P" 5 bit performance-monitor register (OP_*_PERFREG)
00321    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
00322    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
00323    see also "k" above
00324    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
00325        for pretty-printing in disassembly only.
00326 
00327    Macro instructions:
00328    "A" General 32 bit expression
00329    "I" 32 bit immediate (value placed in imm_expr).
00330    "+I" 32 bit immediate (value placed in imm2_expr).
00331    "F" 64 bit floating point constant in .rdata
00332    "L" 64 bit floating point constant in .lit8
00333    "f" 32 bit floating point constant
00334    "l" 32 bit floating point constant in .lit4
00335 
00336    MDMX instruction operands (note that while these use the FP register
00337    fields, they accept both $fN and $vN names for the registers):  
00338    "O" MDMX alignment offset (OP_*_ALN)
00339    "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
00340    "X" MDMX destination register (OP_*_FD) 
00341    "Y" MDMX source register (OP_*_FS)
00342    "Z" MDMX source register (OP_*_FT)
00343 
00344    DSP ASE usage:
00345    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
00346    "3" 3 bit unsigned immediate (OP_*_SA3)
00347    "4" 4 bit unsigned immediate (OP_*_SA4)
00348    "5" 8 bit unsigned immediate (OP_*_IMM8)
00349    "6" 5 bit unsigned immediate (OP_*_RS)
00350    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
00351    "8" 6 bit unsigned immediate (OP_*_WRDSP)
00352    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
00353    "0" 6 bit signed immediate (OP_*_DSPSFT)
00354    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
00355    "'" 6 bit unsigned immediate (OP_*_RDDSP)
00356    "@" 10 bit signed immediate (OP_*_IMM10)
00357 
00358    MT ASE usage:
00359    "!" 1 bit usermode flag (OP_*_MT_U)
00360    "$" 1 bit load high flag (OP_*_MT_H)
00361    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
00362    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
00363    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
00364    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
00365    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
00366 
00367    UDI immediates:
00368    "+1" UDI immediate bits 6-10
00369    "+2" UDI immediate bits 6-15
00370    "+3" UDI immediate bits 6-20
00371    "+4" UDI immediate bits 6-25
00372 
00373    Other:
00374    "()" parens surrounding optional value
00375    ","  separates operands
00376    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
00377    "+"  Start of extension sequence.
00378 
00379    Characters used so far, for quick reference when adding more:
00380    "234567890"
00381    "%[]<>(),+:'@!$*&"
00382    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
00383    "abcdefghijklopqrstuvwxz"
00384 
00385    Extension character sequences used so far ("+" followed by the
00386    following), for quick reference when adding more:
00387    "1234"
00388    "ABCDEFGHIT"
00389    "t"
00390 */
00391 
00392 /* These are the bits which may be set in the pinfo field of an
00393    instructions, if it is not equal to INSN_MACRO.  */
00394 
00395 /* Modifies the general purpose register in OP_*_RD.  */
00396 #define INSN_WRITE_GPR_D            0x00000001
00397 /* Modifies the general purpose register in OP_*_RT.  */
00398 #define INSN_WRITE_GPR_T            0x00000002
00399 /* Modifies general purpose register 31.  */
00400 #define INSN_WRITE_GPR_31           0x00000004
00401 /* Modifies the floating point register in OP_*_FD.  */
00402 #define INSN_WRITE_FPR_D            0x00000008
00403 /* Modifies the floating point register in OP_*_FS.  */
00404 #define INSN_WRITE_FPR_S            0x00000010
00405 /* Modifies the floating point register in OP_*_FT.  */
00406 #define INSN_WRITE_FPR_T            0x00000020
00407 /* Reads the general purpose register in OP_*_RS.  */
00408 #define INSN_READ_GPR_S             0x00000040
00409 /* Reads the general purpose register in OP_*_RT.  */
00410 #define INSN_READ_GPR_T             0x00000080
00411 /* Reads the floating point register in OP_*_FS.  */
00412 #define INSN_READ_FPR_S             0x00000100
00413 /* Reads the floating point register in OP_*_FT.  */
00414 #define INSN_READ_FPR_T             0x00000200
00415 /* Reads the floating point register in OP_*_FR.  */
00416 #define INSN_READ_FPR_R                0x00000400
00417 /* Modifies coprocessor condition code.  */
00418 #define INSN_WRITE_COND_CODE        0x00000800
00419 /* Reads coprocessor condition code.  */
00420 #define INSN_READ_COND_CODE         0x00001000
00421 /* TLB operation.  */
00422 #define INSN_TLB                    0x00002000
00423 /* Reads coprocessor register other than floating point register.  */
00424 #define INSN_COP                    0x00004000
00425 /* Instruction loads value from memory, requiring delay.  */
00426 #define INSN_LOAD_MEMORY_DELAY      0x00008000
00427 /* Instruction loads value from coprocessor, requiring delay.  */
00428 #define INSN_LOAD_COPROC_DELAY         0x00010000
00429 /* Instruction has unconditional branch delay slot.  */
00430 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
00431 /* Instruction has conditional branch delay slot.  */
00432 #define INSN_COND_BRANCH_DELAY      0x00040000
00433 /* Conditional branch likely: if branch not taken, insn nullified.  */
00434 #define INSN_COND_BRANCH_LIKELY        0x00080000
00435 /* Moves to coprocessor register, requiring delay.  */
00436 #define INSN_COPROC_MOVE_DELAY      0x00100000
00437 /* Loads coprocessor register from memory, requiring delay.  */
00438 #define INSN_COPROC_MEMORY_DELAY    0x00200000
00439 /* Reads the HI register.  */
00440 #define INSN_READ_HI            0x00400000
00441 /* Reads the LO register.  */
00442 #define INSN_READ_LO            0x00800000
00443 /* Modifies the HI register.  */
00444 #define INSN_WRITE_HI                  0x01000000
00445 /* Modifies the LO register.  */
00446 #define INSN_WRITE_LO                  0x02000000
00447 /* Takes a trap (easier to keep out of delay slot).  */
00448 #define INSN_TRAP                   0x04000000
00449 /* Instruction stores value into memory.  */
00450 #define INSN_STORE_MEMORY       0x08000000
00451 /* Instruction uses single precision floating point.  */
00452 #define FP_S                    0x10000000
00453 /* Instruction uses double precision floating point.  */
00454 #define FP_D                    0x20000000
00455 /* Instruction is part of the tx39's integer multiply family.    */
00456 #define INSN_MULT                   0x40000000
00457 /* Instruction synchronize shared memory.  */
00458 #define INSN_SYNC               0x80000000
00459 
00460 /* These are the bits which may be set in the pinfo2 field of an
00461    instruction. */
00462 
00463 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
00464 #define       INSN2_ALIAS              0x00000001
00465 /* Instruction reads MDMX accumulator. */
00466 #define INSN2_READ_MDMX_ACC     0x00000002
00467 /* Instruction writes MDMX accumulator. */
00468 #define INSN2_WRITE_MDMX_ACC           0x00000004
00469 
00470 /* Instruction is actually a macro.  It should be ignored by the
00471    disassembler, and requires special treatment by the assembler.  */
00472 #define INSN_MACRO                  0xffffffff
00473 
00474 /* Masks used to mark instructions to indicate which MIPS ISA level
00475    they were introduced in.  ISAs, as defined below, are logical
00476    ORs of these bits, indicating that they support the instructions
00477    defined at the given level.  */
00478 
00479 #define INSN_ISA_MASK                0x00000fff
00480 #define INSN_ISA1                 0x00000001
00481 #define INSN_ISA2                 0x00000002
00482 #define INSN_ISA3                 0x00000004
00483 #define INSN_ISA4                 0x00000008
00484 #define INSN_ISA5                 0x00000010
00485 #define INSN_ISA32                0x00000020
00486 #define INSN_ISA64                0x00000040
00487 #define INSN_ISA32R2              0x00000080
00488 #define INSN_ISA64R2              0x00000100
00489 
00490 /* Masks used for MIPS-defined ASEs.  */
00491 #define INSN_ASE_MASK                0x3c00f000
00492 
00493 /* DSP ASE */ 
00494 #define INSN_DSP                  0x00001000
00495 #define INSN_DSP64                0x00002000
00496 /* MIPS 16 ASE */
00497 #define INSN_MIPS16               0x00004000
00498 /* MIPS-3D ASE */
00499 #define INSN_MIPS3D               0x00008000
00500 
00501 /* Chip specific instructions.  These are bitmasks.  */
00502 
00503 /* MIPS R4650 instruction.  */
00504 #define INSN_4650                 0x00010000
00505 /* LSI R4010 instruction.  */
00506 #define INSN_4010                 0x00020000
00507 /* NEC VR4100 instruction.  */
00508 #define INSN_4100                 0x00040000
00509 /* Toshiba R3900 instruction.  */
00510 #define INSN_3900                 0x00080000
00511 /* MIPS R10000 instruction.  */
00512 #define INSN_10000                0x00100000
00513 /* Broadcom SB-1 instruction.  */
00514 #define INSN_SB1                  0x00200000
00515 /* NEC VR4111/VR4181 instruction.  */
00516 #define INSN_4111                 0x00400000
00517 /* NEC VR4120 instruction.  */
00518 #define INSN_4120                 0x00800000
00519 /* NEC VR5400 instruction.  */
00520 #define INSN_5400             0x01000000
00521 /* NEC VR5500 instruction.  */
00522 #define INSN_5500             0x02000000
00523 
00524 /* MDMX ASE */ 
00525 #define INSN_MDMX                 0x04000000
00526 /* MT ASE */
00527 #define INSN_MT                   0x08000000
00528 /* SmartMIPS ASE  */
00529 #define INSN_SMARTMIPS            0x10000000
00530 /* DSP R2 ASE  */
00531 #define INSN_DSPR2                0x20000000
00532 
00533 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
00534 
00535 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
00536 #define       ISA_MIPS1       (INSN_ISA1)
00537 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
00538 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
00539 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
00540 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
00541 
00542 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
00543 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
00544 
00545 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
00546 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
00547 
00548 
00549 /* CPU defines, use instead of hardcoding processor number. Keep this
00550    in sync with bfd/archures.c in order for machine selection to work.  */
00551 #define CPU_UNKNOWN  0               /* Gas internal use.  */
00552 #define CPU_R3000    3000
00553 #define CPU_R3900    3900
00554 #define CPU_R4000    4000
00555 #define CPU_R4010    4010
00556 #define CPU_VR4100   4100
00557 #define CPU_R4111    4111
00558 #define CPU_VR4120   4120
00559 #define CPU_R4300    4300
00560 #define CPU_R4400    4400
00561 #define CPU_R4600    4600
00562 #define CPU_R4650    4650
00563 #define CPU_R5000    5000
00564 #define CPU_VR5400   5400
00565 #define CPU_VR5500   5500
00566 #define CPU_R6000    6000
00567 #define CPU_RM7000   7000
00568 #define CPU_R8000    8000
00569 #define CPU_RM9000   9000
00570 #define CPU_R10000   10000
00571 #define CPU_R12000   12000
00572 #define CPU_MIPS16   16
00573 #define CPU_MIPS32   32
00574 #define CPU_MIPS32R2 33
00575 #define CPU_MIPS5       5
00576 #define CPU_MIPS64      64
00577 #define CPU_MIPS64R2 65
00578 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
00579 
00580 /* Test for membership in an ISA including chip specific ISAs.  INSN
00581    is pointer to an element of the opcode table; ISA is the specified
00582    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
00583    test, or zero if no CPU specific ISA test is desired.  */
00584 
00585 #define OPCODE_IS_MEMBER(insn, isa, cpu)                       \
00586     (((insn)->membership & isa) != 0                                  \
00587      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)   \
00588      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)  \
00589      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)  \
00590      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)   \
00591      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)  \
00592      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)   \
00593      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                     \
00594         && ((insn)->membership & INSN_10000) != 0)                    \
00595      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)      \
00596      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)   \
00597      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)  \
00598      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)  \
00599      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)  \
00600      || 0)    /* Please keep this term for easier source merging.  */
00601 
00602 /* This is a list of macro expanded instructions.
00603 
00604    _I appended means immediate
00605    _A appended means address
00606    _AB appended means address with base register
00607    _D appended means 64 bit floating point constant
00608    _S appended means 32 bit floating point constant.  */
00609 
00610 enum
00611 {
00612   M_ABS,
00613   M_ADD_I,
00614   M_ADDU_I,
00615   M_AND_I,
00616   M_BALIGN,
00617   M_BEQ,
00618   M_BEQ_I,
00619   M_BEQL_I,
00620   M_BGE,
00621   M_BGEL,
00622   M_BGE_I,
00623   M_BGEL_I,
00624   M_BGEU,
00625   M_BGEUL,
00626   M_BGEU_I,
00627   M_BGEUL_I,
00628   M_BGT,
00629   M_BGTL,
00630   M_BGT_I,
00631   M_BGTL_I,
00632   M_BGTU,
00633   M_BGTUL,
00634   M_BGTU_I,
00635   M_BGTUL_I,
00636   M_BLE,
00637   M_BLEL,
00638   M_BLE_I,
00639   M_BLEL_I,
00640   M_BLEU,
00641   M_BLEUL,
00642   M_BLEU_I,
00643   M_BLEUL_I,
00644   M_BLT,
00645   M_BLTL,
00646   M_BLT_I,
00647   M_BLTL_I,
00648   M_BLTU,
00649   M_BLTUL,
00650   M_BLTU_I,
00651   M_BLTUL_I,
00652   M_BNE,
00653   M_BNE_I,
00654   M_BNEL_I,
00655   M_CACHE_AB,
00656   M_DABS,
00657   M_DADD_I,
00658   M_DADDU_I,
00659   M_DDIV_3,
00660   M_DDIV_3I,
00661   M_DDIVU_3,
00662   M_DDIVU_3I,
00663   M_DEXT,
00664   M_DINS,
00665   M_DIV_3,
00666   M_DIV_3I,
00667   M_DIVU_3,
00668   M_DIVU_3I,
00669   M_DLA_AB,
00670   M_DLCA_AB,
00671   M_DLI,
00672   M_DMUL,
00673   M_DMUL_I,
00674   M_DMULO,
00675   M_DMULO_I,
00676   M_DMULOU,
00677   M_DMULOU_I,
00678   M_DREM_3,
00679   M_DREM_3I,
00680   M_DREMU_3,
00681   M_DREMU_3I,
00682   M_DSUB_I,
00683   M_DSUBU_I,
00684   M_DSUBU_I_2,
00685   M_J_A,
00686   M_JAL_1,
00687   M_JAL_2,
00688   M_JAL_A,
00689   M_L_DOB,
00690   M_L_DAB,
00691   M_LA_AB,
00692   M_LB_A,
00693   M_LB_AB,
00694   M_LBU_A,
00695   M_LBU_AB,
00696   M_LCA_AB,
00697   M_LD_A,
00698   M_LD_OB,
00699   M_LD_AB,
00700   M_LDC1_AB,
00701   M_LDC2_AB,
00702   M_LDC3_AB,
00703   M_LDL_AB,
00704   M_LDR_AB,
00705   M_LH_A,
00706   M_LH_AB,
00707   M_LHU_A,
00708   M_LHU_AB,
00709   M_LI,
00710   M_LI_D,
00711   M_LI_DD,
00712   M_LI_S,
00713   M_LI_SS,
00714   M_LL_AB,
00715   M_LLD_AB,
00716   M_LS_A,
00717   M_LW_A,
00718   M_LW_AB,
00719   M_LWC0_A,
00720   M_LWC0_AB,
00721   M_LWC1_A,
00722   M_LWC1_AB,
00723   M_LWC2_A,
00724   M_LWC2_AB,
00725   M_LWC3_A,
00726   M_LWC3_AB,
00727   M_LWL_A,
00728   M_LWL_AB,
00729   M_LWR_A,
00730   M_LWR_AB,
00731   M_LWU_AB,
00732   M_MOVE,
00733   M_MUL,
00734   M_MUL_I,
00735   M_MULO,
00736   M_MULO_I,
00737   M_MULOU,
00738   M_MULOU_I,
00739   M_NOR_I,
00740   M_OR_I,
00741   M_REM_3,
00742   M_REM_3I,
00743   M_REMU_3,
00744   M_REMU_3I,
00745   M_DROL,
00746   M_ROL,
00747   M_DROL_I,
00748   M_ROL_I,
00749   M_DROR,
00750   M_ROR,
00751   M_DROR_I,
00752   M_ROR_I,
00753   M_S_DA,
00754   M_S_DOB,
00755   M_S_DAB,
00756   M_S_S,
00757   M_SC_AB,
00758   M_SCD_AB,
00759   M_SD_A,
00760   M_SD_OB,
00761   M_SD_AB,
00762   M_SDC1_AB,
00763   M_SDC2_AB,
00764   M_SDC3_AB,
00765   M_SDL_AB,
00766   M_SDR_AB,
00767   M_SEQ,
00768   M_SEQ_I,
00769   M_SGE,
00770   M_SGE_I,
00771   M_SGEU,
00772   M_SGEU_I,
00773   M_SGT,
00774   M_SGT_I,
00775   M_SGTU,
00776   M_SGTU_I,
00777   M_SLE,
00778   M_SLE_I,
00779   M_SLEU,
00780   M_SLEU_I,
00781   M_SLT_I,
00782   M_SLTU_I,
00783   M_SNE,
00784   M_SNE_I,
00785   M_SB_A,
00786   M_SB_AB,
00787   M_SH_A,
00788   M_SH_AB,
00789   M_SW_A,
00790   M_SW_AB,
00791   M_SWC0_A,
00792   M_SWC0_AB,
00793   M_SWC1_A,
00794   M_SWC1_AB,
00795   M_SWC2_A,
00796   M_SWC2_AB,
00797   M_SWC3_A,
00798   M_SWC3_AB,
00799   M_SWL_A,
00800   M_SWL_AB,
00801   M_SWR_A,
00802   M_SWR_AB,
00803   M_SUB_I,
00804   M_SUBU_I,
00805   M_SUBU_I_2,
00806   M_TEQ_I,
00807   M_TGE_I,
00808   M_TGEU_I,
00809   M_TLT_I,
00810   M_TLTU_I,
00811   M_TNE_I,
00812   M_TRUNCWD,
00813   M_TRUNCWS,
00814   M_ULD,
00815   M_ULD_A,
00816   M_ULH,
00817   M_ULH_A,
00818   M_ULHU,
00819   M_ULHU_A,
00820   M_ULW,
00821   M_ULW_A,
00822   M_USH,
00823   M_USH_A,
00824   M_USW,
00825   M_USW_A,
00826   M_USD,
00827   M_USD_A,
00828   M_XOR_I,
00829   M_COP0,
00830   M_COP1,
00831   M_COP2,
00832   M_COP3,
00833   M_NUM_MACROS
00834 };
00835 
00836 
00837 /* The order of overloaded instructions matters.  Label arguments and
00838    register arguments look the same. Instructions that can have either
00839    for arguments must apear in the correct order in this table for the
00840    assembler to pick the right one. In other words, entries with
00841    immediate operands must apear after the same instruction with
00842    registers.
00843 
00844    Many instructions are short hand for other instructions (i.e., The
00845    jal <register> instruction is short for jalr <register>).  */
00846 
00847 extern const struct mips_opcode mips_builtin_opcodes[];
00848 extern const int bfd_mips_num_builtin_opcodes;
00849 extern struct mips_opcode *mips_opcodes;
00850 extern int bfd_mips_num_opcodes;
00851 #define NUMOPCODES bfd_mips_num_opcodes
00852 
00853 
00854 /* The rest of this file adds definitions for the mips16 TinyRISC
00855    processor.  */
00856 
00857 /* These are the bitmasks and shift counts used for the different
00858    fields in the instruction formats.  Other than OP, no masks are
00859    provided for the fixed portions of an instruction, since they are
00860    not needed.
00861 
00862    The I format uses IMM11.
00863 
00864    The RI format uses RX and IMM8.
00865 
00866    The RR format uses RX, and RY.
00867 
00868    The RRI format uses RX, RY, and IMM5.
00869 
00870    The RRR format uses RX, RY, and RZ.
00871 
00872    The RRI_A format uses RX, RY, and IMM4.
00873 
00874    The SHIFT format uses RX, RY, and SHAMT.
00875 
00876    The I8 format uses IMM8.
00877 
00878    The I8_MOVR32 format uses RY and REGR32.
00879 
00880    The IR_MOV32R format uses REG32R and MOV32Z.
00881 
00882    The I64 format uses IMM8.
00883 
00884    The RI64 format uses RY and IMM5.
00885    */
00886 
00887 #define MIPS16OP_MASK_OP    0x1f
00888 #define MIPS16OP_SH_OP             11
00889 #define MIPS16OP_MASK_IMM11 0x7ff
00890 #define MIPS16OP_SH_IMM11   0
00891 #define MIPS16OP_MASK_RX    0x7
00892 #define MIPS16OP_SH_RX             8
00893 #define MIPS16OP_MASK_IMM8  0xff
00894 #define MIPS16OP_SH_IMM8    0
00895 #define MIPS16OP_MASK_RY    0x7
00896 #define MIPS16OP_SH_RY             5
00897 #define MIPS16OP_MASK_IMM5  0x1f
00898 #define MIPS16OP_SH_IMM5    0
00899 #define MIPS16OP_MASK_RZ    0x7
00900 #define MIPS16OP_SH_RZ             2
00901 #define MIPS16OP_MASK_IMM4  0xf
00902 #define MIPS16OP_SH_IMM4    0
00903 #define MIPS16OP_MASK_REGR32       0x1f
00904 #define MIPS16OP_SH_REGR32  0
00905 #define MIPS16OP_MASK_REG32R       0x1f
00906 #define MIPS16OP_SH_REG32R  3
00907 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
00908 #define MIPS16OP_MASK_MOVE32Z      0x7
00909 #define MIPS16OP_SH_MOVE32Z 0
00910 #define MIPS16OP_MASK_IMM6  0x3f
00911 #define MIPS16OP_SH_IMM6    5
00912 
00913 /* These are the characters which may appears in the args field of an
00914    instruction.  They appear in the order in which the fields appear
00915    when the instruction is used.  Commas and parentheses in the args
00916    string are ignored when assembling, and written into the output
00917    when disassembling.
00918 
00919    "y" 3 bit register (MIPS16OP_*_RY)
00920    "x" 3 bit register (MIPS16OP_*_RX)
00921    "z" 3 bit register (MIPS16OP_*_RZ)
00922    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
00923    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
00924    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
00925    "0" zero register ($0)
00926    "S" stack pointer ($sp or $29)
00927    "P" program counter
00928    "R" return address register ($ra or $31)
00929    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
00930    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
00931    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
00932    "a" 26 bit jump address
00933    "e" 11 bit extension value
00934    "l" register list for entry instruction
00935    "L" register list for exit instruction
00936 
00937    The remaining codes may be extended.  Except as otherwise noted,
00938    the full extended operand is a 16 bit signed value.
00939    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
00940    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
00941    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
00942    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
00943    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
00944    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
00945    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
00946    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
00947    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
00948    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
00949    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
00950    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
00951    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
00952    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
00953    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
00954    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
00955    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
00956    "q" 11 bit branch address (MIPS16OP_*_IMM11)
00957    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
00958    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
00959    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
00960    "m" 7 bit register list for save instruction (18 bit extended)
00961    "M" 7 bit register list for restore instruction (18 bit extended)
00962   */
00963 
00964 /* Save/restore encoding for the args field when all 4 registers are
00965    either saved as arguments or saved/restored as statics.  */
00966 #define MIPS16_ALL_ARGS    0xe
00967 #define MIPS16_ALL_STATICS 0xb
00968 
00969 /* For the mips16, we use the same opcode table format and a few of
00970    the same flags.  However, most of the flags are different.  */
00971 
00972 /* Modifies the register in MIPS16OP_*_RX.  */
00973 #define MIPS16_INSN_WRITE_X            0x00000001
00974 /* Modifies the register in MIPS16OP_*_RY.  */
00975 #define MIPS16_INSN_WRITE_Y            0x00000002
00976 /* Modifies the register in MIPS16OP_*_RZ.  */
00977 #define MIPS16_INSN_WRITE_Z            0x00000004
00978 /* Modifies the T ($24) register.  */
00979 #define MIPS16_INSN_WRITE_T            0x00000008
00980 /* Modifies the SP ($29) register.  */
00981 #define MIPS16_INSN_WRITE_SP                  0x00000010
00982 /* Modifies the RA ($31) register.  */
00983 #define MIPS16_INSN_WRITE_31                  0x00000020
00984 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
00985 #define MIPS16_INSN_WRITE_GPR_Y               0x00000040
00986 /* Reads the register in MIPS16OP_*_RX.  */
00987 #define MIPS16_INSN_READ_X             0x00000080
00988 /* Reads the register in MIPS16OP_*_RY.  */
00989 #define MIPS16_INSN_READ_Y             0x00000100
00990 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
00991 #define MIPS16_INSN_READ_Z             0x00000200
00992 /* Reads the T ($24) register.  */
00993 #define MIPS16_INSN_READ_T             0x00000400
00994 /* Reads the SP ($29) register.  */
00995 #define MIPS16_INSN_READ_SP            0x00000800
00996 /* Reads the RA ($31) register.  */
00997 #define MIPS16_INSN_READ_31            0x00001000
00998 /* Reads the program counter.  */
00999 #define MIPS16_INSN_READ_PC            0x00002000
01000 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
01001 #define MIPS16_INSN_READ_GPR_X                0x00004000
01002 /* Is a branch insn. */
01003 #define MIPS16_INSN_BRANCH                  0x00010000
01004 
01005 /* The following flags have the same value for the mips16 opcode
01006    table:
01007    INSN_UNCOND_BRANCH_DELAY
01008    INSN_COND_BRANCH_DELAY
01009    INSN_COND_BRANCH_LIKELY (never used)
01010    INSN_READ_HI
01011    INSN_READ_LO
01012    INSN_WRITE_HI
01013    INSN_WRITE_LO
01014    INSN_TRAP
01015    INSN_ISA3
01016    */
01017 
01018 extern const struct mips_opcode mips16_opcodes[];
01019 extern const int bfd_mips16_num_opcodes;
01020 
01021 #endif /* _MIPS_H_ */