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cell-binutils  2.17cvs20070401
Classes | Defines | Enumerations | Variables
mips.h File Reference
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Classes

struct  mips_opcode

Defines

#define OP_MASK_OP   0x3f
#define OP_SH_OP   26
#define OP_MASK_RS   0x1f
#define OP_SH_RS   21
#define OP_MASK_FR   0x1f
#define OP_SH_FR   21
#define OP_MASK_FMT   0x1f
#define OP_SH_FMT   21
#define OP_MASK_BCC   0x7
#define OP_SH_BCC   18
#define OP_MASK_CODE   0x3ff
#define OP_SH_CODE   16
#define OP_MASK_CODE2   0x3ff
#define OP_SH_CODE2   6
#define OP_MASK_RT   0x1f
#define OP_SH_RT   16
#define OP_MASK_FT   0x1f
#define OP_SH_FT   16
#define OP_MASK_CACHE   0x1f
#define OP_SH_CACHE   16
#define OP_MASK_RD   0x1f
#define OP_SH_RD   11
#define OP_MASK_FS   0x1f
#define OP_SH_FS   11
#define OP_MASK_PREFX   0x1f
#define OP_SH_PREFX   11
#define OP_MASK_CCC   0x7
#define OP_SH_CCC   8
#define OP_MASK_CODE20   0xfffff /* 20 bit syscall/breakpoint code. */
#define OP_SH_CODE20   6
#define OP_MASK_SHAMT   0x1f
#define OP_SH_SHAMT   6
#define OP_MASK_FD   0x1f
#define OP_SH_FD   6
#define OP_MASK_TARGET   0x3ffffff
#define OP_SH_TARGET   0
#define OP_MASK_COPZ   0x1ffffff
#define OP_SH_COPZ   0
#define OP_MASK_IMMEDIATE   0xffff
#define OP_SH_IMMEDIATE   0
#define OP_MASK_DELTA   0xffff
#define OP_SH_DELTA   0
#define OP_MASK_FUNCT   0x3f
#define OP_SH_FUNCT   0
#define OP_MASK_SPEC   0x3f
#define OP_SH_SPEC   0
#define OP_SH_LOCC   8 /* FP condition code. */
#define OP_SH_HICC   18 /* FP condition code. */
#define OP_MASK_CC   0x7
#define OP_SH_COP1NORM   25 /* Normal COP1 encoding. */
#define OP_MASK_COP1NORM   0x1 /* a single bit. */
#define OP_SH_COP1SPEC   21 /* COP1 encodings. */
#define OP_MASK_COP1SPEC   0xf
#define OP_MASK_COP1SCLR   0x4
#define OP_MASK_COP1CMP   0x3
#define OP_SH_COP1CMP   4
#define OP_SH_FORMAT   21 /* FP short format field. */
#define OP_MASK_FORMAT   0x7
#define OP_SH_TRUE   16
#define OP_MASK_TRUE   0x1
#define OP_SH_GE   17
#define OP_MASK_GE   0x01
#define OP_SH_UNSIGNED   16
#define OP_MASK_UNSIGNED   0x1
#define OP_SH_HINT   16
#define OP_MASK_HINT   0x1f
#define OP_SH_MMI   0 /* Multimedia (parallel) op. */
#define OP_MASK_MMI   0x3f
#define OP_SH_MMISUB   6
#define OP_MASK_MMISUB   0x1f
#define OP_MASK_PERFREG   0x1f /* Performance monitoring. */
#define OP_SH_PERFREG   1
#define OP_SH_SEL   0 /* Coprocessor select field. */
#define OP_MASK_SEL   0x7 /* The sel field of mfcZ and mtcZ. */
#define OP_SH_CODE19   6 /* 19 bit wait code. */
#define OP_MASK_CODE19   0x7ffff
#define OP_SH_ALN   21
#define OP_MASK_ALN   0x7
#define OP_SH_VSEL   21
#define OP_MASK_VSEL   0x1f
#define OP_MASK_VECBYTE
#define OP_SH_VECBYTE   22
#define OP_MASK_VECALIGN   0x7 /* Vector byte-align (alni.ob) op. */
#define OP_SH_VECALIGN   21
#define OP_MASK_INSMSB   0x1f /* "ins" MSB. */
#define OP_SH_INSMSB   11
#define OP_MASK_EXTMSBD   0x1f /* "ext" MSBD. */
#define OP_SH_EXTMSBD   11
#define OP_SH_DSPACC   11
#define OP_MASK_DSPACC   0x3
#define OP_SH_DSPACC_S   21
#define OP_MASK_DSPACC_S   0x3
#define OP_SH_DSPSFT   20
#define OP_MASK_DSPSFT   0x3f
#define OP_SH_DSPSFT_7   19
#define OP_MASK_DSPSFT_7   0x7f
#define OP_SH_SA3   21
#define OP_MASK_SA3   0x7
#define OP_SH_SA4   21
#define OP_MASK_SA4   0xf
#define OP_SH_IMM8   16
#define OP_MASK_IMM8   0xff
#define OP_SH_IMM10   16
#define OP_MASK_IMM10   0x3ff
#define OP_SH_WRDSP   11
#define OP_MASK_WRDSP   0x3f
#define OP_SH_RDDSP   16
#define OP_MASK_RDDSP   0x3f
#define OP_SH_BP   11
#define OP_MASK_BP   0x3
#define OP_SH_MT_U   5
#define OP_MASK_MT_U   0x1
#define OP_SH_MT_H   4
#define OP_MASK_MT_H   0x1
#define OP_SH_MTACC_T   18
#define OP_MASK_MTACC_T   0x3
#define OP_SH_MTACC_D   13
#define OP_MASK_MTACC_D   0x3
#define OP_OP_COP0   0x10
#define OP_OP_COP1   0x11
#define OP_OP_COP2   0x12
#define OP_OP_COP3   0x13
#define OP_OP_LWC1   0x31
#define OP_OP_LWC2   0x32
#define OP_OP_LWC3   0x33 /* a.k.a. pref */
#define OP_OP_LDC1   0x35
#define OP_OP_LDC2   0x36
#define OP_OP_LDC3   0x37 /* a.k.a. ld */
#define OP_OP_SWC1   0x39
#define OP_OP_SWC2   0x3a
#define OP_OP_SWC3   0x3b
#define OP_OP_SDC1   0x3d
#define OP_OP_SDC2   0x3e
#define OP_OP_SDC3   0x3f /* a.k.a. sd */
#define MDMX_FMTSEL_IMM_QH   0x1d
#define MDMX_FMTSEL_IMM_OB   0x1e
#define MDMX_FMTSEL_VEC_QH   0x15
#define MDMX_FMTSEL_VEC_OB   0x16
#define OP_SH_UDI1   6
#define OP_MASK_UDI1   0x1f
#define OP_SH_UDI2   6
#define OP_MASK_UDI2   0x3ff
#define OP_SH_UDI3   6
#define OP_MASK_UDI3   0x7fff
#define OP_SH_UDI4   6
#define OP_MASK_UDI4   0xfffff
#define INSN_WRITE_GPR_D   0x00000001
#define INSN_WRITE_GPR_T   0x00000002
#define INSN_WRITE_GPR_31   0x00000004
#define INSN_WRITE_FPR_D   0x00000008
#define INSN_WRITE_FPR_S   0x00000010
#define INSN_WRITE_FPR_T   0x00000020
#define INSN_READ_GPR_S   0x00000040
#define INSN_READ_GPR_T   0x00000080
#define INSN_READ_FPR_S   0x00000100
#define INSN_READ_FPR_T   0x00000200
#define INSN_READ_FPR_R   0x00000400
#define INSN_WRITE_COND_CODE   0x00000800
#define INSN_READ_COND_CODE   0x00001000
#define INSN_TLB   0x00002000
#define INSN_COP   0x00004000
#define INSN_LOAD_MEMORY_DELAY   0x00008000
#define INSN_LOAD_COPROC_DELAY   0x00010000
#define INSN_UNCOND_BRANCH_DELAY   0x00020000
#define INSN_COND_BRANCH_DELAY   0x00040000
#define INSN_COND_BRANCH_LIKELY   0x00080000
#define INSN_COPROC_MOVE_DELAY   0x00100000
#define INSN_COPROC_MEMORY_DELAY   0x00200000
#define INSN_READ_HI   0x00400000
#define INSN_READ_LO   0x00800000
#define INSN_WRITE_HI   0x01000000
#define INSN_WRITE_LO   0x02000000
#define INSN_TRAP   0x04000000
#define INSN_STORE_MEMORY   0x08000000
#define FP_S   0x10000000
#define FP_D   0x20000000
#define INSN_MULT   0x40000000
#define INSN_SYNC   0x80000000
#define INSN2_ALIAS   0x00000001
#define INSN2_READ_MDMX_ACC   0x00000002
#define INSN2_WRITE_MDMX_ACC   0x00000004
#define INSN_MACRO   0xffffffff
#define INSN_ISA_MASK   0x00000fff
#define INSN_ISA1   0x00000001
#define INSN_ISA2   0x00000002
#define INSN_ISA3   0x00000004
#define INSN_ISA4   0x00000008
#define INSN_ISA5   0x00000010
#define INSN_ISA32   0x00000020
#define INSN_ISA64   0x00000040
#define INSN_ISA32R2   0x00000080
#define INSN_ISA64R2   0x00000100
#define INSN_ASE_MASK   0x3c00f000
#define INSN_DSP   0x00001000
#define INSN_DSP64   0x00002000
#define INSN_MIPS16   0x00004000
#define INSN_MIPS3D   0x00008000
#define INSN_4650   0x00010000
#define INSN_4010   0x00020000
#define INSN_4100   0x00040000
#define INSN_3900   0x00080000
#define INSN_10000   0x00100000
#define INSN_SB1   0x00200000
#define INSN_4111   0x00400000
#define INSN_4120   0x00800000
#define INSN_5400   0x01000000
#define INSN_5500   0x02000000
#define INSN_MDMX   0x04000000
#define INSN_MT   0x08000000
#define INSN_SMARTMIPS   0x10000000
#define INSN_DSPR2   0x20000000
#define ISA_UNKNOWN   0 /* Gas internal use. */
#define ISA_MIPS1   (INSN_ISA1)
#define ISA_MIPS2   (ISA_MIPS1 | INSN_ISA2)
#define ISA_MIPS3   (ISA_MIPS2 | INSN_ISA3)
#define ISA_MIPS4   (ISA_MIPS3 | INSN_ISA4)
#define ISA_MIPS5   (ISA_MIPS4 | INSN_ISA5)
#define ISA_MIPS32   (ISA_MIPS2 | INSN_ISA32)
#define ISA_MIPS64   (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
#define ISA_MIPS32R2   (ISA_MIPS32 | INSN_ISA32R2)
#define ISA_MIPS64R2   (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
#define CPU_UNKNOWN   0 /* Gas internal use. */
#define CPU_R3000   3000
#define CPU_R3900   3900
#define CPU_R4000   4000
#define CPU_R4010   4010
#define CPU_VR4100   4100
#define CPU_R4111   4111
#define CPU_VR4120   4120
#define CPU_R4300   4300
#define CPU_R4400   4400
#define CPU_R4600   4600
#define CPU_R4650   4650
#define CPU_R5000   5000
#define CPU_VR5400   5400
#define CPU_VR5500   5500
#define CPU_R6000   6000
#define CPU_RM7000   7000
#define CPU_R8000   8000
#define CPU_RM9000   9000
#define CPU_R10000   10000
#define CPU_R12000   12000
#define CPU_MIPS16   16
#define CPU_MIPS32   32
#define CPU_MIPS32R2   33
#define CPU_MIPS5   5
#define CPU_MIPS64   64
#define CPU_MIPS64R2   65
#define CPU_SB1   12310201 /* octal 'SB', 01. */
#define OPCODE_IS_MEMBER(insn, isa, cpu)
#define NUMOPCODES   bfd_mips_num_opcodes
#define MIPS16OP_MASK_OP   0x1f
#define MIPS16OP_SH_OP   11
#define MIPS16OP_MASK_IMM11   0x7ff
#define MIPS16OP_SH_IMM11   0
#define MIPS16OP_MASK_RX   0x7
#define MIPS16OP_SH_RX   8
#define MIPS16OP_MASK_IMM8   0xff
#define MIPS16OP_SH_IMM8   0
#define MIPS16OP_MASK_RY   0x7
#define MIPS16OP_SH_RY   5
#define MIPS16OP_MASK_IMM5   0x1f
#define MIPS16OP_SH_IMM5   0
#define MIPS16OP_MASK_RZ   0x7
#define MIPS16OP_SH_RZ   2
#define MIPS16OP_MASK_IMM4   0xf
#define MIPS16OP_SH_IMM4   0
#define MIPS16OP_MASK_REGR32   0x1f
#define MIPS16OP_SH_REGR32   0
#define MIPS16OP_MASK_REG32R   0x1f
#define MIPS16OP_SH_REG32R   3
#define MIPS16OP_EXTRACT_REG32R(i)   ((((i) >> 5) & 7) | ((i) & 0x18))
#define MIPS16OP_MASK_MOVE32Z   0x7
#define MIPS16OP_SH_MOVE32Z   0
#define MIPS16OP_MASK_IMM6   0x3f
#define MIPS16OP_SH_IMM6   5
#define MIPS16_ALL_ARGS   0xe
#define MIPS16_ALL_STATICS   0xb
#define MIPS16_INSN_WRITE_X   0x00000001
#define MIPS16_INSN_WRITE_Y   0x00000002
#define MIPS16_INSN_WRITE_Z   0x00000004
#define MIPS16_INSN_WRITE_T   0x00000008
#define MIPS16_INSN_WRITE_SP   0x00000010
#define MIPS16_INSN_WRITE_31   0x00000020
#define MIPS16_INSN_WRITE_GPR_Y   0x00000040
#define MIPS16_INSN_READ_X   0x00000080
#define MIPS16_INSN_READ_Y   0x00000100
#define MIPS16_INSN_READ_Z   0x00000200
#define MIPS16_INSN_READ_T   0x00000400
#define MIPS16_INSN_READ_SP   0x00000800
#define MIPS16_INSN_READ_31   0x00001000
#define MIPS16_INSN_READ_PC   0x00002000
#define MIPS16_INSN_READ_GPR_X   0x00004000
#define MIPS16_INSN_BRANCH   0x00010000

Enumerations

enum  {
  M_ABS, M_ADD_I, M_ADDU_I, M_AND_I,
  M_BALIGN, M_BEQ, M_BEQ_I, M_BEQL_I,
  M_BGE, M_BGEL, M_BGE_I, M_BGEL_I,
  M_BGEU, M_BGEUL, M_BGEU_I, M_BGEUL_I,
  M_BGT, M_BGTL, M_BGT_I, M_BGTL_I,
  M_BGTU, M_BGTUL, M_BGTU_I, M_BGTUL_I,
  M_BLE, M_BLEL, M_BLE_I, M_BLEL_I,
  M_BLEU, M_BLEUL, M_BLEU_I, M_BLEUL_I,
  M_BLT, M_BLTL, M_BLT_I, M_BLTL_I,
  M_BLTU, M_BLTUL, M_BLTU_I, M_BLTUL_I,
  M_BNE, M_BNE_I, M_BNEL_I, M_CACHE_AB,
  M_DABS, M_DADD_I, M_DADDU_I, M_DDIV_3,
  M_DDIV_3I, M_DDIVU_3, M_DDIVU_3I, M_DEXT,
  M_DINS, M_DIV_3, M_DIV_3I, M_DIVU_3,
  M_DIVU_3I, M_DLA_AB, M_DLCA_AB, M_DLI,
  M_DMUL, M_DMUL_I, M_DMULO, M_DMULO_I,
  M_DMULOU, M_DMULOU_I, M_DREM_3, M_DREM_3I,
  M_DREMU_3, M_DREMU_3I, M_DSUB_I, M_DSUBU_I,
  M_DSUBU_I_2, M_J_A, M_JAL_1, M_JAL_2,
  M_JAL_A, M_L_DOB, M_L_DAB, M_LA_AB,
  M_LB_A, M_LB_AB, M_LBU_A, M_LBU_AB,
  M_LCA_AB, M_LD_A, M_LD_OB, M_LD_AB,
  M_LDC1_AB, M_LDC2_AB, M_LDC3_AB, M_LDL_AB,
  M_LDR_AB, M_LH_A, M_LH_AB, M_LHU_A,
  M_LHU_AB, M_LI, M_LI_D, M_LI_DD,
  M_LI_S, M_LI_SS, M_LL_AB, M_LLD_AB,
  M_LS_A, M_LW_A, M_LW_AB, M_LWC0_A,
  M_LWC0_AB, M_LWC1_A, M_LWC1_AB, M_LWC2_A,
  M_LWC2_AB, M_LWC3_A, M_LWC3_AB, M_LWL_A,
  M_LWL_AB, M_LWR_A, M_LWR_AB, M_LWU_AB,
  M_MOVE, M_MUL, M_MUL_I, M_MULO,
  M_MULO_I, M_MULOU, M_MULOU_I, M_NOR_I,
  M_OR_I, M_REM_3, M_REM_3I, M_REMU_3,
  M_REMU_3I, M_DROL, M_ROL, M_DROL_I,
  M_ROL_I, M_DROR, M_ROR, M_DROR_I,
  M_ROR_I, M_S_DA, M_S_DOB, M_S_DAB,
  M_S_S, M_SC_AB, M_SCD_AB, M_SD_A,
  M_SD_OB, M_SD_AB, M_SDC1_AB, M_SDC2_AB,
  M_SDC3_AB, M_SDL_AB, M_SDR_AB, M_SEQ,
  M_SEQ_I, M_SGE, M_SGE_I, M_SGEU,
  M_SGEU_I, M_SGT, M_SGT_I, M_SGTU,
  M_SGTU_I, M_SLE, M_SLE_I, M_SLEU,
  M_SLEU_I, M_SLT_I, M_SLTU_I, M_SNE,
  M_SNE_I, M_SB_A, M_SB_AB, M_SH_A,
  M_SH_AB, M_SW_A, M_SW_AB, M_SWC0_A,
  M_SWC0_AB, M_SWC1_A, M_SWC1_AB, M_SWC2_A,
  M_SWC2_AB, M_SWC3_A, M_SWC3_AB, M_SWL_A,
  M_SWL_AB, M_SWR_A, M_SWR_AB, M_SUB_I,
  M_SUBU_I, M_SUBU_I_2, M_TEQ_I, M_TGE_I,
  M_TGEU_I, M_TLT_I, M_TLTU_I, M_TNE_I,
  M_TRUNCWD, M_TRUNCWS, M_ULD, M_ULD_A,
  M_ULH, M_ULH_A, M_ULHU, M_ULHU_A,
  M_ULW, M_ULW_A, M_USH, M_USH_A,
  M_USW, M_USW_A, M_USD, M_USD_A,
  M_XOR_I, M_COP0, M_COP1, M_COP2,
  M_COP3, M_NUM_MACROS
}

Variables

const int bfd_mips_num_builtin_opcodes
struct mips_opcodemips_opcodes
int bfd_mips_num_opcodes
const int bfd_mips16_num_opcodes

Class Documentation

struct mips_opcode

Definition at line 219 of file mips.h.

Class Members
const char * args
unsigned long mask
unsigned long match
unsigned long membership
const char * name
unsigned long pinfo
unsigned long pinfo2

Define Documentation

#define CPU_MIPS16   16

Definition at line 571 of file mips.h.

#define CPU_MIPS32   32

Definition at line 572 of file mips.h.

#define CPU_MIPS32R2   33

Definition at line 573 of file mips.h.

#define CPU_MIPS5   5

Definition at line 574 of file mips.h.

#define CPU_MIPS64   64

Definition at line 575 of file mips.h.

#define CPU_MIPS64R2   65

Definition at line 576 of file mips.h.

#define CPU_R10000   10000

Definition at line 569 of file mips.h.

#define CPU_R12000   12000

Definition at line 570 of file mips.h.

#define CPU_R3000   3000

Definition at line 551 of file mips.h.

#define CPU_R3900   3900

Definition at line 552 of file mips.h.

#define CPU_R4000   4000

Definition at line 553 of file mips.h.

#define CPU_R4010   4010

Definition at line 554 of file mips.h.

#define CPU_R4111   4111

Definition at line 556 of file mips.h.

#define CPU_R4300   4300

Definition at line 558 of file mips.h.

#define CPU_R4400   4400

Definition at line 559 of file mips.h.

#define CPU_R4600   4600

Definition at line 560 of file mips.h.

#define CPU_R4650   4650

Definition at line 561 of file mips.h.

#define CPU_R5000   5000

Definition at line 562 of file mips.h.

#define CPU_R6000   6000

Definition at line 565 of file mips.h.

#define CPU_R8000   8000

Definition at line 567 of file mips.h.

#define CPU_RM7000   7000

Definition at line 566 of file mips.h.

#define CPU_RM9000   9000

Definition at line 568 of file mips.h.

#define CPU_SB1   12310201 /* octal 'SB', 01. */

Definition at line 577 of file mips.h.

#define CPU_UNKNOWN   0 /* Gas internal use. */

Definition at line 550 of file mips.h.

#define CPU_VR4100   4100

Definition at line 555 of file mips.h.

#define CPU_VR4120   4120

Definition at line 557 of file mips.h.

#define CPU_VR5400   5400

Definition at line 563 of file mips.h.

#define CPU_VR5500   5500

Definition at line 564 of file mips.h.

#define FP_D   0x20000000

Definition at line 453 of file mips.h.

#define FP_S   0x10000000

Definition at line 451 of file mips.h.

#define INSN2_ALIAS   0x00000001

Definition at line 463 of file mips.h.

#define INSN2_READ_MDMX_ACC   0x00000002

Definition at line 465 of file mips.h.

#define INSN2_WRITE_MDMX_ACC   0x00000004

Definition at line 467 of file mips.h.

#define INSN_10000   0x00100000

Definition at line 511 of file mips.h.

#define INSN_3900   0x00080000

Definition at line 509 of file mips.h.

#define INSN_4010   0x00020000

Definition at line 505 of file mips.h.

#define INSN_4100   0x00040000

Definition at line 507 of file mips.h.

#define INSN_4111   0x00400000

Definition at line 515 of file mips.h.

#define INSN_4120   0x00800000

Definition at line 517 of file mips.h.

#define INSN_4650   0x00010000

Definition at line 503 of file mips.h.

#define INSN_5400   0x01000000

Definition at line 519 of file mips.h.

#define INSN_5500   0x02000000

Definition at line 521 of file mips.h.

#define INSN_ASE_MASK   0x3c00f000

Definition at line 490 of file mips.h.

#define INSN_COND_BRANCH_DELAY   0x00040000

Definition at line 431 of file mips.h.

#define INSN_COND_BRANCH_LIKELY   0x00080000

Definition at line 433 of file mips.h.

#define INSN_COP   0x00004000

Definition at line 423 of file mips.h.

#define INSN_COPROC_MEMORY_DELAY   0x00200000

Definition at line 437 of file mips.h.

#define INSN_COPROC_MOVE_DELAY   0x00100000

Definition at line 435 of file mips.h.

#define INSN_DSP   0x00001000

Definition at line 493 of file mips.h.

#define INSN_DSP64   0x00002000

Definition at line 494 of file mips.h.

#define INSN_DSPR2   0x20000000

Definition at line 530 of file mips.h.

#define INSN_ISA1   0x00000001

Definition at line 479 of file mips.h.

#define INSN_ISA2   0x00000002

Definition at line 480 of file mips.h.

#define INSN_ISA3   0x00000004

Definition at line 481 of file mips.h.

#define INSN_ISA32   0x00000020

Definition at line 484 of file mips.h.

#define INSN_ISA32R2   0x00000080

Definition at line 486 of file mips.h.

#define INSN_ISA4   0x00000008

Definition at line 482 of file mips.h.

#define INSN_ISA5   0x00000010

Definition at line 483 of file mips.h.

#define INSN_ISA64   0x00000040

Definition at line 485 of file mips.h.

#define INSN_ISA64R2   0x00000100

Definition at line 487 of file mips.h.

#define INSN_ISA_MASK   0x00000fff

Definition at line 478 of file mips.h.

#define INSN_LOAD_COPROC_DELAY   0x00010000

Definition at line 427 of file mips.h.

#define INSN_LOAD_MEMORY_DELAY   0x00008000

Definition at line 425 of file mips.h.

#define INSN_MACRO   0xffffffff

Definition at line 471 of file mips.h.

#define INSN_MDMX   0x04000000

Definition at line 524 of file mips.h.

#define INSN_MIPS16   0x00004000

Definition at line 496 of file mips.h.

#define INSN_MIPS3D   0x00008000

Definition at line 498 of file mips.h.

#define INSN_MT   0x08000000

Definition at line 526 of file mips.h.

#define INSN_MULT   0x40000000

Definition at line 455 of file mips.h.

#define INSN_READ_COND_CODE   0x00001000

Definition at line 419 of file mips.h.

#define INSN_READ_FPR_R   0x00000400

Definition at line 415 of file mips.h.

#define INSN_READ_FPR_S   0x00000100

Definition at line 411 of file mips.h.

#define INSN_READ_FPR_T   0x00000200

Definition at line 413 of file mips.h.

#define INSN_READ_GPR_S   0x00000040

Definition at line 407 of file mips.h.

#define INSN_READ_GPR_T   0x00000080

Definition at line 409 of file mips.h.

#define INSN_READ_HI   0x00400000

Definition at line 439 of file mips.h.

#define INSN_READ_LO   0x00800000

Definition at line 441 of file mips.h.

#define INSN_SB1   0x00200000

Definition at line 513 of file mips.h.

#define INSN_SMARTMIPS   0x10000000

Definition at line 528 of file mips.h.

#define INSN_STORE_MEMORY   0x08000000

Definition at line 449 of file mips.h.

#define INSN_SYNC   0x80000000

Definition at line 457 of file mips.h.

#define INSN_TLB   0x00002000

Definition at line 421 of file mips.h.

#define INSN_TRAP   0x04000000

Definition at line 447 of file mips.h.

#define INSN_UNCOND_BRANCH_DELAY   0x00020000

Definition at line 429 of file mips.h.

#define INSN_WRITE_COND_CODE   0x00000800

Definition at line 417 of file mips.h.

#define INSN_WRITE_FPR_D   0x00000008

Definition at line 401 of file mips.h.

#define INSN_WRITE_FPR_S   0x00000010

Definition at line 403 of file mips.h.

#define INSN_WRITE_FPR_T   0x00000020

Definition at line 405 of file mips.h.

#define INSN_WRITE_GPR_31   0x00000004

Definition at line 399 of file mips.h.

#define INSN_WRITE_GPR_D   0x00000001

Definition at line 395 of file mips.h.

#define INSN_WRITE_GPR_T   0x00000002

Definition at line 397 of file mips.h.

#define INSN_WRITE_HI   0x01000000

Definition at line 443 of file mips.h.

#define INSN_WRITE_LO   0x02000000

Definition at line 445 of file mips.h.

#define ISA_MIPS1   (INSN_ISA1)

Definition at line 535 of file mips.h.

#define ISA_MIPS2   (ISA_MIPS1 | INSN_ISA2)

Definition at line 536 of file mips.h.

#define ISA_MIPS3   (ISA_MIPS2 | INSN_ISA3)

Definition at line 537 of file mips.h.

#define ISA_MIPS32   (ISA_MIPS2 | INSN_ISA32)

Definition at line 541 of file mips.h.

Definition at line 544 of file mips.h.

#define ISA_MIPS4   (ISA_MIPS3 | INSN_ISA4)

Definition at line 538 of file mips.h.

#define ISA_MIPS5   (ISA_MIPS4 | INSN_ISA5)

Definition at line 539 of file mips.h.

Definition at line 542 of file mips.h.

Definition at line 545 of file mips.h.

#define ISA_UNKNOWN   0 /* Gas internal use. */

Definition at line 534 of file mips.h.

#define MDMX_FMTSEL_IMM_OB   0x1e

Definition at line 203 of file mips.h.

#define MDMX_FMTSEL_IMM_QH   0x1d

Definition at line 202 of file mips.h.

#define MDMX_FMTSEL_VEC_OB   0x16

Definition at line 205 of file mips.h.

#define MDMX_FMTSEL_VEC_QH   0x15

Definition at line 204 of file mips.h.

#define MIPS16_ALL_ARGS   0xe

Definition at line 965 of file mips.h.

#define MIPS16_ALL_STATICS   0xb

Definition at line 966 of file mips.h.

#define MIPS16_INSN_BRANCH   0x00010000

Definition at line 1002 of file mips.h.

#define MIPS16_INSN_READ_31   0x00001000

Definition at line 996 of file mips.h.

#define MIPS16_INSN_READ_GPR_X   0x00004000

Definition at line 1000 of file mips.h.

#define MIPS16_INSN_READ_PC   0x00002000

Definition at line 998 of file mips.h.

#define MIPS16_INSN_READ_SP   0x00000800

Definition at line 994 of file mips.h.

#define MIPS16_INSN_READ_T   0x00000400

Definition at line 992 of file mips.h.

#define MIPS16_INSN_READ_X   0x00000080

Definition at line 986 of file mips.h.

#define MIPS16_INSN_READ_Y   0x00000100

Definition at line 988 of file mips.h.

#define MIPS16_INSN_READ_Z   0x00000200

Definition at line 990 of file mips.h.

#define MIPS16_INSN_WRITE_31   0x00000020

Definition at line 982 of file mips.h.

#define MIPS16_INSN_WRITE_GPR_Y   0x00000040

Definition at line 984 of file mips.h.

#define MIPS16_INSN_WRITE_SP   0x00000010

Definition at line 980 of file mips.h.

#define MIPS16_INSN_WRITE_T   0x00000008

Definition at line 978 of file mips.h.

#define MIPS16_INSN_WRITE_X   0x00000001

Definition at line 972 of file mips.h.

#define MIPS16_INSN_WRITE_Y   0x00000002

Definition at line 974 of file mips.h.

#define MIPS16_INSN_WRITE_Z   0x00000004

Definition at line 976 of file mips.h.

#define MIPS16OP_EXTRACT_REG32R (   i)    ((((i) >> 5) & 7) | ((i) & 0x18))

Definition at line 906 of file mips.h.

#define MIPS16OP_MASK_IMM11   0x7ff

Definition at line 888 of file mips.h.

#define MIPS16OP_MASK_IMM4   0xf

Definition at line 900 of file mips.h.

#define MIPS16OP_MASK_IMM5   0x1f

Definition at line 896 of file mips.h.

#define MIPS16OP_MASK_IMM6   0x3f

Definition at line 909 of file mips.h.

#define MIPS16OP_MASK_IMM8   0xff

Definition at line 892 of file mips.h.

#define MIPS16OP_MASK_MOVE32Z   0x7

Definition at line 907 of file mips.h.

#define MIPS16OP_MASK_OP   0x1f

Definition at line 886 of file mips.h.

#define MIPS16OP_MASK_REG32R   0x1f

Definition at line 904 of file mips.h.

#define MIPS16OP_MASK_REGR32   0x1f

Definition at line 902 of file mips.h.

#define MIPS16OP_MASK_RX   0x7

Definition at line 890 of file mips.h.

#define MIPS16OP_MASK_RY   0x7

Definition at line 894 of file mips.h.

#define MIPS16OP_MASK_RZ   0x7

Definition at line 898 of file mips.h.

#define MIPS16OP_SH_IMM11   0

Definition at line 889 of file mips.h.

#define MIPS16OP_SH_IMM4   0

Definition at line 901 of file mips.h.

#define MIPS16OP_SH_IMM5   0

Definition at line 897 of file mips.h.

#define MIPS16OP_SH_IMM6   5

Definition at line 910 of file mips.h.

#define MIPS16OP_SH_IMM8   0

Definition at line 893 of file mips.h.

#define MIPS16OP_SH_MOVE32Z   0

Definition at line 908 of file mips.h.

#define MIPS16OP_SH_OP   11

Definition at line 887 of file mips.h.

#define MIPS16OP_SH_REG32R   3

Definition at line 905 of file mips.h.

#define MIPS16OP_SH_REGR32   0

Definition at line 903 of file mips.h.

#define MIPS16OP_SH_RX   8

Definition at line 891 of file mips.h.

#define MIPS16OP_SH_RY   5

Definition at line 895 of file mips.h.

#define MIPS16OP_SH_RZ   2

Definition at line 899 of file mips.h.

Definition at line 850 of file mips.h.

#define OP_MASK_ALN   0x7

Definition at line 138 of file mips.h.

#define OP_MASK_BCC   0x7

Definition at line 69 of file mips.h.

#define OP_MASK_BP   0x3

Definition at line 172 of file mips.h.

#define OP_MASK_CACHE   0x1f

Definition at line 79 of file mips.h.

#define OP_MASK_CC   0x7

Definition at line 109 of file mips.h.

#define OP_MASK_CCC   0x7

Definition at line 87 of file mips.h.

#define OP_MASK_CODE   0x3ff

Definition at line 71 of file mips.h.

#define OP_MASK_CODE19   0x7ffff

Definition at line 136 of file mips.h.

#define OP_MASK_CODE2   0x3ff

Definition at line 73 of file mips.h.

#define OP_MASK_CODE20   0xfffff /* 20 bit syscall/breakpoint code. */

Definition at line 89 of file mips.h.

#define OP_MASK_COP1CMP   0x3

Definition at line 115 of file mips.h.

#define OP_MASK_COP1NORM   0x1 /* a single bit. */

Definition at line 111 of file mips.h.

#define OP_MASK_COP1SCLR   0x4

Definition at line 114 of file mips.h.

#define OP_MASK_COP1SPEC   0xf

Definition at line 113 of file mips.h.

#define OP_MASK_COPZ   0x1ffffff

Definition at line 97 of file mips.h.

#define OP_MASK_DELTA   0xffff

Definition at line 101 of file mips.h.

#define OP_MASK_DSPACC   0x3

Definition at line 152 of file mips.h.

#define OP_MASK_DSPACC_S   0x3

Definition at line 154 of file mips.h.

#define OP_MASK_DSPSFT   0x3f

Definition at line 156 of file mips.h.

#define OP_MASK_DSPSFT_7   0x7f

Definition at line 158 of file mips.h.

#define OP_MASK_EXTMSBD   0x1f /* "ext" MSBD. */

Definition at line 147 of file mips.h.

#define OP_MASK_FD   0x1f

Definition at line 93 of file mips.h.

#define OP_MASK_FMT   0x1f

Definition at line 67 of file mips.h.

#define OP_MASK_FORMAT   0x7

Definition at line 118 of file mips.h.

#define OP_MASK_FR   0x1f

Definition at line 65 of file mips.h.

#define OP_MASK_FS   0x1f

Definition at line 83 of file mips.h.

#define OP_MASK_FT   0x1f

Definition at line 77 of file mips.h.

#define OP_MASK_FUNCT   0x3f

Definition at line 103 of file mips.h.

#define OP_MASK_GE   0x01

Definition at line 122 of file mips.h.

#define OP_MASK_HINT   0x1f

Definition at line 126 of file mips.h.

#define OP_MASK_IMM10   0x3ff

Definition at line 166 of file mips.h.

#define OP_MASK_IMM8   0xff

Definition at line 164 of file mips.h.

#define OP_MASK_IMMEDIATE   0xffff

Definition at line 99 of file mips.h.

#define OP_MASK_INSMSB   0x1f /* "ins" MSB. */

Definition at line 145 of file mips.h.

#define OP_MASK_MMI   0x3f

Definition at line 128 of file mips.h.

#define OP_MASK_MMISUB   0x1f

Definition at line 130 of file mips.h.

#define OP_MASK_MT_H   0x1

Definition at line 178 of file mips.h.

#define OP_MASK_MT_U   0x1

Definition at line 176 of file mips.h.

#define OP_MASK_MTACC_D   0x3

Definition at line 182 of file mips.h.

#define OP_MASK_MTACC_T   0x3

Definition at line 180 of file mips.h.

#define OP_MASK_OP   0x3f

Definition at line 61 of file mips.h.

#define OP_MASK_PERFREG   0x1f /* Performance monitoring. */

Definition at line 131 of file mips.h.

#define OP_MASK_PREFX   0x1f

Definition at line 85 of file mips.h.

#define OP_MASK_RD   0x1f

Definition at line 81 of file mips.h.

#define OP_MASK_RDDSP   0x3f

Definition at line 170 of file mips.h.

#define OP_MASK_RS   0x1f

Definition at line 63 of file mips.h.

#define OP_MASK_RT   0x1f

Definition at line 75 of file mips.h.

#define OP_MASK_SA3   0x7

Definition at line 160 of file mips.h.

#define OP_MASK_SA4   0xf

Definition at line 162 of file mips.h.

#define OP_MASK_SEL   0x7 /* The sel field of mfcZ and mtcZ. */

Definition at line 134 of file mips.h.

#define OP_MASK_SHAMT   0x1f

Definition at line 91 of file mips.h.

#define OP_MASK_SPEC   0x3f

Definition at line 105 of file mips.h.

#define OP_MASK_TARGET   0x3ffffff

Definition at line 95 of file mips.h.

#define OP_MASK_TRUE   0x1

Definition at line 120 of file mips.h.

#define OP_MASK_UDI1   0x1f

Definition at line 209 of file mips.h.

#define OP_MASK_UDI2   0x3ff

Definition at line 211 of file mips.h.

#define OP_MASK_UDI3   0x7fff

Definition at line 213 of file mips.h.

#define OP_MASK_UDI4   0xfffff

Definition at line 215 of file mips.h.

#define OP_MASK_UNSIGNED   0x1

Definition at line 124 of file mips.h.

#define OP_MASK_VECALIGN   0x7 /* Vector byte-align (alni.ob) op. */

Definition at line 143 of file mips.h.

#define OP_MASK_VECBYTE
Value:
0x7    /* Selector field is really 4 bits,
                                      but 0x8-0xf don't select bytes.  */

Definition at line 141 of file mips.h.

#define OP_MASK_VSEL   0x1f

Definition at line 140 of file mips.h.

#define OP_MASK_WRDSP   0x3f

Definition at line 168 of file mips.h.

#define OP_OP_COP0   0x10

Definition at line 184 of file mips.h.

#define OP_OP_COP1   0x11

Definition at line 185 of file mips.h.

#define OP_OP_COP2   0x12

Definition at line 186 of file mips.h.

#define OP_OP_COP3   0x13

Definition at line 187 of file mips.h.

#define OP_OP_LDC1   0x35

Definition at line 191 of file mips.h.

#define OP_OP_LDC2   0x36

Definition at line 192 of file mips.h.

#define OP_OP_LDC3   0x37 /* a.k.a. ld */

Definition at line 193 of file mips.h.

#define OP_OP_LWC1   0x31

Definition at line 188 of file mips.h.

#define OP_OP_LWC2   0x32

Definition at line 189 of file mips.h.

#define OP_OP_LWC3   0x33 /* a.k.a. pref */

Definition at line 190 of file mips.h.

#define OP_OP_SDC1   0x3d

Definition at line 197 of file mips.h.

#define OP_OP_SDC2   0x3e

Definition at line 198 of file mips.h.

#define OP_OP_SDC3   0x3f /* a.k.a. sd */

Definition at line 199 of file mips.h.

#define OP_OP_SWC1   0x39

Definition at line 194 of file mips.h.

#define OP_OP_SWC2   0x3a

Definition at line 195 of file mips.h.

#define OP_OP_SWC3   0x3b

Definition at line 196 of file mips.h.

#define OP_SH_ALN   21

Definition at line 137 of file mips.h.

#define OP_SH_BCC   18

Definition at line 70 of file mips.h.

#define OP_SH_BP   11

Definition at line 171 of file mips.h.

#define OP_SH_CACHE   16

Definition at line 80 of file mips.h.

#define OP_SH_CCC   8

Definition at line 88 of file mips.h.

#define OP_SH_CODE   16

Definition at line 72 of file mips.h.

#define OP_SH_CODE19   6 /* 19 bit wait code. */

Definition at line 135 of file mips.h.

#define OP_SH_CODE2   6

Definition at line 74 of file mips.h.

#define OP_SH_CODE20   6

Definition at line 90 of file mips.h.

#define OP_SH_COP1CMP   4

Definition at line 116 of file mips.h.

#define OP_SH_COP1NORM   25 /* Normal COP1 encoding. */

Definition at line 110 of file mips.h.

#define OP_SH_COP1SPEC   21 /* COP1 encodings. */

Definition at line 112 of file mips.h.

#define OP_SH_COPZ   0

Definition at line 98 of file mips.h.

#define OP_SH_DELTA   0

Definition at line 102 of file mips.h.

#define OP_SH_DSPACC   11

Definition at line 151 of file mips.h.

#define OP_SH_DSPACC_S   21

Definition at line 153 of file mips.h.

#define OP_SH_DSPSFT   20

Definition at line 155 of file mips.h.

#define OP_SH_DSPSFT_7   19

Definition at line 157 of file mips.h.

#define OP_SH_EXTMSBD   11

Definition at line 148 of file mips.h.

#define OP_SH_FD   6

Definition at line 94 of file mips.h.

#define OP_SH_FMT   21

Definition at line 68 of file mips.h.

#define OP_SH_FORMAT   21 /* FP short format field. */

Definition at line 117 of file mips.h.

#define OP_SH_FR   21

Definition at line 66 of file mips.h.

#define OP_SH_FS   11

Definition at line 84 of file mips.h.

#define OP_SH_FT   16

Definition at line 78 of file mips.h.

#define OP_SH_FUNCT   0

Definition at line 104 of file mips.h.

#define OP_SH_GE   17

Definition at line 121 of file mips.h.

#define OP_SH_HICC   18 /* FP condition code. */

Definition at line 108 of file mips.h.

#define OP_SH_HINT   16

Definition at line 125 of file mips.h.

#define OP_SH_IMM10   16

Definition at line 165 of file mips.h.

#define OP_SH_IMM8   16

Definition at line 163 of file mips.h.

#define OP_SH_IMMEDIATE   0

Definition at line 100 of file mips.h.

#define OP_SH_INSMSB   11

Definition at line 146 of file mips.h.

#define OP_SH_LOCC   8 /* FP condition code. */

Definition at line 107 of file mips.h.

#define OP_SH_MMI   0 /* Multimedia (parallel) op. */

Definition at line 127 of file mips.h.

#define OP_SH_MMISUB   6

Definition at line 129 of file mips.h.

#define OP_SH_MT_H   4

Definition at line 177 of file mips.h.

#define OP_SH_MT_U   5

Definition at line 175 of file mips.h.

#define OP_SH_MTACC_D   13

Definition at line 181 of file mips.h.

#define OP_SH_MTACC_T   18

Definition at line 179 of file mips.h.

#define OP_SH_OP   26

Definition at line 62 of file mips.h.

#define OP_SH_PERFREG   1

Definition at line 132 of file mips.h.

#define OP_SH_PREFX   11

Definition at line 86 of file mips.h.

#define OP_SH_RD   11

Definition at line 82 of file mips.h.

#define OP_SH_RDDSP   16

Definition at line 169 of file mips.h.

#define OP_SH_RS   21

Definition at line 64 of file mips.h.

#define OP_SH_RT   16

Definition at line 76 of file mips.h.

#define OP_SH_SA3   21

Definition at line 159 of file mips.h.

#define OP_SH_SA4   21

Definition at line 161 of file mips.h.

#define OP_SH_SEL   0 /* Coprocessor select field. */

Definition at line 133 of file mips.h.

#define OP_SH_SHAMT   6

Definition at line 92 of file mips.h.

#define OP_SH_SPEC   0

Definition at line 106 of file mips.h.

#define OP_SH_TARGET   0

Definition at line 96 of file mips.h.

#define OP_SH_TRUE   16

Definition at line 119 of file mips.h.

#define OP_SH_UDI1   6

Definition at line 208 of file mips.h.

#define OP_SH_UDI2   6

Definition at line 210 of file mips.h.

#define OP_SH_UDI3   6

Definition at line 212 of file mips.h.

#define OP_SH_UDI4   6

Definition at line 214 of file mips.h.

#define OP_SH_UNSIGNED   16

Definition at line 123 of file mips.h.

#define OP_SH_VECALIGN   21

Definition at line 144 of file mips.h.

#define OP_SH_VECBYTE   22

Definition at line 142 of file mips.h.

#define OP_SH_VSEL   21

Definition at line 139 of file mips.h.

#define OP_SH_WRDSP   11

Definition at line 167 of file mips.h.

#define OPCODE_IS_MEMBER (   insn,
  isa,
  cpu 
)
Value:
(((insn)->membership & isa) != 0                               \
     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)   \
     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)  \
     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)  \
     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)   \
     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)  \
     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)   \
     || ((cpu == CPU_R10000 || cpu == CPU_R12000)                     \
        && ((insn)->membership & INSN_10000) != 0)                    \
     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)      \
     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)   \
     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)  \
     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)  \
     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)  \
     || 0)    /* Please keep this term for easier source merging.  */

Definition at line 584 of file mips.h.


Enumeration Type Documentation

anonymous enum
Enumerator:
M_ABS 
M_ADD_I 
M_ADDU_I 
M_AND_I 
M_BALIGN 
M_BEQ 
M_BEQ_I 
M_BEQL_I 
M_BGE 
M_BGEL 
M_BGE_I 
M_BGEL_I 
M_BGEU 
M_BGEUL 
M_BGEU_I 
M_BGEUL_I 
M_BGT 
M_BGTL 
M_BGT_I 
M_BGTL_I 
M_BGTU 
M_BGTUL 
M_BGTU_I 
M_BGTUL_I 
M_BLE 
M_BLEL 
M_BLE_I 
M_BLEL_I 
M_BLEU 
M_BLEUL 
M_BLEU_I 
M_BLEUL_I 
M_BLT 
M_BLTL 
M_BLT_I 
M_BLTL_I 
M_BLTU 
M_BLTUL 
M_BLTU_I 
M_BLTUL_I 
M_BNE 
M_BNE_I 
M_BNEL_I 
M_CACHE_AB 
M_DABS 
M_DADD_I 
M_DADDU_I 
M_DDIV_3 
M_DDIV_3I 
M_DDIVU_3 
M_DDIVU_3I 
M_DEXT 
M_DINS 
M_DIV_3 
M_DIV_3I 
M_DIVU_3 
M_DIVU_3I 
M_DLA_AB 
M_DLCA_AB 
M_DLI 
M_DMUL 
M_DMUL_I 
M_DMULO 
M_DMULO_I 
M_DMULOU 
M_DMULOU_I 
M_DREM_3 
M_DREM_3I 
M_DREMU_3 
M_DREMU_3I 
M_DSUB_I 
M_DSUBU_I 
M_DSUBU_I_2 
M_J_A 
M_JAL_1 
M_JAL_2 
M_JAL_A 
M_L_DOB 
M_L_DAB 
M_LA_AB 
M_LB_A 
M_LB_AB 
M_LBU_A 
M_LBU_AB 
M_LCA_AB 
M_LD_A 
M_LD_OB 
M_LD_AB 
M_LDC1_AB 
M_LDC2_AB 
M_LDC3_AB 
M_LDL_AB 
M_LDR_AB 
M_LH_A 
M_LH_AB 
M_LHU_A 
M_LHU_AB 
M_LI 
M_LI_D 
M_LI_DD 
M_LI_S 
M_LI_SS 
M_LL_AB 
M_LLD_AB 
M_LS_A 
M_LW_A 
M_LW_AB 
M_LWC0_A 
M_LWC0_AB 
M_LWC1_A 
M_LWC1_AB 
M_LWC2_A 
M_LWC2_AB 
M_LWC3_A 
M_LWC3_AB 
M_LWL_A 
M_LWL_AB 
M_LWR_A 
M_LWR_AB 
M_LWU_AB 
M_MOVE 
M_MUL 
M_MUL_I 
M_MULO 
M_MULO_I 
M_MULOU 
M_MULOU_I 
M_NOR_I 
M_OR_I 
M_REM_3 
M_REM_3I 
M_REMU_3 
M_REMU_3I 
M_DROL 
M_ROL 
M_DROL_I 
M_ROL_I 
M_DROR 
M_ROR 
M_DROR_I 
M_ROR_I 
M_S_DA 
M_S_DOB 
M_S_DAB 
M_S_S 
M_SC_AB 
M_SCD_AB 
M_SD_A 
M_SD_OB 
M_SD_AB 
M_SDC1_AB 
M_SDC2_AB 
M_SDC3_AB 
M_SDL_AB 
M_SDR_AB 
M_SEQ 
M_SEQ_I 
M_SGE 
M_SGE_I 
M_SGEU 
M_SGEU_I 
M_SGT 
M_SGT_I 
M_SGTU 
M_SGTU_I 
M_SLE 
M_SLE_I 
M_SLEU 
M_SLEU_I 
M_SLT_I 
M_SLTU_I 
M_SNE 
M_SNE_I 
M_SB_A 
M_SB_AB 
M_SH_A 
M_SH_AB 
M_SW_A 
M_SW_AB 
M_SWC0_A 
M_SWC0_AB 
M_SWC1_A 
M_SWC1_AB 
M_SWC2_A 
M_SWC2_AB 
M_SWC3_A 
M_SWC3_AB 
M_SWL_A 
M_SWL_AB 
M_SWR_A 
M_SWR_AB 
M_SUB_I 
M_SUBU_I 
M_SUBU_I_2 
M_TEQ_I 
M_TGE_I 
M_TGEU_I 
M_TLT_I 
M_TLTU_I 
M_TNE_I 
M_TRUNCWD 
M_TRUNCWS 
M_ULD 
M_ULD_A 
M_ULH 
M_ULH_A 
M_ULHU 
M_ULHU_A 
M_ULW 
M_ULW_A 
M_USH 
M_USH_A 
M_USW 
M_USW_A 
M_USD 
M_USD_A 
M_XOR_I 
M_COP0 
M_COP1 
M_COP2 
M_COP3 
M_NUM_MACROS 

Definition at line 609 of file mips.h.

{
  M_ABS,
  M_ADD_I,
  M_ADDU_I,
  M_AND_I,
  M_BALIGN,
  M_BEQ,
  M_BEQ_I,
  M_BEQL_I,
  M_BGE,
  M_BGEL,
  M_BGE_I,
  M_BGEL_I,
  M_BGEU,
  M_BGEUL,
  M_BGEU_I,
  M_BGEUL_I,
  M_BGT,
  M_BGTL,
  M_BGT_I,
  M_BGTL_I,
  M_BGTU,
  M_BGTUL,
  M_BGTU_I,
  M_BGTUL_I,
  M_BLE,
  M_BLEL,
  M_BLE_I,
  M_BLEL_I,
  M_BLEU,
  M_BLEUL,
  M_BLEU_I,
  M_BLEUL_I,
  M_BLT,
  M_BLTL,
  M_BLT_I,
  M_BLTL_I,
  M_BLTU,
  M_BLTUL,
  M_BLTU_I,
  M_BLTUL_I,
  M_BNE,
  M_BNE_I,
  M_BNEL_I,
  M_CACHE_AB,
  M_DABS,
  M_DADD_I,
  M_DADDU_I,
  M_DDIV_3,
  M_DDIV_3I,
  M_DDIVU_3,
  M_DDIVU_3I,
  M_DEXT,
  M_DINS,
  M_DIV_3,
  M_DIV_3I,
  M_DIVU_3,
  M_DIVU_3I,
  M_DLA_AB,
  M_DLCA_AB,
  M_DLI,
  M_DMUL,
  M_DMUL_I,
  M_DMULO,
  M_DMULO_I,
  M_DMULOU,
  M_DMULOU_I,
  M_DREM_3,
  M_DREM_3I,
  M_DREMU_3,
  M_DREMU_3I,
  M_DSUB_I,
  M_DSUBU_I,
  M_DSUBU_I_2,
  M_J_A,
  M_JAL_1,
  M_JAL_2,
  M_JAL_A,
  M_L_DOB,
  M_L_DAB,
  M_LA_AB,
  M_LB_A,
  M_LB_AB,
  M_LBU_A,
  M_LBU_AB,
  M_LCA_AB,
  M_LD_A,
  M_LD_OB,
  M_LD_AB,
  M_LDC1_AB,
  M_LDC2_AB,
  M_LDC3_AB,
  M_LDL_AB,
  M_LDR_AB,
  M_LH_A,
  M_LH_AB,
  M_LHU_A,
  M_LHU_AB,
  M_LI,
  M_LI_D,
  M_LI_DD,
  M_LI_S,
  M_LI_SS,
  M_LL_AB,
  M_LLD_AB,
  M_LS_A,
  M_LW_A,
  M_LW_AB,
  M_LWC0_A,
  M_LWC0_AB,
  M_LWC1_A,
  M_LWC1_AB,
  M_LWC2_A,
  M_LWC2_AB,
  M_LWC3_A,
  M_LWC3_AB,
  M_LWL_A,
  M_LWL_AB,
  M_LWR_A,
  M_LWR_AB,
  M_LWU_AB,
  M_MOVE,
  M_MUL,
  M_MUL_I,
  M_MULO,
  M_MULO_I,
  M_MULOU,
  M_MULOU_I,
  M_NOR_I,
  M_OR_I,
  M_REM_3,
  M_REM_3I,
  M_REMU_3,
  M_REMU_3I,
  M_DROL,
  M_ROL,
  M_DROL_I,
  M_ROL_I,
  M_DROR,
  M_ROR,
  M_DROR_I,
  M_ROR_I,
  M_S_DA,
  M_S_DOB,
  M_S_DAB,
  M_S_S,
  M_SC_AB,
  M_SCD_AB,
  M_SD_A,
  M_SD_OB,
  M_SD_AB,
  M_SDC1_AB,
  M_SDC2_AB,
  M_SDC3_AB,
  M_SDL_AB,
  M_SDR_AB,
  M_SEQ,
  M_SEQ_I,
  M_SGE,
  M_SGE_I,
  M_SGEU,
  M_SGEU_I,
  M_SGT,
  M_SGT_I,
  M_SGTU,
  M_SGTU_I,
  M_SLE,
  M_SLE_I,
  M_SLEU,
  M_SLEU_I,
  M_SLT_I,
  M_SLTU_I,
  M_SNE,
  M_SNE_I,
  M_SB_A,
  M_SB_AB,
  M_SH_A,
  M_SH_AB,
  M_SW_A,
  M_SW_AB,
  M_SWC0_A,
  M_SWC0_AB,
  M_SWC1_A,
  M_SWC1_AB,
  M_SWC2_A,
  M_SWC2_AB,
  M_SWC3_A,
  M_SWC3_AB,
  M_SWL_A,
  M_SWL_AB,
  M_SWR_A,
  M_SWR_AB,
  M_SUB_I,
  M_SUBU_I,
  M_SUBU_I_2,
  M_TEQ_I,
  M_TGE_I,
  M_TGEU_I,
  M_TLT_I,
  M_TLTU_I,
  M_TNE_I,
  M_TRUNCWD,
  M_TRUNCWS,
  M_ULD,
  M_ULD_A,
  M_ULH,
  M_ULH_A,
  M_ULHU,
  M_ULHU_A,
  M_ULW,
  M_ULW_A,
  M_USH,
  M_USH_A,
  M_USW,
  M_USW_A,
  M_USD,
  M_USD_A,
  M_XOR_I,
  M_COP0,
  M_COP1,
  M_COP2,
  M_COP3,
  M_NUM_MACROS

Variable Documentation

Definition at line 243 of file mips16-opc.c.

Definition at line 1698 of file mips-opc.c.

Definition at line 1704 of file mips-opc.c.

Definition at line 1702 of file mips-opc.c.