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cell-binutils  2.17cvs20070401
maxq.h
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00001 /* maxq.h -- Header file for MAXQ opcode table.
00002 
00003    Copyright (C) 2004 Free Software Foundation, Inc.
00004 
00005    This file is part of GDB, GAS, and the GNU binutils.
00006 
00007    Written by Vineet Sharma(vineets@noida.hcltech.com)
00008    Inderpreet Singh (inderpreetb@noida.hcltech.com)
00009 
00010    GDB, GAS, and the GNU binutils are free software; you can redistribute
00011    them and/or modify them under the terms of the GNU General Public License
00012    as published by the Free Software Foundation; either version 2, or (at
00013    your option) any later version.
00014 
00015    GDB, GAS, and the GNU binutils are distributed in the hope that they will
00016    be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
00017    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
00018    Public License for more details.
00019 
00020    You should have received a copy of the GNU General Public License along
00021    with this file; see the file COPYING.  If not, write to the Free Software
00022    Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00023 
00024 #ifndef _MAXQ20_H_
00025 #define  _MAXQ20_H_
00026 
00027 /* This file contains the opcode table for the MAXQ10/20 processor. The table
00028    has been designed on the lines of the SH processor with the following 
00029    fields:
00030    (1) Instruction Name
00031    (2) Instruction arguments description
00032    (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4
00033        |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8)  
00034    (4) Architecture supported
00035 
00036    The Register table is also defined. It contains the following fields
00037    (1) Register name
00038    (2) Module Number
00039    (3) Module Index
00040    (4) Opcode
00041    (5) Regtype
00042 
00043    The Memory access table is defined containing the various opcodes for 
00044    memory access containing the following fields
00045    (1) Memory access Operand Name
00046    (2) Memory access Operand opcode.  */
00047 
00048 # define MAXQ10 0x0001
00049 # define MAXQ20 0x0002
00050 # define MAX    (MAXQ10 | MAXQ20)
00051 
00052 /* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte:
00053    NOP_DST 2nd byte: NOP_SRC.  */
00054 # define NOP_FMT  1
00055 # define NOP_SRC  0x3A
00056 # define NOP_DST  0x5A
00057 
00058 typedef enum
00059 {
00060   ZEROBIT = 0x1,            /* A zero followed by 3 bits.  */
00061   ONEBIT = 0x2,                    /* A one followed by 3 bits.  */
00062   REG = 0x4,                /* Register.  */
00063   MEM = 0x8,                /* Memory access.  */
00064   IMM = 0x10,               /* Immediate value.  */
00065   DISP = 0x20,                     /* Displacement value.  */
00066   BIT = 0x40,               /* Bit value.  */
00067   FMT = 0x80,               /* The format bit.  */
00068   IMMBIT = 0x100,           /* An immediate bit.  */
00069   FLAG = 0x200,                    /* A Flag.  */
00070   DATA = 0x400,                    /* Symbol in the data section.  */
00071   BIT_BUCKET = 0x800,              /* FOr BIT BUCKET.  */
00072 }
00073 UNKNOWN_OP;
00074 
00075 typedef enum
00076 {
00077   NO_ARG = 0,
00078   A_IMM = 0x01,                    /* An 8 bit immediate value.  */
00079   A_REG = 0x2,                     /* An 8 bit source register.  */
00080   A_MEM = 0x4,                     /* A 7 bit destination register.  */
00081   FLAG_C = 0x8,                    /* Carry Flag.  */
00082   FLAG_NC = 0x10,           /* No Carry (~C) flag.  */
00083   FLAG_Z = 0x20,            /* Zero Flag.  */
00084   FLAG_NZ = 0x40,           /* Not Zero Flag.  */
00085   FLAG_S = 0x80,            /* Sign Flag.  */
00086   FLAG_E = 0x100,           /* Equals Flag.  */
00087   FLAG_NE = 0x200,          /* Not Equal Flag.  */
00088   ACC_BIT = 0x400,          /* One of the 16 accumulator bits of the form Acc.<b>.  */
00089   DST_BIT = 0x800,          /* One of the 8 bits of the specified SRC.  */
00090   SRC_BIT = 0x1000,         /* One of the 8 bits of the specified source register.  */
00091   A_BIT_0 = 0x2000,         /* #0.  */
00092   A_BIT_1 = 0x4000,         /* #1.  */
00093   A_DISP = 0x8000,          /* Displacement Operand.  */
00094   A_DATA = 0x10000,         /* Data in the data section.  */
00095   A_BIT_BUCKET = 0x200000,
00096 }
00097 MAX_ARG_TYPE;
00098 
00099 typedef struct
00100 {
00101   char * name;                     /* Name of the instruction.  */
00102   unsigned int op_number;   /* Operand Number or the number of operands.  */
00103   MAX_ARG_TYPE arg[2];             /* Types of operands.  */
00104   int format;               /* Format bit.  */
00105   int dst[2];               /* Destination in the move instruction.  */
00106   int src[2];               /* Source in the move instruction.  */
00107   int arch;                 /* The Machine architecture.  */
00108   unsigned int instr_id;    /* Added for decode and dissassembly.  */
00109 }
00110 MAXQ20_OPCODE_INFO;
00111 
00112 /* Structure for holding opcodes of the same name.  */
00113 typedef struct
00114 {
00115   const MAXQ20_OPCODE_INFO *start; /* The first opcode.  */
00116   const MAXQ20_OPCODE_INFO *end;   /* The last opcode.  */
00117 }
00118 MAXQ20_OPCODES;
00119 
00120 /* The entry into the hash table will be of the type MAXX_OPCODES.  */
00121 
00122 /* The definition of the table.  */
00123 const MAXQ20_OPCODE_INFO op_table[] =
00124 {
00125   /* LOGICAL OPERATIONS */
00126   /* AND src : f001 1010 ssss ssss */
00127   {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0},
00128    {REG | MEM | IMM | DISP, 0}, MAX, 0x11},
00129   /* AND Acc.<b> : 1111 1010 bbbb 1010 */
00130   {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39},
00131   /* OR src : f010 1010 ssss ssss */
00132   {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0},
00133    {REG | MEM | IMM | DISP, 0}, MAX, 0x12},
00134   /* OR Acc.<b> : 1010 1010 bbbb 1010 */
00135   {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A},
00136   /* XOR src : f011 1010 ssss ssss */
00137   {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0},
00138    {REG | MEM | IMM | DISP, 0}, MAX, 0x13},
00139   /* XOR Acc.<b> : 1011 1010 bbbb 1010 */
00140   {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B},
00141   /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */
00142   /* CPL : 1000 1010 0001 1010 */
00143   {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21},
00144   /* CPL C : 1101 1010 0010 1010 */
00145   {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D},
00146   /* NEG : 1000 1010 1001 1010 */
00147   {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29},
00148   /* SLA : 1000 1010 0010 1010 */
00149   {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22},
00150   /* SLA2: 1000 1010 0011 1010 */
00151   {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23},
00152   /* SLA4: 1000 1010 0110 1010 */
00153   {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26},
00154   /* RL : 1000 1010 0100 1010 */
00155   {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24},
00156   /* RLC : 1000 1010 0101 1010 */
00157   {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25},
00158   /* SRA : 1000 1010 1111 1010 */
00159   {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F},
00160   /* SRA2: 1000 1010 1110 1010 */
00161   {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E},
00162   /* SRA4: 1000 1010 1011 1010 */
00163   {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B},
00164   /* SR : 1000 1010 1010 1010 */
00165   {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A},
00166   /* RR : 1000 1010 1100 1010 */
00167   {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C},
00168   /* RRC : 1000 1010 1101 1010 */
00169   {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D},
00170   /* MATH OPERATIONS */
00171   /* ADD src : f100 1010 ssss ssss */
00172   {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0},
00173    {IMM | REG | MEM | DISP, 0}, MAX, 0x14},
00174   /* ADDC src : f110 1010 ssss ssss */
00175   {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0},
00176    {IMM | REG | MEM | DISP, 0}, MAX, 0x16},
00177   /* SUB src : f101 1010 ssss ssss */
00178   {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0},
00179    {IMM | REG | MEM | DISP, 0}, MAX, 0x15},
00180   /* SUBB src : f111 1010 ssss ssss */
00181   {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0},
00182    {IMM | REG | MEM | DISP, 0}, MAX, 0x17},
00183   /* BRANCHING OPERATIONS */
00184 
00185   /* DJNZ LC[0] src: f100 1101 ssss ssss */
00186   {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0},
00187    {IMM | REG | MEM | DISP, 0}, MAX, 0xA4},
00188   /* DJNZ LC[1] src: f101 1101 ssss ssss */
00189   {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0},
00190    {IMM | REG | MEM | DISP, 0}, MAX, 0xA5},
00191   /* CALL src : f011 1101 ssss ssss */
00192   {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0},
00193    {IMM | REG | MEM | DISP, 0}, MAX, 0xA3},
00194   /* JUMP src : f000 1100 ssss ssss */
00195   {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0},
00196    {IMM | REG | MEM | DISP, 0}, MAX, 0x50},
00197   /* JUMP C,src : f010 1100 ssss ssss */
00198   {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0},
00199    {IMM | REG | MEM | DISP, 0}, MAX, 0x52},
00200   /* JUMP NC,src: f110 1100 ssss ssss */
00201   {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0},
00202    {IMM | REG | MEM | DISP, 0}, MAX, 0x56},
00203   /* JUMP Z,src : f001 1100 ssss ssss */
00204   {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0},
00205    {IMM | REG | MEM | DISP, 0}, MAX, 0x51},
00206   /* JUMP NZ,src: f101 1100 ssss ssss */
00207   {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0},
00208    {IMM | REG | MEM | DISP, 0}, MAX, 0x55},
00209   /* JUMP E,src : 0011 1100 ssss ssss */
00210   {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53},
00211   /* JUMP NE,src: 0111 1100 ssss ssss */
00212   {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57},
00213   /* JUMP S,src : f100 1100 ssss ssss */
00214   {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0},
00215    {IMM | REG | MEM | DISP, 0}, MAX, 0x54},
00216   /* RET : 1000 1100 0000 1101 */
00217   {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68},
00218   /* RET C : 1010 1100 0000 1101 */
00219   {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A},
00220   /* RET NC : 1110 1100 0000 1101 */
00221   {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E},
00222   /* RET Z : 1001 1100 0000 1101 */
00223   {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69},
00224   /* RET NZ : 1101 1100 0000 1101 */
00225   {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D},
00226   /* RET S : 1100 1100 0000 1101 */
00227   {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C},
00228   /* RETI : 1000 1100 1000 1101 */
00229   {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78},
00230   /* ADDED ACCORDING TO NEW SPECIFICATION */
00231 
00232   /* RETI C : 1010 1100 1000 1101 */
00233   {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A},
00234   /* RETI NC : 1110 1100 1000 1101 */
00235   {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E},
00236   /* RETI Z : 1001 1100 1000 1101 */
00237   {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79},
00238   /* RETI NZ : 1101 1100 1000 1101 */
00239   {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D},
00240   /* RETI S : 1100 1100 1000 1101 */
00241   {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C},
00242   /* MISCELLANEOUS INSTRUCTIONS */
00243   /* CMP src : f111 1000 ssss ssss */
00244   {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0},
00245    {REG | MEM | IMM | DISP, 0}, MAX, 0xD7},
00246   /* DATA TRANSFER OPERATIONS */
00247   /* XCH : 1000 1010 1000 1010 */
00248   {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28},
00249   /* XCHN : 1000 1010 0111 1010 */
00250   {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27},
00251   /* PUSH src : f000 1101 ssss ssss */
00252   {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0},
00253    {IMM | REG | MEM | DISP, 0}, MAX, 0xA0},
00254   /* POP dst : 1ddd dddd 0000 1101 */
00255   {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0},
00256   /* Added according to new spec */
00257   /* POPI dst : 1ddd dddd 1000 1101 */
00258   {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0},
00259   /* MOVE dst,src: fddd dddd ssss ssss */
00260   {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT,
00261    {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80},
00262   /* BIT OPERATIONS */
00263   /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */
00264   {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E},
00265   /* MOVE C,#0 : 1101 1010 0000 1010 */
00266   {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D},
00267   /* MOVE C,#1 : 1101 1010 0001 1010 */
00268   {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D},
00269   /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */
00270   {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F},
00271   /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */
00272   {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40},
00273   /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */
00274   {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41},
00275   /* MOVE C,src.<b> : fbbb 0111 ssss ssss */
00276   {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97},
00277   /* NOP : 1101 1010 0011 1010 */
00278   {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D},
00279   {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00}
00280 };
00281 
00282 /* All the modules.  */
00283 
00284 #define       MOD0 0x0
00285 #define MOD1 0x1
00286 #define MOD2 0x2
00287 #define MOD3 0x3
00288 #define MOD4 0x4
00289 #define MOD5 0x5
00290 #define MOD6 0x6
00291 #define MOD7 0x7
00292 #define MOD8 0x8
00293 #define MOD9 0x9
00294 #define MODA 0xa
00295 #define MODB 0xb
00296 #define MODC 0xc
00297 #define MODD 0xd
00298 #define MODE 0xe
00299 #define MODF 0xf
00300 
00301 /* Added according to new specification.  */
00302 #define MOD10 0x10
00303 #define MOD11 0x11
00304 #define MOD12 0x12
00305 #define MOD13 0x13
00306 #define MOD14 0x14
00307 #define MOD15 0x15
00308 #define MOD16 0x16
00309 #define MOD17 0x17
00310 #define MOD18 0x18
00311 #define MOD19 0x19
00312 #define MOD1A 0x1a
00313 #define MOD1B 0x1b
00314 #define MOD1C 0x1c
00315 #define MOD1D 0x1d
00316 #define MOD1E 0x1e
00317 #define MOD1F 0x1f
00318 
00319 /* - Peripheral Register Modules - */
00320 /* Serial Register Modules.  */
00321 #define CTRL         MOD8   /* For the module containing the control registers.  */
00322 #define ACC          MOD9   /* For the module containing the 16 accumulators.  */
00323 #define Act_ACC      MODA   /* For the module containing the active accumulator.  */
00324 #define PFX          MODB   /* For the module containing the prefix registers.  */
00325 #define IP           MODC   /* For the module containing the instruction pointer register.  */
00326 #define SPIV         MODD   /* For the module containing the stack pointer and the interrupt vector.  */
00327 #define       LC            MODD   /* For the module containing the loop counters and HILO registers.  */
00328 #define DP           MODF   /* For the module containig the data pointer registers.  */
00329 
00330 /* Register Types.  */
00331 typedef enum _Reg_type
00332 { Reg_8R,                   /* 8 bit register. read only.  */
00333   Reg_16R,                  /* 16 bit register, read only.  */
00334   Reg_8W,                   /* 8 bit register, both read and write.  */
00335   Reg_16W                   /* 16 bit register, both read and write.  */
00336 }
00337 Reg_type;
00338 
00339 /* Register Structure.  */
00340 typedef struct reg
00341 {
00342   char *reg_name;           /* Register name.  */
00343   short int Mod_name;              /* The module name.  */
00344   short int Mod_index;             /* The module index.  */
00345   int opcode;               /* The opcode of the register.  */
00346   Reg_type rtype;           /* 8 bit/16 bit and read only/read write.  */
00347   int arch;                 /* The Machine architecture.  */
00348 }
00349 reg_entry;
00350 
00351 reg_entry *new_reg_table = NULL;
00352 int num_of_reg = 0;
00353 
00354 typedef struct
00355 {
00356   char *rname;
00357   int rindex;
00358 }
00359 reg_index;
00360 
00361 /* Register Table description.  */
00362 reg_entry system_reg_table[] =
00363 {
00364   /* Serial Registers */
00365   /* MODULE 8 Registers : I call them the control registers.  */
00366   /* Accumulator Pointer CTRL[0h] */
00367   {
00368    "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX},
00369   /* Accumulator Pointer Control Register : CTRL[1h] */
00370 
00371   {
00372    "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX},
00373   /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */
00374   {
00375    "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX},
00376   /* Interrupt and Control Register : CTRL[5h] */
00377   {
00378    "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX},
00379   /* Interrupt Mask Register : CTRL[6h] */
00380   {
00381    "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX},
00382   /* Interrupt System Control : CTRL[8h] */
00383   {
00384    "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX},
00385   /* Interrupt Identification Register : CTRL[Bh] */
00386   {
00387    "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX},
00388   /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */
00389   {
00390    "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX},
00391   /* Watchdog Control Register : CTRL[Fh] */
00392   {
00393    "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX},
00394   /* The 16 accumulator registers : ACC[0h-Fh] */
00395   {
00396    "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20},
00397   {
00398    "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20},
00399   {
00400    "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20},
00401   {
00402    "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20},
00403   {
00404    "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20},
00405   {
00406    "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20},
00407   {
00408    "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20},
00409   {
00410    "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20},
00411   {
00412    "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20},
00413   {
00414    "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20},
00415   {
00416    "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20},
00417   {
00418    "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20},
00419   {
00420    "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20},
00421   {
00422    "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20},
00423   {
00424    "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20},
00425   {
00426    "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20},
00427   /* The Active Accumulators : Act_Acc[0h-1h] */
00428   {
00429    "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20},
00430   {
00431    "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20},
00432   /* The 16 accumulator registers : ACC[0h-Fh] */
00433   {
00434    "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10},
00435   {
00436    "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10},
00437   {
00438    "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10},
00439   {
00440    "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10},
00441   {
00442    "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10},
00443   {
00444    "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10},
00445   {
00446    "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10},
00447   {
00448    "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10},
00449   {
00450    "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10},
00451   {
00452    "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10},
00453   {
00454    "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10},
00455   {
00456    "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10},
00457   {
00458    "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10},
00459   {
00460    "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10},
00461   {
00462    "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10},
00463   {
00464    "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10},
00465   /* The Active Accumulators : Act_Acc[0h-1h] */
00466   {
00467    "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10},
00468   /* The Active Accumulators : Act_Acc[0h-1h] */
00469   {
00470    "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10},
00471   /* The Prefix Registers : PFX[0h,2h] */
00472   {
00473    "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX},
00474   {
00475    "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX},
00476   {
00477    "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX},
00478   {
00479    "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX},
00480   {
00481    "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX},
00482   {
00483    "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX},
00484   {
00485    "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX},
00486   {
00487    "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX},
00488   /* The Instruction Pointer Registers : IP[0h,8h] */
00489   {
00490    "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX},
00491   /* The Stack Pointer Registers : SPIV[1h,9h] */
00492   {
00493    "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX},
00494   /* The Interrupt Vector Registers : SPIV[2h,Ah] */
00495   {
00496    "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX},
00497   /* ADDED for New Specification */
00498 
00499   /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */
00500   {
00501    "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX},
00502   {
00503    "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX},
00504   /* MODULE Eh Whole Column has changed */
00505 
00506   {
00507    "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX},
00508   {
00509    "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX},
00510   {
00511    "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX},
00512   {
00513    "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX},
00514   {
00515    "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX},
00516   {
00517    "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX},
00518   {
00519    "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX},
00520   {
00521    "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX},
00522   {
00523    "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX},
00524   /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */
00525   {
00526    "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX},
00527   {
00528    "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX},
00529 };
00530 typedef struct
00531 {
00532   char *name;
00533   int type;
00534 }
00535 match_table;
00536 
00537 #define GPIO0        0x00   /* Gerneral Purpose I/O Module 0.  */
00538 #define GPIO1        0x01   /* Gerneral Purpose I/O Module 1.  */
00539 #define RTC          0x00   /* Real Time Clock Module.  */
00540 #define MAC          0x02   /* Hardware Multiplier Module.  */
00541 #define SER0         0x02   /* Contains the UART Registers.  */
00542 #define SPI          0x03   /* Serial Pheripheral Interface Module.  */
00543 #define OWBM                0x03   /* One Wire Bus Module.  */
00544 #define SER1         0x03   /* Contains the UART Registers.  */
00545 #define TIMER20             0x03   /* Timer Counter Module 2.  */
00546 #define TIMER21             0x04   /* Timer Counter Module 2.  */
00547 #define JTAGD               0x03   /* In-Circuit Debugging Support.  */
00548 #define LCD          0x03   /* LCD register Modules.  */
00549 
00550 /* Plugable modules register table f.  */
00551 
00552 reg_entry peripheral_reg_table[] =
00553 {
00554   /* -------- The GPIO Module Registers -------- */
00555   /* Port n Output Registers : GPIO[0h-4h] */
00556   {
00557    "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX},
00558   {
00559    "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX},
00560   {
00561    "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX},
00562   {
00563    "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX},
00564   /* External Interrupt Flag Register : GPIO[6h] */
00565   {
00566    "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX},
00567   /* External Interrupt Enable Register : GPIO[7h] */
00568   {
00569    "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX},
00570   /* Port n Input Registers : GPIO[8h-Bh] */
00571   {
00572    "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX},
00573   {
00574    "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX},
00575   {
00576    "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX},
00577   {
00578    "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX},
00579   {
00580    "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX},
00581   /* Port n Direction Registers : GPIO[Ch-Fh] */
00582   {
00583    "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX},
00584   {
00585    "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX},
00586   {
00587    "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX},
00588   {
00589    "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX},
00590   /* -------- Real Time Counter Module RTC -------- */
00591   /* RTC Control Register : [01h] */
00592   {
00593    "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX},
00594   /* RTC Seconds High [02h] */
00595   {
00596    "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX},
00597   /* RTC Seconds Low [03h] */
00598   {
00599    "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX},
00600   /* RTC Subsecond Register [04h] */
00601   {
00602    "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX},
00603   /* RTC Alarm seconds high [05h] */
00604   {
00605    "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX},
00606   /* RTC Alarm seconds high [06h] */
00607   {
00608    "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX},
00609   /* RTC Subsecond Alarm Register [07h] */
00610   {
00611    "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX},
00612   /* -------- The GPIO Module Registers -------- */
00613   /* Port n Output Registers : GPIO[0h-4h] */
00614   {
00615    "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX},
00616   {
00617    "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX},
00618   {
00619    "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX},
00620   {
00621    "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX},
00622   /* External Interrupt Flag Register : GPIO[6h] */
00623   {
00624    "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX},
00625   /* External Interrupt Enable Register : GPIO[7h] */
00626   {
00627    "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX},
00628   /* Port n Input Registers : GPIO[8h-Bh] */
00629   {
00630    "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX},
00631   {
00632    "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX},
00633   {
00634    "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX},
00635   {
00636    "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX},
00637   {
00638    "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX},
00639   /* Port n Direction Registers : GPIO[Ch-Fh] */
00640   {
00641    "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX},
00642   {
00643    "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX},
00644   {
00645    "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX},
00646   {
00647    "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX},
00648 #if 0
00649   /* Supply Boltage Check Register */
00650   {
00651    "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX},
00652   /* Wake up output register */
00653   {
00654    "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX},
00655 #endif /* */
00656 
00657   /* -------- MAC Hardware multiplier module -------- */
00658   /* MAC Hardware Multiplier control register: [01h] */
00659   {
00660    "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX},
00661   /* MAC Multiplier Operand A Register [02h] */
00662   {
00663    "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX},
00664   /* MAC Multiplier Operand B Register [03h] */
00665   {
00666    "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX},
00667   /* MAC Multiplier Accumulator 2 Register [04h] */
00668   {
00669    "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX},
00670   /* MAC Multiplier Accumulator 1 Register [05h] */
00671   {
00672    "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX},
00673   /* MAC Multiplier Accumulator 0 Register [06h] */
00674   {
00675    "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX},
00676   /* -------- The Serial I/O module SER -------- */
00677   /* UART registers */
00678   /* Serial Port Control Register : SER[6h] */
00679   {
00680    "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX},
00681   /* Serial Data Buffer Register : SER[7h] */
00682   {
00683    "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX},
00684   /* Serial Port Mode Register : SER[4h] */
00685   {
00686    "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX},
00687   /* Serial Port Phase Register : SER[4h] */
00688   {
00689    "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX},
00690   /* ------ LCD Display Module ---------- */
00691   {
00692    "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX},
00693   {
00694    "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX},
00695   {
00696    "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX},
00697   {
00698    "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX},
00699   {
00700    "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX},
00701   {
00702    "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX},
00703   {
00704    "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX},
00705   {
00706    "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX},
00707   {
00708    "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX},
00709   {
00710    "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX},
00711   {
00712    "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX},
00713   {
00714    "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX},
00715   {
00716    "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX},
00717   {
00718    "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX},
00719   {
00720    "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX},
00721   {
00722    "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX},
00723   {
00724    "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX},
00725   {
00726    "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX},
00727   {
00728    "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX},
00729   /* -------- SPI registers -------- */
00730   /* SPI data buffer Register : SER[7h] */
00731   {
00732    "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX},
00733   /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */
00734   {
00735    "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX},
00736   /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read
00737      only.  */
00738   {
00739    "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX},
00740   /* SPI Clock Register : SER[Ah] */
00741   {
00742    "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX},
00743   /* -------- One Wire Bus Master OWBM -------- */
00744   /* OWBM One Wire address Register register: [01h] */
00745   {
00746    "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX},
00747   /* OWBM One Wire Data register: [02h] */
00748   {
00749    "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX},
00750   /* -------- The Serial I/O module SER -------- */
00751   /* UART registers */
00752   /* Serial Port Control Register : SER[6h] */
00753   {
00754    "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX},
00755   /* Serial Data Buffer Register : SER[7h] */
00756   {
00757    "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX},
00758   /* Serial Port Mode Register : SER[4h] */
00759   {
00760    "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX},
00761   /* Serial Port Phase Register : SER[4h] */
00762   {
00763    "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX},
00764   /* -------- Timer/Counter 2 Module -------- */
00765   /* Timer 2 configuration Register : TC[3h] */
00766   {
00767    "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX},
00768   {
00769    "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX},
00770   {
00771    "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX},
00772   {
00773    "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX},
00774   {
00775    "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX},
00776   {
00777    "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX},
00778   {
00779    "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX},
00780   {
00781    "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX},
00782   {
00783    "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX},
00784   /* Timer 2-1 configuration Register : TC[4h] */
00785 
00786   {
00787    "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX},
00788   {
00789    "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX},
00790   {
00791    "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX},
00792   {
00793    "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX},
00794   {
00795    "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX},
00796   {
00797    "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX},
00798   {
00799    "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX},
00800   {
00801    "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX},
00802   {
00803    "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX},
00804   {
00805    "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX},
00806   {
00807    "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX},
00808   {
00809    "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX},
00810   {
00811    "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX},
00812   {
00813    "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX},
00814   {
00815    "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX},
00816   {
00817    "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX},
00818   {
00819    "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX},
00820   {
00821    "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX},
00822   {
00823    NULL, 0, 0, 0, 0, 0}
00824 };
00825 
00826 /* Memory access argument.  */
00827 struct mem_access
00828 {
00829   char *name;               /* Name of the Memory access operand.  */
00830   int opcode;               /* Its corresponding opcode.  */
00831 };
00832 typedef struct mem_access mem_access;
00833 
00834 /* The Memory table for accessing the data memory through particular registers.  */
00835 struct mem_access mem_table[] =
00836 {
00837   /* The Pop Operation on the stack.  */
00838   {"@SP--", 0x0d},
00839   /* Data Pointer 0 */
00840   {"@DP[0]", 0x0f},
00841   /* Data Ponter 1 */
00842   {"@DP[1]", 0x4f},
00843   /* Data Pointer 0 post increment */
00844   {"@DP[0]++", 0x1f},
00845   /* Data Pointer 1 post increment */
00846   {"@DP[1]++", 0x5f},
00847   /* Data Pointer 0 post decrement */
00848   {"@DP[0]--", 0x2f},
00849   /* Data Pointer 1 post decrement */
00850   {"@DP[1]--", 0x6f},
00851   /* ADDED According to New Specification.  */
00852 
00853   {"@BP[OFFS]", 0x0E},
00854   {"@BP[OFFS++]", 0x1E},
00855   {"@BP[OFFS--]", 0x2E},
00856   {"NUL", 0x76},
00857   {"@++SP", 0x0D},
00858   {"@BP[++OFFS]", 0x1E},
00859   {"@BP[--OFFS]", 0x2E},
00860   {"@++DP[0]", 0x1F},
00861   {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F}
00862 };
00863 
00864 /* Register bit argument.  */
00865 struct reg_bit
00866 {
00867   reg_entry *reg;
00868   int bit;
00869 };
00870 typedef struct reg_bit reg_bit;
00871 
00872 /* There are certain names given to particular bits of some registers.
00873    These will be taken care of here.  */
00874 struct bit_name
00875 {
00876   char *name;
00877   char *reg_bit;
00878 };
00879 typedef struct bit_name bit_name;
00880 
00881 bit_name bit_table[] =
00882 {
00883   {
00884    "RI", "SCON.0"},
00885   /* FOr APC */
00886   {
00887    "MOD0", "APC.0"},
00888   {
00889    "MOD1", "APC.1"},
00890   {
00891    "MOD2", "APC.2"},
00892   {
00893    "IDS", "APC.6"},
00894   {
00895    "CLR", "APC.6"},
00896   /* For PSF */
00897   {
00898    "E", "PSF.0"},
00899   {
00900    "C", "PSF.1"},
00901   {
00902    "OV", "PSF.2"},
00903   {
00904    "S", "PSF.6"},
00905   {
00906    "Z", "PSF.7"},
00907   /* For IC */
00908 
00909   {
00910    "IGE", "IC.0"},
00911   {
00912    "INS", "IC.1"},
00913   {
00914    "CGDS", "IC.5"},
00915   /* For IMR */
00916 
00917   {
00918    "IM0", "IMR.0"},
00919   {
00920    "IM1", "IMR.1"},
00921   {
00922    "IM2", "IMR.2"},
00923   {
00924    "IM3", "IMR.3"},
00925   {
00926    "IM4", "IMR.4"},
00927   {
00928    "IM5", "IMR.5"},
00929   {
00930    "IMS", "IMR.7"},
00931   /* For SC */
00932   {
00933    "PWL", "SC.1"},
00934   {
00935    "ROD", "SC.2"},
00936   {
00937    "UPA", "SC.3"},
00938   {
00939    "CDA0", "SC.4"},
00940   {
00941    "CDA1", "SC.5"},
00942   /* For IIR */
00943 
00944   {
00945    "II0", "IIR.0"},
00946   {
00947    "II1", "IIR.1"},
00948   {
00949    "II2", "IIR.2"},
00950   {
00951    "II3", "IIR.3"},
00952   {
00953    "II4", "IIR.4"},
00954   {
00955    "II5", "IIR.5"},
00956   {
00957    "IIS", "IIR.7"},
00958   /* For CKCN */
00959 
00960   {
00961    "CD0", "CKCN.0"},
00962   {
00963    "CD1", "CKCN.1"},
00964   {
00965    "PMME", "CKCN.2"},
00966   {
00967    "SWB", "CKCN.3"},
00968   {
00969    "STOP", "CKCN.4"},
00970   {
00971    "RGMD", "CKCN.5"},
00972   {
00973    "RGSL", "CKCN.6"},
00974   /* For WDCN */
00975 
00976   {
00977    "RWT", "WDCN.0"},
00978   {
00979    "EWT", "WDCN.1"},
00980   {
00981    "WTRF", "WDCN.2"},
00982   {
00983    "WDIF", "WDCN.3"},
00984   {
00985    "WD0", "WDCN.4"},
00986   {
00987    "WD1", "WDCN.5"},
00988   {
00989    "EWDI", "WDCN.6"},
00990   {
00991    "POR", "WDCN.7"},
00992   /* For DPC */
00993 
00994   {
00995    "DPS0", "DPC.0"},
00996   {
00997    "DPS1", "DPC.1"},
00998   {
00999    "WBS0", "DPC.2"},
01000   {
01001    "WBS1", "DPC.3"},
01002   {
01003    "WBS2", "DPC.4"},
01004 
01005    /* For SCON */  
01006   {
01007    "TI", "SCON.1"},
01008   {
01009    "RB8", "SCON.2"},
01010   {
01011    "TB8", "SCON.3"},
01012   {
01013    "REN", "SCON.4"},
01014   {
01015    "SM2", "SCON.5"},
01016   {
01017    "SM1", "SCON.6"},
01018   {
01019    "SM0", "SCON.7"},
01020   {
01021    "FE", "SCON.7"}
01022 };
01023 
01024 const char *LSInstr[] =
01025 {
01026   "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP",
01027   "DJNZ", "CALL", NULL
01028 };
01029 
01030 typedef enum
01031 {
01032   DST,
01033   SRC,
01034   BOTH,
01035 }
01036 type1;
01037 
01038 struct mem_access_syntax
01039 {
01040   char name[12];            /* Name of the Memory access operand.  */
01041   type1 type;
01042   char *invalid_op[5];
01043 };
01044 typedef struct mem_access_syntax mem_access_syntax;
01045 
01046 /* The Memory Access table for accessing the data memory through particular
01047    registers.  */
01048 const mem_access_syntax mem_access_syntax_table[] =
01049 {
01050   {
01051    "@SP--", SRC,
01052    {
01053     NULL, NULL, NULL, NULL, NULL}},
01054   /* Data Pointer 0 */
01055   {
01056    "@DP[0]", BOTH,
01057    {
01058     "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
01059   /* Data Ponter 1 */
01060   {
01061    "@DP[1]", BOTH,
01062    {
01063     "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
01064   /* Data Pointer 0 post increment */
01065   {
01066    "@DP[0]++", SRC,
01067    {
01068     NULL, NULL, NULL, NULL, NULL}},
01069   /* Data Pointer 1 post increment */
01070   {
01071    "@DP[1]++", SRC,
01072    {
01073     NULL, NULL, NULL, NULL, NULL}},
01074   /* Data Pointer 0 post decrement */
01075   {
01076    "@DP[0]--", SRC,
01077    {
01078     NULL, NULL, NULL, NULL, NULL}},
01079   /* Data Pointer 1 post decrement */
01080   {
01081    "@DP[1]--", SRC,
01082    {
01083     NULL, NULL, NULL, NULL, NULL}},
01084   /* ADDED According to New Specification */
01085 
01086   {
01087    "@BP[OFFS]", BOTH,
01088    {
01089     "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}},
01090   {
01091    "@BP[OFFS++]", SRC,
01092    {
01093     NULL, NULL, NULL, NULL, NULL}},
01094   {
01095    "@BP[OFFS--]", SRC,
01096    {
01097     NULL, NULL, NULL, NULL, NULL}},
01098   {
01099    "NUL", DST,
01100    {
01101     NULL, NULL, NULL, NULL, NULL}},
01102   {
01103    "@++SP", DST,
01104    {
01105     NULL, NULL, NULL, NULL, NULL}},
01106   {
01107    "@BP[++OFFS]", DST,
01108    {
01109     "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
01110   {
01111    "@BP[--OFFS]", DST,
01112    {
01113     "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
01114   {
01115    "@++DP[0]", DST,
01116    {
01117     "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
01118   {
01119    "@++DP[1]", DST,
01120    {
01121     "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
01122   {
01123    "@--DP[0]", DST,
01124    {
01125     "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}},
01126   {
01127    "@--DP[1]", DST,
01128    {
01129     "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}}
01130 };
01131 
01132 #endif