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cell-binutils  2.17cvs20070401
m88k.h
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00001 /* Table of opcodes for the Motorola M88k family.
00002    Copyright 1989, 1990, 1991, 1993, 2001, 2002
00003    Free Software Foundation, Inc.
00004 
00005 This file is part of GDB and GAS.
00006 
00007 This program is free software; you can redistribute it and/or modify
00008 it under the terms of the GNU General Public License as published by
00009 the Free Software Foundation; either version 2 of the License, or
00010 (at your option) any later version.
00011 
00012 This program is distributed in the hope that it will be useful,
00013 but WITHOUT ANY WARRANTY; without even the implied warranty of
00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015 GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this program; if not, write to the Free Software
00019 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 /*
00022  *                   Disassembler Instruction Table
00023  *
00024  *     The first field of the table is the opcode field. If an opcode
00025  *     is specified which has any non-opcode bits on, a system error
00026  *     will occur when the system attempts the install it into the
00027  *     instruction table.  The second parameter is a pointer to the
00028  *     instruction mnemonic. Each operand is specified by offset, width,
00029  *     and type. The offset is the bit number of the least significant
00030  *     bit of the operand with bit 0 being the least significant bit of
00031  *     the instruction. The width is the number of bits used to specify
00032  *     the operand. The type specifies the output format to be used for
00033  *     the operand. The valid formats are: register, register indirect,
00034  *     hex constant, and bit field specification.  The last field is a
00035  *     pointer to the next instruction in the linked list.  These pointers
00036  *     are initialized by init_disasm().
00037  *
00038  *                          Revision History
00039  *
00040  *     Revision 1.0  11/08/85      Creation date
00041  *             1.1   02/05/86      Updated instruction mnemonic table MD
00042  *             1.2   06/16/86      Updated SIM_FLAGS for floating point
00043  *             1.3   09/20/86      Updated for new encoding
00044  *                   05/11/89      R. Trawick adapted from Motorola disassembler
00045  */
00046 
00047 #include <stdio.h>
00048 
00049 /* Define the number of bits in the primary opcode field of the instruction,
00050    the destination field, the source 1 and source 2 fields.  */
00051 
00052 /* Size of opcode field.  */
00053 #define OP 8
00054 
00055 /* Size of destination.  */
00056 #define DEST 6
00057 
00058 /* Size of source1.  */
00059 #define SOURCE1 6
00060 
00061 /* Size of source2.  */
00062 #define SOURCE2 6
00063 
00064 /* Number of registers.  */
00065 #define REGs 32
00066 
00067 /* Type definitions.  */
00068 
00069 typedef unsigned int UINT;
00070 #define    WORD    long
00071 #define    FLAG    unsigned
00072 #define    STATE   short
00073 
00074 /* The next four equates define the priorities that the various classes
00075  * of instructions have regarding writing results back into registers and
00076  * signalling exceptions.  */
00077 
00078 /* PMEM is also defined in <sys/param.h> on Delta 88's.  Sigh!  */
00079 #undef PMEM
00080 
00081 /* Integer priority.  */
00082 #define    PINT  0
00083 
00084 /* Floating point priority.  */
00085 #define    PFLT  1
00086 
00087 /* Memory priority.  */
00088 #define    PMEM  2
00089 
00090 /* Not applicable, instruction doesn't write to regs.  */
00091 #define    NA    3
00092 
00093 /* Highest of these priorities.  */
00094 #define    HIPRI 3
00095 
00096 /* The instruction registers are an artificial mechanism to speed up
00097  * simulator execution.  In the real processor, an instruction register
00098  * is 32 bits wide.  In the simulator, the 32 bit instruction is kept in
00099  * a structure field called rawop, and the instruction is partially decoded,
00100  * and split into various fields and flags which make up the other fields
00101  * of the structure.
00102  * The partial decode is done when the instructions are initially loaded
00103  * into simulator memory.  The simulator code memory is not an array of
00104  * 32 bit words, but is an array of instruction register structures.
00105  * Yes this wastes memory, but it executes much quicker.
00106  */
00107 
00108 struct IR_FIELDS
00109 {
00110   unsigned op:OP,
00111     dest: DEST,
00112     src1: SOURCE1,
00113     src2: SOURCE2;
00114   int ltncy,
00115     extime,
00116     /* Writeback priority.  */
00117     wb_pri;
00118   /* Immediate size.  */
00119   unsigned        imm_flags:2,
00120     /* Register source 1 used.  */
00121     rs1_used:1,
00122     /* Register source 2 used. */
00123     rs2_used:1,
00124     /* Register source/dest. used.  */
00125     rsd_used:1,
00126     /* Complement.  */
00127     c_flag:1,
00128     /* Upper half word.  */
00129     u_flag:1,
00130     /* Execute next.  */
00131     n_flag:1,
00132     /* Uses writeback slot.  */
00133     wb_flag:1,
00134     /* Dest size.  */
00135     dest_64:1,
00136     /* Source 1 size.  */
00137     s1_64:1,
00138     /* Source 2 size.  */
00139     s2_64:1,
00140     scale_flag:1,
00141     /* Scaled register.  */
00142     brk_flg:1;
00143 };
00144 
00145 struct mem_segs
00146 {
00147   /* Pointer (returned by calloc) to segment.  */
00148   struct mem_wrd *seg;                    
00149 
00150   /* Base load address from file headers.  */
00151   unsigned long baseaddr;                 
00152 
00153   /* Ending address of segment.  */
00154   unsigned long endaddr;           
00155 
00156   /* Segment control flags (none defined).  */   
00157   int        flags;                
00158 };
00159 
00160 #define       MAXSEGS              (10)                 /* max number of segment allowed */
00161 #define       MEMSEGSIZE    (sizeof(struct mem_segs))/* size of mem_segs structure */
00162 
00163 #if 0
00164 #define BRK_RD              (0x01)               /* break on memory read */
00165 #define BRK_WR              (0x02)               /* break on memory write */
00166 #define BRK_EXEC     (0x04)               /* break on execution */
00167 #define       BRK_CNT              (0x08)               /* break on terminal count */
00168 #endif
00169 
00170 struct mem_wrd
00171 {
00172   /* Simulator instruction break down.  */
00173   struct IR_FIELDS opcode;
00174   union {
00175     /* Memory element break down.  */
00176     unsigned long  l;
00177     unsigned short s[2];
00178     unsigned char  c[4];
00179   } mem;
00180 };
00181 
00182 /* Size of each 32 bit memory model.  */
00183 #define       MEMWRDSIZE    (sizeof (struct mem_wrd))
00184 
00185 extern struct mem_segs memory[];
00186 extern struct PROCESSOR m78000;
00187 
00188 struct PROCESSOR
00189 {
00190   unsigned WORD
00191   /* Execute instruction pointer.  */
00192   ip, 
00193     /* Vector base register.  */
00194     vbr,
00195     /* Processor status register.  */
00196     psr;
00197   
00198   /* Source 1.  */
00199   WORD    S1bus,
00200     /* Source 2.  */
00201     S2bus,
00202     /* Destination.  */
00203     Dbus,
00204     /* Data address bus.  */
00205     DAbus,
00206     ALU,
00207     /* Data registers.  */
00208     Regs[REGs],
00209     /* Max clocks before reg is available.  */
00210     time_left[REGs],
00211     /* Writeback priority of reg.  */
00212     wb_pri[REGs], 
00213     /* Integer unit control regs.  */
00214     SFU0_regs[REGs],
00215     /* Floating point control regs.  */
00216     SFU1_regs[REGs], 
00217     Scoreboard[REGs],
00218     Vbr;
00219   unsigned WORD   scoreboard,
00220     Psw,
00221     Tpsw;
00222   /* Waiting for a jump instruction.  */
00223   FLAG   jump_pending:1;
00224 };
00225 
00226 /* Size of immediate field.  */
00227 
00228 #define    i26bit      1
00229 #define    i16bit      2
00230 #define    i10bit      3
00231 
00232 /* Definitions for fields in psr.  */
00233 
00234 #define psr_mode  31
00235 #define psr_rbo   30
00236 #define psr_ser   29
00237 #define psr_carry 28
00238 #define psr_sf7m  11
00239 #define psr_sf6m  10
00240 #define psr_sf5m   9
00241 #define psr_sf4m   8
00242 #define psr_sf3m   7
00243 #define psr_sf2m   6
00244 #define psr_sf1m   5
00245 #define psr_mam    4
00246 #define psr_inm    3
00247 #define psr_exm    2
00248 #define psr_trm    1
00249 #define psr_ovfm   0
00250 
00251 /* The 1 clock operations.  */
00252 
00253 #define    ADDU        1
00254 #define    ADDC        2
00255 #define    ADDUC       3
00256 #define    ADD         4
00257 
00258 #define    SUBU    ADD+1
00259 #define    SUBB    ADD+2
00260 #define    SUBUB   ADD+3
00261 #define    SUB     ADD+4
00262 
00263 #define    AND_    ADD+5
00264 #define    OR      ADD+6
00265 #define    XOR     ADD+7
00266 #define    CMP     ADD+8
00267 
00268 /* Loads.  */
00269 
00270 #define    LDAB    CMP+1
00271 #define    LDAH    CMP+2
00272 #define    LDA     CMP+3
00273 #define    LDAD    CMP+4
00274 
00275 #define    LDB   LDAD+1
00276 #define    LDH   LDAD+2
00277 #define    LD    LDAD+3
00278 #define    LDD   LDAD+4
00279 #define    LDBU  LDAD+5
00280 #define    LDHU  LDAD+6
00281 
00282 /* Stores.  */
00283 
00284 #define    STB    LDHU+1
00285 #define    STH    LDHU+2
00286 #define    ST     LDHU+3
00287 #define    STD    LDHU+4
00288 
00289 /* Exchange.  */
00290 
00291 #define    XMEMBU LDHU+5
00292 #define    XMEM   LDHU+6
00293 
00294 /* Branches.  */
00295 
00296 #define    JSR    STD+1
00297 #define    BSR    STD+2
00298 #define    BR     STD+3
00299 #define    JMP    STD+4
00300 #define    BB1    STD+5
00301 #define    BB0    STD+6
00302 #define    RTN    STD+7
00303 #define    BCND   STD+8
00304 
00305 /* Traps.  */
00306 
00307 #define    TB1    BCND+1
00308 #define    TB0    BCND+2
00309 #define    TCND   BCND+3
00310 #define    RTE    BCND+4
00311 #define    TBND   BCND+5
00312 
00313 /* Misc.  */
00314 
00315 #define    MUL     TBND + 1
00316 #define    DIV     MUL  +2
00317 #define    DIVU    MUL  +3
00318 #define    MASK    MUL  +4
00319 #define    FF0     MUL  +5
00320 #define    FF1     MUL  +6
00321 #define    CLR     MUL  +7
00322 #define    SET     MUL  +8
00323 #define    EXT     MUL  +9
00324 #define    EXTU    MUL  +10
00325 #define    MAK     MUL  +11
00326 #define    ROT     MUL  +12
00327 
00328 /* Control register manipulations.  */
00329 
00330 #define    LDCR    ROT  +1
00331 #define    STCR    ROT  +2
00332 #define    XCR     ROT  +3
00333 
00334 #define    FLDCR    ROT  +4
00335 #define    FSTCR    ROT  +5
00336 #define    FXCR     ROT  +6
00337 
00338 #define    NOP     XCR +1
00339 
00340 /* Floating point instructions.  */
00341 
00342 #define    FADD    NOP +1
00343 #define    FSUB    NOP +2
00344 #define    FMUL    NOP +3
00345 #define    FDIV    NOP +4
00346 #define    FSQRT   NOP +5
00347 #define    FCMP    NOP +6
00348 #define    FIP     NOP +7
00349 #define    FLT     NOP +8
00350 #define    INT     NOP +9
00351 #define    NINT    NOP +10
00352 #define    TRNC    NOP +11
00353 #define    FLDC   NOP +12
00354 #define    FSTC   NOP +13
00355 #define    FXC    NOP +14
00356 
00357 #define UEXT(src,off,wid) \
00358   ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
00359 
00360 #define SEXT(src,off,wid) \
00361   (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
00362 
00363 #define MAKE(src,off,wid) \
00364   ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
00365 
00366 #define opword(n) (unsigned long) (memaddr->mem.l)
00367 
00368 /* Constants and masks.  */
00369 
00370 #define SFU0       0x80000000
00371 #define SFU1       0x84000000
00372 #define SFU7       0x9c000000
00373 #define RRI10      0xf0000000
00374 #define RRR        0xf4000000
00375 #define SFUMASK    0xfc00ffe0
00376 #define RRRMASK    0xfc00ffe0
00377 #define RRI10MASK  0xfc00fc00
00378 #define DEFMASK    0xfc000000
00379 #define CTRL       0x0000f000
00380 #define CTRLMASK   0xfc00f800
00381 
00382 /* Operands types.  */
00383 
00384 enum operand_type
00385 {
00386   HEX = 1,
00387   REG = 2,
00388   CONT = 3,
00389   IND = 3,
00390   BF = 4,
00391   /* Scaled register.  */
00392   REGSC = 5,
00393   /* Control register.  */
00394   CRREG = 6,
00395   /* Floating point control register.  */
00396   FCRREG = 7,
00397   PCREL = 8,
00398   CONDMASK = 9,
00399   /* Extended register.  */
00400   XREG = 10,
00401   /* Decimal.  */
00402   DEC = 11
00403 };
00404 
00405 /* Hashing specification.  */
00406 
00407 #define HASHVAL     79
00408 
00409 /* Structure templates.  */
00410 
00411 typedef struct
00412 {
00413   unsigned int offset;
00414   unsigned int width;
00415   enum operand_type type;
00416 } OPSPEC;
00417 
00418 struct SIM_FLAGS
00419 {
00420   int  ltncy,   /* latency (max number of clocks needed to execute).  */
00421     extime,   /* execution time (min number of clocks needed to execute).  */
00422     wb_pri;   /* writeback slot priority.  */
00423   unsigned         op:OP,   /* simulator version of opcode.  */
00424     imm_flags:2,   /* 10,16 or 26 bit immediate flags.  */
00425     rs1_used:1,   /* register source 1 used.  */
00426     rs2_used:1,   /* register source 2 used.  */
00427     rsd_used:1,   /* register source/dest used.  */
00428     c_flag:1,   /* complement.  */
00429     u_flag:1,   /* upper half word.  */
00430     n_flag:1,   /* execute next.  */
00431     wb_flag:1,   /* uses writeback slot.  */
00432     dest_64:1,   /* double precision dest.  */
00433     s1_64:1,   /* double precision source 1.  */
00434     s2_64:1,   /* double precision source 2.  */
00435     scale_flag:1;   /* register is scaled.  */
00436 };
00437 
00438 typedef struct INSTRUCTAB {
00439   unsigned int  opcode;
00440   char          *mnemonic;
00441   OPSPEC        op1,op2,op3;
00442   struct SIM_FLAGS flgs;
00443 } INSTAB;
00444 
00445 
00446 #define NO_OPERAND {0,0,0}
00447 
00448 extern const INSTAB  instructions[];
00449 
00450 /*
00451  * Local Variables:
00452  * fill-column: 131
00453  * End:
00454  */