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cell-binutils  2.17cvs20070401
m68k.h
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00001 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
00002    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
00003    2003, 2004, 2006 Free Software Foundation, Inc.
00004 
00005    This file is part of GDB, GAS, and the GNU binutils.
00006 
00007    GDB, GAS, and the GNU binutils are free software; you can redistribute
00008    them and/or modify them under the terms of the GNU General Public
00009    License as published by the Free Software Foundation; either version
00010    1, or (at your option) any later version.
00011 
00012    GDB, GAS, and the GNU binutils are distributed in the hope that they
00013    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015    the GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with this file; see the file COPYING.  If not, write to the Free
00019    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00020    02110-1301, USA.  */
00021 
00022 /* These are used as bit flags for the arch field in the m68k_opcode
00023    structure.  */
00024 #define       _m68k_undef  0
00025 #define       m68000   0x001
00026 #define       m68010   0x002
00027 #define       m68020   0x004
00028 #define       m68030   0x008
00029 #define       m68040   0x010
00030 #define m68060   0x020
00031 #define       m68881   0x040
00032 #define       m68851   0x080
00033 #define cpu32  0x100        /* e.g., 68332 */
00034 #define fido_a   0x200
00035 #define m68k_mask  0x3ff
00036 
00037 #define mcfmac   0x400             /* ColdFire MAC. */
00038 #define mcfemac  0x800             /* ColdFire EMAC. */
00039 #define cfloat   0x1000            /* ColdFire FPU.  */
00040 #define mcfhwdiv 0x2000            /* ColdFire hardware divide.  */
00041 
00042 #define mcfisa_a 0x4000            /* ColdFire ISA_A.  */
00043 #define mcfisa_aa 0x8000    /* ColdFire ISA_A+.  */
00044 #define mcfisa_b 0x10000           /* ColdFire ISA_B.  */
00045 #define mcfusp   0x20000    /* ColdFire USP instructions.  */
00046 #define mcf_mask 0x3e400
00047 
00048 /* Handy aliases.  */
00049 #define       m68040up   (m68040 | m68060)
00050 #define       m68030up   (m68030 | m68040up)
00051 #define       m68020up   (m68020 | m68030up)
00052 #define       m68010up   (m68010 | cpu32 | fido_a | m68020up)
00053 #define       m68000up   (m68000 | m68010up)
00054 
00055 #define       mfloat  (m68881 | m68040 | m68060)
00056 #define       mmmu    (m68851 | m68030 | m68040 | m68060)
00057 
00058 /* The structure used to hold information for an opcode.  */
00059 
00060 struct m68k_opcode
00061 {
00062   /* The opcode name.  */
00063   const char *name;
00064   /* The pseudo-size of the instruction(in bytes).  Used to determine
00065      number of bytes necessary to disassemble the instruction.  */
00066   unsigned int size;
00067   /* The opcode itself.  */
00068   unsigned long opcode;
00069   /* The mask used by the disassembler.  */
00070   unsigned long match;
00071   /* The arguments.  */
00072   const char *args;
00073   /* The architectures which support this opcode.  */
00074   unsigned int arch;
00075 };
00076 
00077 /* The structure used to hold information for an opcode alias.  */
00078 
00079 struct m68k_opcode_alias
00080 {
00081   /* The alias name.  */
00082   const char *alias;
00083   /* The instruction for which this is an alias.  */
00084   const char *primary;
00085 };
00086 
00087 /* We store four bytes of opcode for all opcodes because that is the
00088    most any of them need.  The actual length of an instruction is
00089    always at least 2 bytes, and is as much longer as necessary to hold
00090    the operands it has.
00091 
00092    The match field is a mask saying which bits must match particular
00093    opcode in order for an instruction to be an instance of that
00094    opcode.
00095 
00096    The args field is a string containing two characters for each
00097    operand of the instruction.  The first specifies the kind of
00098    operand; the second, the place it is stored.  */
00099 
00100 /* Kinds of operands:
00101    Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
00102 
00103    D  data register only.  Stored as 3 bits.
00104    A  address register only.  Stored as 3 bits.
00105    a  address register indirect only.  Stored as 3 bits.
00106    R  either kind of register.  Stored as 4 bits.
00107    r  either kind of register indirect only.  Stored as 4 bits.
00108       At the moment, used only for cas2 instruction.
00109    F  floating point coprocessor register only.   Stored as 3 bits.
00110    O  an offset (or width): immediate data 0-31 or data register.
00111       Stored as 6 bits in special format for BF... insns.
00112    +  autoincrement only.  Stored as 3 bits (number of the address register).
00113    -  autodecrement only.  Stored as 3 bits (number of the address register).
00114    Q  quick immediate data.  Stored as 3 bits.
00115       This matches an immediate operand only when value is in range 1 .. 8.
00116    M  moveq immediate data.  Stored as 8 bits.
00117       This matches an immediate operand only when value is in range -128..127
00118    T  trap vector immediate data.  Stored as 4 bits.
00119 
00120    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
00121       a three bit register offset, depending on the field type.
00122 
00123    #  immediate data.  Stored in special places (b, w or l)
00124       which say how many bits to store.
00125    ^  immediate data for floating point instructions.   Special places
00126       are offset by 2 bytes from '#'...
00127    B  pc-relative address, converted to an offset
00128       that is treated as immediate data.
00129    d  displacement and register.  Stores the register as 3 bits
00130       and stores the displacement in the entire second word.
00131 
00132    C  the CCR.  No need to store it; this is just for filtering validity.
00133    S  the SR.  No need to store, just as with CCR.
00134    U  the USP.  No need to store, just as with CCR.
00135    E  the MAC ACC.  No need to store, just as with CCR.
00136    e  the EMAC ACC[0123].
00137    G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
00138    g  the EMAC ACCEXT{01,23}.
00139    H  the MASK.  No need to store, just as with CCR.
00140    i  the MAC/EMAC scale factor.
00141 
00142    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
00143       extracted from the 'd' field of word one, which means that an extended
00144       coprocessor opcode can be skipped using the 'i' place, if needed.
00145 
00146    s  System Control register for the floating point coprocessor.
00147 
00148    J  Misc register for movec instruction, stored in 'j' format.
00149        Possible values:
00150        0x000  SFC    Source Function Code reg    [60, 40, 30, 20, 10]
00151        0x001  DFC    Data Function Code reg             [60, 40, 30, 20, 10]
00152        0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
00153        0x003  TC     MMU Translation Control            [60, 40]
00154        0x004  ITT0   Instruction Transparent
00155                             Translation reg 0    [60, 40]
00156        0x005  ITT1   Instruction Transparent
00157                             Translation reg 1    [60, 40]
00158        0x006  DTT0   Data Transparent
00159                             Translation reg 0    [60, 40]
00160        0x007  DTT1   Data Transparent
00161                             Translation reg 1    [60, 40]
00162        0x008  BUSCR  Bus Control Register        [60]
00163        0x800  USP    User Stack Pointer          [60, 40, 30, 20, 10]
00164         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
00165        0x802  CAAR   Cache Address Register             [        30, 20]
00166        0x803  MSP    Master Stack Pointer        [    40, 30, 20]
00167        0x804  ISP    Interrupt Stack Pointer            [    40, 30, 20]
00168        0x805  MMUSR  MMU Status reg                     [    40]
00169        0x806  URP    User Root Pointer           [60, 40]
00170        0x807  SRP    Supervisor Root Pointer            [60, 40]
00171        0x808  PCR    Processor Configuration reg [60]
00172        0xC00  ROMBAR ROM Base Address Register   [520X]
00173        0xC04  RAMBAR0       RAM Base Address Register 0 [520X]
00174        0xC05  RAMBAR1       RAM Base Address Register 0 [520X]
00175        0xC0F  MBAR0  RAM Base Address Register 0 [520X]
00176         0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
00177         0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
00178 
00179     L  Register list of the type d0-d7/a0-a7 etc.
00180        (New!  Improved!  Can also hold fp0-fp7, as well!)
00181        The assembler tries to see if the registers match the insn by
00182        looking at where the insn wants them stored.
00183 
00184     l  Register list like L, but with all the bits reversed.
00185        Used for going the other way. . .
00186 
00187     c  cache identifier which may be "nc" for no cache, "ic"
00188        for instruction cache, "dc" for data cache, or "bc"
00189        for both caches.  Used in cinv and cpush.  Always
00190        stored in position "d".
00191 
00192     u  Any register, with ``upper'' or ``lower'' specification.  Used
00193        in the mac instructions with size word.
00194 
00195  The remainder are all stored as 6 bits using an address mode and a
00196  register number; they differ in which addressing modes they match.
00197 
00198    *  all                                 (modes 0-6,7.0-4)
00199    ~  alterable memory                           (modes 2-6,7.0,7.1)
00200                                           (not 0,1,7.2-4)
00201    %  alterable                                  (modes 0-6,7.0,7.1)
00202                                           (not 7.2-4)
00203    ;  data                                (modes 0,2-6,7.0-4)
00204                                           (not 1)
00205    @  data, but not immediate                    (modes 0,2-6,7.0-3)
00206                                           (not 1,7.4)
00207    !  control                             (modes 2,5,6,7.0-3)
00208                                           (not 0,1,3,4,7.4)
00209    &  alterable control                          (modes 2,5,6,7.0,7.1)
00210                                           (not 0,1,3,4,7.2-4)
00211    $  alterable data                      (modes 0,2-6,7.0,7.1)
00212                                           (not 1,7.2-4)
00213    ?  alterable control, or data register (modes 0,2,5,6,7.0,7.1)
00214                                           (not 1,3,4,7.2-4)
00215    /  control, or data register                  (modes 0,2,5,6,7.0-3)
00216                                           (not 1,3,4,7.4)
00217    >  *save operands                      (modes 2,4,5,6,7.0,7.1)
00218                                           (not 0,1,3,7.2-4)
00219    <  *restore operands                          (modes 2,3,5,6,7.0-3)
00220                                           (not 0,1,4,7.4)
00221 
00222    coldfire move operands:
00223    m                                      (modes 0-4)
00224    n                                      (modes 5,7.2)
00225    o                                      (modes 6,7.0,7.1,7.3,7.4)
00226    p                                      (modes 0-5)
00227 
00228    coldfire bset/bclr/btst/mulsl/mulul operands:
00229    q                                      (modes 0,2-5)
00230    v                                      (modes 0,2-5,7.0,7.1)
00231    b                                            (modes 0,2-5,7.2)
00232    w                                            (modes 2-5,7.2)
00233    y                                      (modes 2,5)
00234    z                                      (modes 2,5,7.2)
00235    x  mov3q immediate operand.
00236    4                                      (modes 2,3,4,5)
00237   */
00238 
00239 /* For the 68851:  */
00240 /* I didn't use much imagination in choosing the
00241    following codes, so many of them aren't very
00242    mnemonic. -rab
00243 
00244    0  32 bit pmmu register
00245        Possible values:
00246        000    TC     Translation Control Register (68030, 68851)
00247 
00248    1  16 bit pmmu register
00249        111    AC     Access Control (68851)
00250 
00251    2  8 bit pmmu register
00252        100    CAL    Current Access Level (68851)
00253        101    VAL    Validate Access Level (68851)
00254        110    SCC    Stack Change Control (68851)
00255 
00256    3  68030-only pmmu registers (32 bit)
00257        010    TT0    Transparent Translation reg 0
00258                      (aka Access Control reg 0 -- AC0 -- on 68ec030)
00259        011    TT1    Transparent Translation reg 1
00260                      (aka Access Control reg 1 -- AC1 -- on 68ec030)
00261 
00262    W  wide pmmu registers
00263        Possible values:
00264        001    DRP    Dma Root Pointer (68851)
00265        010    SRP    Supervisor Root Pointer (68030, 68851)
00266        011    CRP    Cpu Root Pointer (68030, 68851)
00267 
00268    f   function code register (68030, 68851)
00269        0      SFC
00270        1      DFC
00271 
00272    V   VAL register only (68851)
00273 
00274    X   BADx, BACx (16 bit)
00275        100    BAD    Breakpoint Acknowledge Data (68851)
00276        101    BAC    Breakpoint Acknowledge Control (68851)
00277 
00278    Y   PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
00279    Z   PCSR (68851)
00280 
00281    |   memory               (modes 2-6, 7.*)
00282 
00283    t  address test level (68030 only)
00284       Stored as 3 bits, range 0-7.
00285       Also used for breakpoint instruction now.
00286 
00287 */
00288 
00289 /* Places to put an operand, for non-general operands:
00290    Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
00291 
00292    s  source, low bits of first word.
00293    d  dest, shifted 9 in first word
00294    1  second word, shifted 12
00295    2  second word, shifted 6
00296    3  second word, shifted 0
00297    4  third word, shifted 12
00298    5  third word, shifted 6
00299    6  third word, shifted 0
00300    7  second word, shifted 7
00301    8  second word, shifted 10
00302    9  second word, shifted 5
00303    D  store in both place 1 and place 3; for divul and divsl.
00304    B  first word, low byte, for branch displacements
00305    W  second word (entire), for branch displacements
00306    L  second and third words (entire), for branch displacements
00307       (also overloaded for move16)
00308    b  second word, low byte
00309    w  second word (entire) [variable word/long branch offset for dbra]
00310    W  second word (entire) (must be signed 16 bit value)
00311    l  second and third word (entire)
00312    g  variable branch offset for bra and similar instructions.
00313       The place to store depends on the magnitude of offset.
00314    t  store in both place 7 and place 8; for floating point operations
00315    c  branch offset for cpBcc operations.
00316       The place to store is word two if bit six of word one is zero,
00317       and words two and three if bit six of word one is one.
00318    i  Increment by two, to skip over coprocessor extended operands.   Only
00319       works with the 'I' format.
00320    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
00321       Also used for dynamic fmovem instruction.
00322    C  floating point coprocessor constant - 7 bits.  Also used for static
00323       K-factors...
00324    j  Movec register #, stored in 12 low bits of second word.
00325    m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
00326       and remaining 3 bits of register shifted 9 bits in first word.
00327       Indicate upper/lower in 1 bit shifted 7 bits in second word.
00328       Use with `R' or `u' format.
00329    n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
00330       with MSB shifted 6 bits in first word and remaining 3 bits of
00331       register shifted 9 bits in first word.  No upper/lower
00332       indication is done.)  Use with `R' or `u' format.
00333    o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
00334       Indicate upper/lower in 1 bit shifted 7 bits in second word.
00335       Use with `R' or `u' format.
00336    M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
00337       upper/lower in 1 bit shifted 6 bits in second word.  Use with
00338       `R' or `u' format.
00339    N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
00340       upper/lower in 1 bit shifted 6 bits in second word.  Use with
00341       `R' or `u' format.
00342    h  shift indicator (scale factor), 1 bit shifted 10 in second word
00343 
00344  Places to put operand, for general operands:
00345    d  destination, shifted 6 bits in first word
00346    b  source, at low bit of first word, and immediate uses one byte
00347    w  source, at low bit of first word, and immediate uses two bytes
00348    l  source, at low bit of first word, and immediate uses four bytes
00349    s  source, at low bit of first word.
00350       Used sometimes in contexts where immediate is not allowed anyway.
00351    f  single precision float, low bit of 1st word, immediate uses 4 bytes
00352    F  double precision float, low bit of 1st word, immediate uses 8 bytes
00353    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
00354    p  packed float, low bit of 1st word, immediate uses 12 bytes
00355    G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
00356    H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
00357    F  EMAC ACCx
00358    f  EMAC ACCy
00359    I  MAC/EMAC scale factor
00360    /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
00361    ]  first word, bit 10
00362 */
00363 
00364 extern const struct m68k_opcode m68k_opcodes[];
00365 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
00366 
00367 extern const int m68k_numopcodes, m68k_numaliases;
00368 
00369 /* end of m68k-opcode.h */