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ia64.h
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00001 /* ia64.h -- Header file for ia64 opcode table
00002    Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
00003    Free Software Foundation, Inc.
00004    Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
00005 
00006 #ifndef opcode_ia64_h
00007 #define opcode_ia64_h
00008 
00009 #include <sys/types.h>
00010 
00011 #include "bfd.h"
00012 
00013 
00014 typedef BFD_HOST_U_64_BIT ia64_insn;
00015 
00016 enum ia64_insn_type
00017   {
00018     IA64_TYPE_NIL = 0,      /* illegal type */
00019     IA64_TYPE_A,     /* integer alu (I- or M-unit) */
00020     IA64_TYPE_I,     /* non-alu integer (I-unit) */
00021     IA64_TYPE_M,     /* memory (M-unit) */
00022     IA64_TYPE_B,     /* branch (B-unit) */
00023     IA64_TYPE_F,     /* floating-point (F-unit) */
00024     IA64_TYPE_X,     /* long encoding (X-unit) */
00025     IA64_TYPE_DYN,   /* Dynamic opcode */
00026     IA64_NUM_TYPES
00027   };
00028 
00029 enum ia64_unit
00030   {
00031     IA64_UNIT_NIL = 0,      /* illegal unit */
00032     IA64_UNIT_I,     /* integer unit */
00033     IA64_UNIT_M,     /* memory unit */
00034     IA64_UNIT_B,     /* branching unit */
00035     IA64_UNIT_F,     /* floating-point unit */
00036     IA64_UNIT_L,     /* long "unit" */
00037     IA64_UNIT_X,     /* may be integer or branch unit */
00038     IA64_NUM_UNITS
00039   };
00040 
00041 /* Changes to this enumeration must be propagated to the operand table in
00042    bfd/cpu-ia64-opc.c
00043  */
00044 enum ia64_opnd
00045   {
00046     IA64_OPND_NIL,   /* no operand---MUST BE FIRST!*/
00047 
00048     /* constants */
00049     IA64_OPND_AR_CSD,       /* application register csd (ar.csd) */
00050     IA64_OPND_AR_CCV,       /* application register ccv (ar.ccv) */
00051     IA64_OPND_AR_PFS,       /* application register pfs (ar.pfs) */
00052     IA64_OPND_C1,    /* the constant 1 */
00053     IA64_OPND_C8,    /* the constant 8 */
00054     IA64_OPND_C16,   /* the constant 16 */
00055     IA64_OPND_GR0,   /* gr0 */
00056     IA64_OPND_IP,    /* instruction pointer (ip) */
00057     IA64_OPND_PR,    /* predicate register (pr) */
00058     IA64_OPND_PR_ROT,       /* rotating predicate register (pr.rot) */
00059     IA64_OPND_PSR,   /* processor status register (psr) */
00060     IA64_OPND_PSR_L, /* processor status register L (psr.l) */
00061     IA64_OPND_PSR_UM,       /* processor status register UM (psr.um) */
00062 
00063     /* register operands: */
00064     IA64_OPND_AR3,   /* third application register # (bits 20-26) */
00065     IA64_OPND_B1,    /* branch register # (bits 6-8) */
00066     IA64_OPND_B2,    /* branch register # (bits 13-15) */
00067     IA64_OPND_CR3,   /* third control register # (bits 20-26) */
00068     IA64_OPND_F1,    /* first floating-point register # */
00069     IA64_OPND_F2,    /* second floating-point register # */
00070     IA64_OPND_F3,    /* third floating-point register # */
00071     IA64_OPND_F4,    /* fourth floating-point register # */
00072     IA64_OPND_P1,    /* first predicate # */
00073     IA64_OPND_P2,    /* second predicate # */
00074     IA64_OPND_R1,    /* first register # */
00075     IA64_OPND_R2,    /* second register # */
00076     IA64_OPND_R3,    /* third register # */
00077     IA64_OPND_R3_2,  /* third register # (limited to gr0-gr3) */
00078 
00079     /* memory operands: */
00080     IA64_OPND_MR3,   /* memory at addr of third register # */
00081 
00082     /* indirect operands: */
00083     IA64_OPND_CPUID_R3,     /* cpuid[reg] */
00084     IA64_OPND_DBR_R3,       /* dbr[reg] */
00085     IA64_OPND_DTR_R3,       /* dtr[reg] */
00086     IA64_OPND_ITR_R3,       /* itr[reg] */
00087     IA64_OPND_IBR_R3,       /* ibr[reg] */
00088     IA64_OPND_MSR_R3,       /* msr[reg] */
00089     IA64_OPND_PKR_R3,       /* pkr[reg] */
00090     IA64_OPND_PMC_R3,       /* pmc[reg] */
00091     IA64_OPND_PMD_R3,       /* pmd[reg] */
00092     IA64_OPND_RR_R3, /* rr[reg] */
00093 
00094     /* immediate operands: */
00095     IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
00096     IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
00097     IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
00098     IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
00099     IA64_OPND_CNT5,  /* 5-bit count (bits 14-18) */
00100     IA64_OPND_CNT6,  /* 6-bit count (bits 27-32) */
00101     IA64_OPND_CPOS6a,       /* 6-bit count (63 - bits 20-25) */
00102     IA64_OPND_CPOS6b,       /* 6-bit count (63 - bits 14-19) */
00103     IA64_OPND_CPOS6c,       /* 6-bit count (63 - bits 31-36) */
00104     IA64_OPND_IMM1,  /* signed 1-bit immediate (bit 36) */
00105     IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
00106     IA64_OPND_IMMU5b,       /* unsigned 5-bit immediate (32 + bits 14-18) */
00107     IA64_OPND_IMMU7a,       /* unsigned 7-bit immediate (bits 13-19) */
00108     IA64_OPND_IMMU7b,       /* unsigned 7-bit immediate (bits 20-26) */
00109     IA64_OPND_SOF,   /* 8-bit stack frame size */
00110     IA64_OPND_SOL,   /* 8-bit size of locals */
00111     IA64_OPND_SOR,   /* 6-bit number of rotating registers (scaled by 8) */
00112     IA64_OPND_IMM8,  /* signed 8-bit immediate (bits 13-19 & 36) */
00113     IA64_OPND_IMM8U4,       /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
00114     IA64_OPND_IMM8M1,       /* signed 8-bit immediate -1 (bits 13-19 & 36) */
00115     IA64_OPND_IMM8M1U4,     /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
00116     IA64_OPND_IMM8M1U8,     /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
00117     IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
00118     IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
00119     IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
00120     IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
00121     IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
00122     IA64_OPND_IMMU21,       /* unsigned 21-bit immediate (bits 6-25, 36) */
00123     IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
00124     IA64_OPND_IMMU24,       /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
00125     IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
00126     IA64_OPND_IMMU62,       /* unsigned 62-bit immediate */
00127     IA64_OPND_IMMU64,       /* unsigned 64-bit immediate (lotsa bits...) */
00128     IA64_OPND_INC3,  /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
00129     IA64_OPND_LEN4,  /* 4-bit count (bits 27-30 + 1) */
00130     IA64_OPND_LEN6,  /* 6-bit count (bits 27-32 + 1) */
00131     IA64_OPND_MBTYPE4,      /* 4-bit mux type (bits 20-23) */
00132     IA64_OPND_MHTYPE8,      /* 8-bit mux type (bits 20-27) */
00133     IA64_OPND_POS6,  /* 6-bit count (bits 14-19) */
00134     IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
00135     IA64_OPND_TAG13b,       /* signed 13-bit tag (ip + 16*bits 24-32) */
00136     IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
00137     IA64_OPND_TGT25b,       /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
00138     IA64_OPND_TGT25c,       /* signed 25-bit (ip + 16*bits 13-32, 36) */
00139     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
00140     IA64_OPND_LDXMOV,       /* any symbol, generates R_IA64_LDXMOV.  */
00141 
00142     IA64_OPND_COUNT  /* # of operand types (MUST BE LAST!) */
00143   };
00144 
00145 enum ia64_dependency_mode
00146 {
00147   IA64_DV_RAW,
00148   IA64_DV_WAW,
00149   IA64_DV_WAR,
00150 };
00151 
00152 enum ia64_dependency_semantics
00153 {
00154   IA64_DVS_NONE,
00155   IA64_DVS_IMPLIED,
00156   IA64_DVS_IMPLIEDF,
00157   IA64_DVS_DATA,
00158   IA64_DVS_INSTR,
00159   IA64_DVS_SPECIFIC,
00160   IA64_DVS_STOP,
00161   IA64_DVS_OTHER,
00162 };
00163 
00164 enum ia64_resource_specifier
00165 {
00166   IA64_RS_ANY,
00167   IA64_RS_AR_K,
00168   IA64_RS_AR_UNAT,
00169   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
00170   IA64_RS_ARb, /* 48-63, 112-127 */
00171   IA64_RS_BR,
00172   IA64_RS_CFM,
00173   IA64_RS_CPUID,
00174   IA64_RS_CR_IRR,
00175   IA64_RS_CR_LRR,
00176   IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
00177   IA64_RS_DBR,
00178   IA64_RS_FR,
00179   IA64_RS_FRb,
00180   IA64_RS_GR0,
00181   IA64_RS_GR,
00182   IA64_RS_IBR,
00183   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
00184   IA64_RS_MSR,
00185   IA64_RS_PKR,
00186   IA64_RS_PMC,
00187   IA64_RS_PMD,
00188   IA64_RS_PR,  /* non-rotating, 1-15 */
00189   IA64_RS_PRr, /* rotating, 16-62 */
00190   IA64_RS_PR63,
00191   IA64_RS_RR,
00192 
00193   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
00194   IA64_RS_CRX, /* CRs not in RS_CR */
00195   IA64_RS_PSR, /* PSR bits */
00196   IA64_RS_RSE, /* implementation-specific RSE resources */
00197   IA64_RS_AR_FPSR,
00198 };
00199 
00200 enum ia64_rse_resource
00201 {
00202   IA64_RSE_N_STACKED_PHYS,
00203   IA64_RSE_BOF,
00204   IA64_RSE_STORE_REG,
00205   IA64_RSE_LOAD_REG,
00206   IA64_RSE_BSPLOAD,
00207   IA64_RSE_RNATBITINDEX,
00208   IA64_RSE_CFLE,
00209   IA64_RSE_NDIRTY,
00210 };
00211 
00212 /* Information about a given resource dependency */
00213 struct ia64_dependency
00214 {
00215   /* Name of the resource */
00216   const char *name;
00217   /* Does this dependency need further specification? */
00218   enum ia64_resource_specifier specifier;
00219   /* Mode of dependency */
00220   enum ia64_dependency_mode mode;
00221   /* Dependency semantics */
00222   enum ia64_dependency_semantics semantics;
00223   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
00224 #define REG_NONE (-1)
00225   int regindex;
00226   /* Special info on semantics */
00227   const char *info;
00228 };
00229 
00230 /* Two arrays of indexes into the ia64_dependency table.
00231    chks are dependencies to check for conflicts when an opcode is
00232    encountered; regs are dependencies to register (mark as used) when an
00233    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
00234    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
00235    readers (WAR) of a resource.  */
00236 struct ia64_opcode_dependency
00237 {
00238   int nchks;
00239   const unsigned short *chks;
00240   int nregs;
00241   const unsigned short *regs;
00242 };
00243 
00244 /* encode/extract the note/index for a dependency */
00245 #define RDEP(N,X) (((N)<<11)|(X))
00246 #define NOTE(X) (((X)>>11)&0x1F)
00247 #define DEP(X) ((X)&0x7FF)
00248 
00249 /* A template descriptor describes the execution units that are active
00250    for each of the three slots.  It also specifies the location of
00251    instruction group boundaries that may be present between two slots.  */
00252 struct ia64_templ_desc
00253   {
00254     int group_boundary;     /* 0=no boundary, 1=between slot 0 & 1, etc. */
00255     enum ia64_unit exec_unit[3];
00256     const char *name;
00257   };
00258 
00259 /* The opcode table is an array of struct ia64_opcode.  */
00260 
00261 struct ia64_opcode
00262   {
00263     /* The opcode name.  */
00264     const char *name;
00265 
00266     /* The type of the instruction: */
00267     enum ia64_insn_type type;
00268 
00269     /* Number of output operands: */
00270     int num_outputs;
00271 
00272     /* The opcode itself.  Those bits which will be filled in with
00273        operands are zeroes.  */
00274     ia64_insn opcode;
00275 
00276     /* The opcode mask.  This is used by the disassembler.  This is a
00277        mask containing ones indicating those bits which must match the
00278        opcode field, and zeroes indicating those bits which need not
00279        match (and are presumably filled in by operands).  */
00280     ia64_insn mask;
00281 
00282     /* An array of operand codes.  Each code is an index into the
00283        operand table.  They appear in the order which the operands must
00284        appear in assembly code, and are terminated by a zero.  */
00285     enum ia64_opnd operands[5];
00286 
00287     /* One bit flags for the opcode.  These are primarily used to
00288        indicate specific processors and environments support the
00289        instructions.  The defined values are listed below. */
00290     unsigned int flags;
00291 
00292     /* Used by ia64_find_next_opcode (). */
00293     short ent_index;
00294 
00295     /* Opcode dependencies. */
00296     const struct ia64_opcode_dependency *dependencies;
00297   };
00298 
00299 /* Values defined for the flags field of a struct ia64_opcode.  */
00300 
00301 #define IA64_OPCODE_FIRST   (1<<0) /* must be first in an insn group */
00302 #define IA64_OPCODE_X_IN_MLX       (1<<1) /* insn is allowed in X slot of MLX */
00303 #define IA64_OPCODE_LAST    (1<<2) /* must be last in an insn group */
00304 #define IA64_OPCODE_PRIV    (1<<3) /* privileged instruct */
00305 #define IA64_OPCODE_SLOT2   (1<<4) /* insn allowed in slot 2 only */
00306 #define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
00307 #define IA64_OPCODE_PSEUDO  (1<<6) /* insn is a pseudo-op */
00308 #define IA64_OPCODE_F2_EQ_F3       (1<<7) /* constraint: F2 == F3 */
00309 #define IA64_OPCODE_LEN_EQ_64MCNT  (1<<8) /* constraint: LEN == 64-CNT */
00310 #define IA64_OPCODE_MOD_RRBS    (1<<9)    /* modifies all rrbs in CFM */
00311 #define IA64_OPCODE_POSTINC (1<<10)       /* postincrement MR3 operand */
00312 
00313 /* A macro to extract the major opcode from an instruction.  */
00314 #define IA64_OP(i)   (((i) >> 37) & 0xf)
00315 
00316 enum ia64_operand_class
00317   {
00318     IA64_OPND_CLASS_CST,    /* constant */
00319     IA64_OPND_CLASS_REG,    /* register */
00320     IA64_OPND_CLASS_IND,    /* indirect register */
00321     IA64_OPND_CLASS_ABS,    /* absolute value */
00322     IA64_OPND_CLASS_REL,    /* IP-relative value */
00323   };
00324 
00325 /* The operands table is an array of struct ia64_operand.  */
00326 
00327 struct ia64_operand
00328 {
00329   enum ia64_operand_class class;
00330 
00331   /* Set VALUE as the operand bits for the operand of type SELF in the
00332      instruction pointed to by CODE.  If an error occurs, *CODE is not
00333      modified and the returned string describes the cause of the
00334      error.  If no error occurs, NULL is returned.  */
00335   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
00336                       ia64_insn *code);
00337 
00338   /* Extract the operand bits for an operand of type SELF from
00339      instruction CODE store them in *VALUE.  If an error occurs, the
00340      cause of the error is described by the string returned.  If no
00341      error occurs, NULL is returned.  */
00342   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
00343                        ia64_insn *value);
00344 
00345   /* A string whose meaning depends on the operand class.  */
00346 
00347   const char *str;
00348 
00349   struct bit_field
00350     {
00351       /* The number of bits in the operand.  */
00352       int bits;
00353 
00354       /* How far the operand is left shifted in the instruction.  */
00355       int shift;
00356     }
00357   field[4];          /* no operand has more than this many bit-fields */
00358 
00359   unsigned int flags;
00360 
00361   const char *desc;  /* brief description */
00362 };
00363 
00364 /* Values defined for the flags field of a struct ia64_operand.  */
00365 
00366 /* Disassemble as signed decimal (instead of hex): */
00367 #define IA64_OPND_FLAG_DECIMAL_SIGNED     (1<<0)
00368 /* Disassemble as unsigned decimal (instead of hex): */
00369 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED   (1<<1)
00370 
00371 extern const struct ia64_templ_desc ia64_templ_desc[16];
00372 
00373 /* The tables are sorted by major opcode number and are otherwise in
00374    the order in which the disassembler should consider instructions.  */
00375 extern struct ia64_opcode ia64_opcodes_a[];
00376 extern struct ia64_opcode ia64_opcodes_i[];
00377 extern struct ia64_opcode ia64_opcodes_m[];
00378 extern struct ia64_opcode ia64_opcodes_b[];
00379 extern struct ia64_opcode ia64_opcodes_f[];
00380 extern struct ia64_opcode ia64_opcodes_d[];
00381 
00382 
00383 extern struct ia64_opcode *ia64_find_opcode (const char *name);
00384 extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
00385 
00386 extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
00387                                        enum ia64_insn_type type);
00388 
00389 extern void ia64_free_opcode (struct ia64_opcode *ent);
00390 extern const struct ia64_dependency *ia64_find_dependency (int index);
00391 
00392 /* To avoid circular library dependencies, this array is implemented
00393    in bfd/cpu-ia64-opc.c: */
00394 extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
00395 
00396 #endif /* opcode_ia64_h */