Back to index

cell-binutils  2.17cvs20070401
i960.h
Go to the documentation of this file.
00001 /* Basic 80960 instruction formats.
00002 
00003    Copyright 2001 Free Software Foundation, Inc.
00004    
00005    This program is free software; you can redistribute it and/or modify
00006    it under the terms of the GNU General Public License as published by
00007    the Free Software Foundation; either version 2, or (at your option)
00008    any later version.
00009 
00010    This program is distributed in the hope that it will be useful,
00011    but WITHOUT ANY WARRANTY; without even the implied warranty of
00012    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013    GNU General Public License for more details.
00014 
00015    You should have received a copy of the GNU General Public License
00016    along with this program; if not, write to the Free Software
00017    Foundation, Inc., 51 Franklin Street - Fifth Floor,
00018    Boston, MA 02110-1301, USA.
00019  
00020   The 'COJ' instructions are actually COBR instructions with the 'b' in
00021   the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if necessary:
00022   if the displacement will not fit in 13 bits, the assembler will replace them
00023   with the corresponding compare and branch instructions.
00024  
00025   All of the 'MEMn' instructions are the same format; the 'n' in the name
00026   indicates the default index scale factor (the size of the datum operated on).
00027  
00028   The FBRA formats are not actually an instruction format.  They are the
00029   "convenience directives" for branching on floating-point comparisons,
00030   each of which generates 2 instructions (a 'bno' and one other branch).
00031  
00032   The CALLJ format is not actually an instruction format.  It indicates that
00033   the instruction generated (a CTRL-format 'call') should have its relocation
00034   specially flagged for link-time replacement with a 'bal' or 'calls' if
00035   appropriate.  */ 
00036 
00037 #define CTRL  0
00038 #define COBR  1
00039 #define COJ   2
00040 #define REG   3
00041 #define MEM1  4
00042 #define MEM2  5
00043 #define MEM4  6
00044 #define MEM8  7
00045 #define MEM12 8
00046 #define MEM16 9
00047 #define FBRA  10
00048 #define CALLJ 11
00049 
00050 /* Masks for the mode bits in REG format instructions */
00051 #define M1           0x0800
00052 #define M2           0x1000
00053 #define M3           0x2000
00054 
00055 /* Generate the 12-bit opcode for a REG format instruction by placing the 
00056  * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
00057  * 7-10.
00058  */
00059 
00060 #define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
00061 
00062 /* Generate a template for a REG format instruction:  place the opcode bits
00063  * in the appropriate fields and OR in mode bits for the operands that will not
00064  * be used.  I.e.,
00065  *            set m1=1, if src1 will not be used
00066  *            set m2=1, if src2 will not be used
00067  *            set m3=1, if dst  will not be used
00068  *
00069  * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
00070  * The information is also useful to us because some 1-operand REG instructions
00071  * use the src1 field, others the dst field; and some 2-operand REG instructions
00072  * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
00073  */
00074 #define R_0(opc)     ( REG_OPC(opc) | M1 | M2 | M3 )    /* No operands      */
00075 #define R_1(opc)     ( REG_OPC(opc) | M2 | M3 )  /* 1 operand: src1  */
00076 #define R_1D(opc)    ( REG_OPC(opc) | M1 | M2 )  /* 1 operand: dst   */
00077 #define R_2(opc)     ( REG_OPC(opc) | M3 )              /* 2 ops: src1/src2 */
00078 #define R_2D(opc)    ( REG_OPC(opc) | M2 )              /* 2 ops: src1/dst  */
00079 #define R_3(opc)     ( REG_OPC(opc) )            /* 3 operands       */
00080 
00081 /* DESCRIPTOR BYTES FOR REGISTER OPERANDS
00082  *
00083  * Interpret names as follows:
00084  *     R:   global or local register only
00085  *     RS:  global, local, or (if target allows) special-function register only
00086  *     RL:  global or local register, or integer literal
00087  *     RSL: global, local, or (if target allows) special-function register;
00088  *            or integer literal
00089  *     F:   global, local, or floating-point register
00090  *     FL:  global, local, or floating-point register; or literal (including
00091  *            floating point)
00092  *
00093  * A number appended to a name indicates that registers must be aligned,
00094  * as follows:
00095  *     2: register number must be multiple of 2
00096  *     4: register number must be multiple of 4
00097  */
00098 
00099 #define SFR   0x10          /* Mask for the "sfr-OK" bit */
00100 #define LIT   0x08          /* Mask for the "literal-OK" bit */
00101 #define FP    0x04          /* Mask for "floating-point-OK" bit */
00102 
00103 /* This macro ors the bits together.  Note that 'align' is a mask
00104  * for the low 0, 1, or 2 bits of the register number, as appropriate.
00105  */
00106 #define OP(align,lit,fp,sfr)       ( align | lit | fp | sfr )
00107 
00108 #define R     OP( 0, 0,   0,  0   )
00109 #define RS    OP( 0, 0,   0,  SFR )
00110 #define RL    OP( 0, LIT, 0,  0   )
00111 #define RSL   OP( 0, LIT, 0,  SFR )
00112 #define F     OP( 0, 0,   FP, 0   )
00113 #define FL    OP( 0, LIT, FP, 0   )
00114 #define R2    OP( 1, 0,   0,  0   )
00115 #define RL2   OP( 1, LIT, 0,  0   )
00116 #define F2    OP( 1, 0,   FP, 0   )
00117 #define FL2   OP( 1, LIT, FP, 0   )
00118 #define R4    OP( 3, 0,   0,  0   )
00119 #define RL4   OP( 3, LIT, 0,  0   )
00120 #define F4    OP( 3, 0,   FP, 0   )
00121 #define FL4   OP( 3, LIT, FP, 0   )
00122 
00123 #define M     0x7f   /* Memory operand (MEMA & MEMB format instructions) */
00124 
00125 /* Macros to extract info from the register operand descriptor byte 'od'.
00126  */
00127 #define SFR_OK(od)   (od & SFR)    /* TRUE if sfr operand allowed */
00128 #define LIT_OK(od)   (od & LIT)    /* TRUE if literal operand allowed */
00129 #define FP_OK(od)    (od & FP)     /* TRUE if floating-point op allowed */
00130 #define REG_ALIGN(od,n)     ((od & 0x3 & n) == 0)
00131                                    /* TRUE if reg #n is properly aligned */
00132 #define MEMOP(od)    (od == M)     /* TRUE if operand is a memory operand*/
00133 
00134 /* Description of a single i80960 instruction */
00135 struct i960_opcode {
00136        long opcode;  /* 32 bits, constant fields filled in, rest zeroed */
00137        char *name;   /* Assembler mnemonic                               */
00138        short iclass; /* Class: see #defines below                        */
00139        char format;  /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ       */
00140        char num_ops; /* Number of operands                               */
00141        char operand[3];/* Operand descriptors; same order as assembler instr */
00142 };
00143 
00144 /* Classes of 960 intructions:
00145  *     - each instruction falls into one class.
00146  *     - each target architecture supports one or more classes.
00147  *
00148  * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
00149  */
00150 #define I_BASE       0x01   /* 80960 base instruction set      */
00151 #define I_CX  0x02   /* 80960Cx instruction             */
00152 #define I_DEC 0x04   /* Decimal instruction             */
00153 #define I_FP  0x08   /* Floating point instruction      */
00154 #define I_KX  0x10   /* 80960Kx instruction             */
00155 #define I_MIL 0x20   /* Military instruction            */
00156 #define I_CASIM      0x40   /* CA simulator instruction */
00157 #define I_CX2 0x80   /* Cx/Jx/Hx instructions    */
00158 #define I_JX  0x100  /* Jx/Hx instruction        */
00159 #define I_HX  0x200  /* Hx instructions          */
00160 
00161 /******************************************************************************
00162  *
00163  *            TABLE OF i960 INSTRUCTION DESCRIPTIONS
00164  *
00165  ******************************************************************************/
00166 
00167 const struct i960_opcode i960_opcodes[] = {
00168 
00169        /* if a CTRL instruction has an operand, it's always a displacement */
00170 
00171        /* callj default=='call' */
00172        { 0x09000000, "callj",      I_BASE,       CALLJ,        1, { 0, 0, 0 } },
00173        { 0x08000000, "b",          I_BASE,       CTRL,  1, { 0, 0, 0 } },
00174        { 0x09000000, "call",              I_BASE,       CTRL,  1, { 0, 0, 0 } },
00175        { 0x0a000000, "ret",        I_BASE,       CTRL,  0, { 0, 0, 0 } },
00176        { 0x0b000000, "bal",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00177        { 0x10000000, "bno",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00178        /* bf same as bno */
00179        { 0x10000000, "bf",         I_BASE,       CTRL,  1, { 0, 0, 0 } },
00180        /* bru same as bno */
00181        { 0x10000000, "bru",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00182        { 0x11000000, "bg",         I_BASE,       CTRL,  1, { 0, 0, 0 } },
00183        /* brg same as bg */
00184        { 0x11000000, "brg",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00185        { 0x12000000, "be",         I_BASE,       CTRL,  1, { 0, 0, 0 } },
00186        /* bre same as be */
00187        { 0x12000000, "bre",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00188        { 0x13000000, "bge",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00189        /* brge same as bge */
00190        { 0x13000000, "brge",              I_BASE,       CTRL,  1, { 0, 0, 0 } },
00191        { 0x14000000, "bl",         I_BASE,       CTRL,  1, { 0, 0, 0 } },
00192        /* brl same as bl */
00193        { 0x14000000, "brl",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00194        { 0x15000000, "bne",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00195        /* brlg same as bne */
00196        { 0x15000000, "brlg",              I_BASE,       CTRL,  1, { 0, 0, 0 } },
00197        { 0x16000000, "ble",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00198        /* brle same as ble */
00199        { 0x16000000, "brle",              I_BASE,       CTRL,  1, { 0, 0, 0 } },
00200        { 0x17000000, "bo",         I_BASE,       CTRL,  1, { 0, 0, 0 } },
00201        /* bt same as bo */
00202        { 0x17000000, "bt",         I_BASE,       CTRL,  1, { 0, 0, 0 } },
00203        /* bro same as bo */
00204        { 0x17000000, "bro",        I_BASE,       CTRL,  1, { 0, 0, 0 } },
00205        { 0x18000000, "faultno",    I_BASE,       CTRL,  0, { 0, 0, 0 } },
00206        /* faultf same as faultno */
00207        { 0x18000000, "faultf",     I_BASE,       CTRL,  0, { 0, 0, 0 } },
00208        { 0x19000000, "faultg",     I_BASE,       CTRL,  0, { 0, 0, 0 } },
00209        { 0x1a000000, "faulte",     I_BASE,       CTRL,  0, { 0, 0, 0 } },
00210        { 0x1b000000, "faultge",    I_BASE,       CTRL,  0, { 0, 0, 0 } },
00211        { 0x1c000000, "faultl",     I_BASE,       CTRL,  0, { 0, 0, 0 } },
00212        { 0x1d000000, "faultne",    I_BASE,       CTRL,  0, { 0, 0, 0 } },
00213        { 0x1e000000, "faultle",    I_BASE,       CTRL,  0, { 0, 0, 0 } },
00214        { 0x1f000000, "faulto",     I_BASE,       CTRL,  0, { 0, 0, 0 } },
00215        /* faultt syn for faulto */
00216        { 0x1f000000, "faultt",     I_BASE,       CTRL,  0, { 0, 0, 0 } },
00217 
00218        { 0x01000000, "syscall",    I_CASIM,CTRL,        0, { 0, 0, 0 } },
00219 
00220        /* If a COBR (or COJ) has 3 operands, the last one is always a
00221         * displacement and does not appear explicitly in the table.
00222         */
00223 
00224        { 0x20000000, "testno",     I_BASE,       COBR,  1, { R, 0, 0 }       },
00225        { 0x21000000, "testg",      I_BASE,       COBR,  1, { R, 0, 0 }       },
00226        { 0x22000000, "teste",      I_BASE,       COBR,  1, { R, 0, 0 }       },
00227        { 0x23000000, "testge",     I_BASE,       COBR,  1, { R, 0, 0 }       },
00228        { 0x24000000, "testl",      I_BASE,       COBR,  1, { R, 0, 0 }       },
00229        { 0x25000000, "testne",     I_BASE,       COBR,  1, { R, 0, 0 }       },
00230        { 0x26000000, "testle",     I_BASE,       COBR,  1, { R, 0, 0 }       },
00231        { 0x27000000, "testo",      I_BASE,       COBR,  1, { R, 0, 0 }       },
00232        { 0x30000000, "bbc",        I_BASE,       COBR,  3, { RL, RS, 0 } },
00233        { 0x31000000, "cmpobg",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00234        { 0x32000000, "cmpobe",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00235        { 0x33000000, "cmpobge",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00236        { 0x34000000, "cmpobl",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00237        { 0x35000000, "cmpobne",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00238        { 0x36000000, "cmpoble",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00239        { 0x37000000, "bbs",        I_BASE,       COBR,  3, { RL, RS, 0 } },
00240        { 0x38000000, "cmpibno",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00241        { 0x39000000, "cmpibg",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00242        { 0x3a000000, "cmpibe",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00243        { 0x3b000000, "cmpibge",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00244        { 0x3c000000, "cmpibl",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00245        { 0x3d000000, "cmpibne",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00246        { 0x3e000000, "cmpible",    I_BASE,       COBR,  3, { RL, RS, 0 } },
00247        { 0x3f000000, "cmpibo",     I_BASE,       COBR,  3, { RL, RS, 0 } },
00248        { 0x31000000, "cmpojg",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00249        { 0x32000000, "cmpoje",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00250        { 0x33000000, "cmpojge",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00251        { 0x34000000, "cmpojl",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00252        { 0x35000000, "cmpojne",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00253        { 0x36000000, "cmpojle",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00254        { 0x38000000, "cmpijno",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00255        { 0x39000000, "cmpijg",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00256        { 0x3a000000, "cmpije",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00257        { 0x3b000000, "cmpijge",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00258        { 0x3c000000, "cmpijl",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00259        { 0x3d000000, "cmpijne",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00260        { 0x3e000000, "cmpijle",    I_BASE,       COJ,   3, { RL, RS, 0 } },
00261        { 0x3f000000, "cmpijo",     I_BASE,       COJ,   3, { RL, RS, 0 } },
00262 
00263        { 0x80000000, "ldob",              I_BASE,       MEM1,  2, { M,  R,  0 } },
00264        { 0x82000000, "stob",              I_BASE,       MEM1,  2, { R,  M,  0 } },
00265        { 0x84000000, "bx",         I_BASE,       MEM1,  1, { M,  0,  0 } },
00266        { 0x85000000, "balx",              I_BASE,       MEM1,  2, { M,  R,  0 } },
00267        { 0x86000000, "callx",      I_BASE,       MEM1,  1, { M,  0,  0 } },
00268        { 0x88000000, "ldos",              I_BASE,       MEM2,  2, { M,  R,  0 } },
00269        { 0x8a000000, "stos",              I_BASE,       MEM2,  2, { R,  M,  0 } },
00270        { 0x8c000000, "lda",        I_BASE,       MEM1,  2, { M,  R,  0 } },
00271        { 0x90000000, "ld",         I_BASE,       MEM4,  2, { M,  R,  0 } },
00272        { 0x92000000, "st",         I_BASE,       MEM4,  2, { R,  M,  0 } },
00273        { 0x98000000, "ldl",        I_BASE,       MEM8,  2, { M,  R2, 0 } },
00274        { 0x9a000000, "stl",        I_BASE,       MEM8,  2, { R2, M,  0 } },
00275        { 0xa0000000, "ldt",        I_BASE,       MEM12, 2, { M,  R4, 0 } },
00276        { 0xa2000000, "stt",        I_BASE,       MEM12, 2, { R4, M,  0 } },
00277        { 0xb0000000, "ldq",        I_BASE,       MEM16, 2, { M,  R4, 0 } },
00278        { 0xb2000000, "stq",        I_BASE,       MEM16, 2, { R4, M,  0 } },
00279        { 0xc0000000, "ldib",              I_BASE,       MEM1,  2, { M,  R,  0 } },
00280        { 0xc2000000, "stib",              I_BASE,       MEM1,  2, { R,  M,  0 } },
00281        { 0xc8000000, "ldis",              I_BASE,       MEM2,  2, { M,  R,  0 } },
00282        { 0xca000000, "stis",              I_BASE,       MEM2,  2, { R,  M,  0 } },
00283 
00284        { R_3(0x580), "notbit",     I_BASE,       REG,   3, { RSL,RSL,RS } },
00285        { R_3(0x581), "and",        I_BASE,       REG,   3, { RSL,RSL,RS } },
00286        { R_3(0x582), "andnot",     I_BASE,       REG,   3, { RSL,RSL,RS } },
00287        { R_3(0x583), "setbit",     I_BASE,       REG,   3, { RSL,RSL,RS } },
00288        { R_3(0x584), "notand",     I_BASE,       REG,   3, { RSL,RSL,RS } },
00289        { R_3(0x586), "xor",        I_BASE,       REG,   3, { RSL,RSL,RS } },
00290        { R_3(0x587), "or",         I_BASE,       REG,   3, { RSL,RSL,RS } },
00291        { R_3(0x588), "nor",        I_BASE,       REG,   3, { RSL,RSL,RS } },
00292        { R_3(0x589), "xnor",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00293        { R_2D(0x58a),       "not",        I_BASE,       REG,   2, { RSL,RS, 0 } },
00294        { R_3(0x58b), "ornot",      I_BASE,       REG,   3, { RSL,RSL,RS } },
00295        { R_3(0x58c), "clrbit",     I_BASE,       REG,   3, { RSL,RSL,RS } },
00296        { R_3(0x58d), "notor",      I_BASE,       REG,   3, { RSL,RSL,RS } },
00297        { R_3(0x58e), "nand",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00298        { R_3(0x58f), "alterbit",   I_BASE,       REG,   3, { RSL,RSL,RS } },
00299        { R_3(0x590), "addo",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00300        { R_3(0x591), "addi",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00301        { R_3(0x592), "subo",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00302        { R_3(0x593), "subi",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00303        { R_3(0x598), "shro",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00304        { R_3(0x59a), "shrdi",      I_BASE,       REG,   3, { RSL,RSL,RS } },
00305        { R_3(0x59b), "shri",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00306        { R_3(0x59c), "shlo",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00307        { R_3(0x59d), "rotate",     I_BASE,       REG,   3, { RSL,RSL,RS } },
00308        { R_3(0x59e), "shli",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00309        { R_2(0x5a0), "cmpo",              I_BASE,       REG,   2, { RSL,RSL, 0 } },
00310        { R_2(0x5a1), "cmpi",              I_BASE,       REG,   2, { RSL,RSL, 0 } },
00311        { R_2(0x5a2), "concmpo",    I_BASE,       REG,   2, { RSL,RSL, 0 } },
00312        { R_2(0x5a3), "concmpi",    I_BASE,       REG,   2, { RSL,RSL, 0 } },
00313        { R_3(0x5a4), "cmpinco",    I_BASE,       REG,   3, { RSL,RSL,RS } },
00314        { R_3(0x5a5), "cmpinci",    I_BASE,       REG,   3, { RSL,RSL,RS } },
00315        { R_3(0x5a6), "cmpdeco",    I_BASE,       REG,   3, { RSL,RSL,RS } },
00316        { R_3(0x5a7), "cmpdeci",    I_BASE,       REG,   3, { RSL,RSL,RS } },
00317        { R_2(0x5ac), "scanbyte",   I_BASE,       REG,   2, { RSL,RSL, 0 } },
00318        { R_2(0x5ae), "chkbit",     I_BASE,       REG,   2, { RSL,RSL, 0 } },
00319        { R_3(0x5b0), "addc",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00320        { R_3(0x5b2), "subc",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00321        { R_2D(0x5cc),       "mov",        I_BASE,       REG,   2, { RSL,RS, 0 } },
00322        { R_2D(0x5dc),       "movl",              I_BASE,       REG,   2, { RL2,R2, 0 } },
00323        { R_2D(0x5ec),       "movt",              I_BASE,       REG,   2, { RL4,R4, 0 } },
00324        { R_2D(0x5fc),       "movq",              I_BASE,       REG,   2, { RL4,R4, 0 } },
00325        { R_3(0x610), "atmod",      I_BASE,       REG,   3, { RS, RSL,R } },
00326        { R_3(0x612), "atadd",      I_BASE,       REG,   3, { RS, RSL,RS } },
00327        { R_2D(0x640),       "spanbit",    I_BASE,       REG,   2, { RSL,RS, 0 } },
00328        { R_2D(0x641),       "scanbit",    I_BASE,       REG,   2, { RSL,RS, 0 } },
00329        { R_3(0x645), "modac",      I_BASE,       REG,   3, { RSL,RSL,RS } },
00330        { R_3(0x650), "modify",     I_BASE,       REG,   3, { RSL,RSL,R } },
00331        { R_3(0x651), "extract",    I_BASE,       REG,   3, { RSL,RSL,R } },
00332        { R_3(0x654), "modtc",      I_BASE,       REG,   3, { RSL,RSL,RS } },
00333        { R_3(0x655), "modpc",      I_BASE,       REG,   3, { RSL,RSL,R } },
00334        { R_1(0x660), "calls",      I_BASE,       REG,   1, { RSL, 0, 0 } },
00335        { R_0(0x66b), "mark",              I_BASE,       REG,   0, { 0, 0, 0 }       },
00336        { R_0(0x66c), "fmark",      I_BASE,       REG,   0, { 0, 0, 0 }       },
00337        { R_0(0x66d), "flushreg",   I_BASE,       REG,   0, { 0, 0, 0 }       },
00338        { R_0(0x66f), "syncf",      I_BASE,       REG,   0, { 0, 0, 0 }       },
00339        { R_3(0x670), "emul",              I_BASE,       REG,   3, { RSL,RSL,R2 } },
00340        { R_3(0x671), "ediv",              I_BASE,       REG,   3, { RSL,RL2,RS } },
00341        { R_2D(0x672),       "cvtadr",     I_CASIM,REG,  2, { RL, R2, 0 } },
00342        { R_3(0x701), "mulo",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00343        { R_3(0x708), "remo",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00344        { R_3(0x70b), "divo",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00345        { R_3(0x741), "muli",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00346        { R_3(0x748), "remi",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00347        { R_3(0x749), "modi",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00348        { R_3(0x74b), "divi",              I_BASE,       REG,   3, { RSL,RSL,RS } },
00349 
00350        /* Floating-point instructions */
00351 
00352        { R_2D(0x674),       "cvtir",      I_FP,  REG,   2, { RL, F, 0 } },
00353        { R_2D(0x675),       "cvtilr",     I_FP,  REG,   2, { RL, F, 0 } },
00354        { R_3(0x676), "scalerl",    I_FP,  REG,   3, { RL, FL2,F2 } },
00355        { R_3(0x677), "scaler",     I_FP,  REG,   3, { RL, FL, F } },
00356        { R_3(0x680), "atanr",      I_FP,  REG,   3, { FL, FL, F } },
00357        { R_3(0x681), "logepr",     I_FP,  REG,   3, { FL, FL, F } },
00358        { R_3(0x682), "logr",              I_FP,  REG,   3, { FL, FL, F } },
00359        { R_3(0x683), "remr",              I_FP,  REG,   3, { FL, FL, F } },
00360        { R_2(0x684), "cmpor",      I_FP,  REG,   2, { FL, FL, 0 } },
00361        { R_2(0x685), "cmpr",              I_FP,  REG,   2, { FL, FL, 0 } },
00362        { R_2D(0x688),       "sqrtr",      I_FP,  REG,   2, { FL, F, 0 } },
00363        { R_2D(0x689),       "expr",              I_FP,  REG,   2, { FL, F, 0 } },
00364        { R_2D(0x68a),       "logbnr",     I_FP,  REG,   2, { FL, F, 0 } },
00365        { R_2D(0x68b),       "roundr",     I_FP,  REG,   2, { FL, F, 0 } },
00366        { R_2D(0x68c),       "sinr",              I_FP,  REG,   2, { FL, F, 0 } },
00367        { R_2D(0x68d),       "cosr",              I_FP,  REG,   2, { FL, F, 0 } },
00368        { R_2D(0x68e),       "tanr",              I_FP,  REG,   2, { FL, F, 0 } },
00369        { R_1(0x68f), "classr",     I_FP,  REG,   1, { FL, 0, 0 }      },
00370        { R_3(0x690), "atanrl",     I_FP,  REG,   3, { FL2,FL2,F2 } },
00371        { R_3(0x691), "logeprl",    I_FP,  REG,   3, { FL2,FL2,F2 } },
00372        { R_3(0x692), "logrl",      I_FP,  REG,   3, { FL2,FL2,F2 } },
00373        { R_3(0x693), "remrl",      I_FP,  REG,   3, { FL2,FL2,F2 } },
00374        { R_2(0x694), "cmporl",     I_FP,  REG,   2, { FL2,FL2, 0 } },
00375        { R_2(0x695), "cmprl",      I_FP,  REG,   2, { FL2,FL2, 0 } },
00376        { R_2D(0x698),       "sqrtrl",     I_FP,  REG,   2, { FL2,F2, 0 } },
00377        { R_2D(0x699),       "exprl",      I_FP,  REG,   2, { FL2,F2, 0 } },
00378        { R_2D(0x69a),       "logbnrl",    I_FP,  REG,   2, { FL2,F2, 0 } },
00379        { R_2D(0x69b),       "roundrl",    I_FP,  REG,   2, { FL2,F2, 0 } },
00380        { R_2D(0x69c),       "sinrl",      I_FP,  REG,   2, { FL2,F2, 0 } },
00381        { R_2D(0x69d),       "cosrl",      I_FP,  REG,   2, { FL2,F2, 0 } },
00382        { R_2D(0x69e),       "tanrl",      I_FP,  REG,   2, { FL2,F2, 0 } },
00383        { R_1(0x69f), "classrl",    I_FP,  REG,   1, { FL2, 0, 0 } },
00384        { R_2D(0x6c0),       "cvtri",      I_FP,  REG,   2, { FL, R, 0 } },
00385        { R_2D(0x6c1),       "cvtril",     I_FP,  REG,   2, { FL, R2, 0 } },
00386        { R_2D(0x6c2),       "cvtzri",     I_FP,  REG,   2, { FL, R, 0 } },
00387        { R_2D(0x6c3),       "cvtzril",    I_FP,  REG,   2, { FL, R2, 0 } },
00388        { R_2D(0x6c9),       "movr",              I_FP,  REG,   2, { FL, F, 0 } },
00389        { R_2D(0x6d9),       "movrl",      I_FP,  REG,   2, { FL2,F2, 0 } },
00390        { R_2D(0x6e1),       "movre",      I_FP,  REG,   2, { FL4,F4, 0 } },
00391        { R_3(0x6e2), "cpysre",     I_FP,  REG,   3, { FL4,FL4,F4 } },
00392        { R_3(0x6e3), "cpyrsre",    I_FP,  REG,   3, { FL4,FL4,F4 } },
00393        { R_3(0x78b), "divr",              I_FP,  REG,   3, { FL, FL, F } },
00394        { R_3(0x78c), "mulr",              I_FP,  REG,   3, { FL, FL, F } },
00395        { R_3(0x78d), "subr",              I_FP,  REG,   3, { FL, FL, F } },
00396        { R_3(0x78f), "addr",              I_FP,  REG,   3, { FL, FL, F } },
00397        { R_3(0x79b), "divrl",      I_FP,  REG,   3, { FL2,FL2,F2 } },
00398        { R_3(0x79c), "mulrl",      I_FP,  REG,   3, { FL2,FL2,F2 } },
00399        { R_3(0x79d), "subrl",      I_FP,  REG,   3, { FL2,FL2,F2 } },
00400        { R_3(0x79f), "addrl",      I_FP,  REG,   3, { FL2,FL2,F2 } },
00401 
00402        /* These are the floating point branch instructions.  Each actually
00403         * generates 2 branch instructions:  the first a CTRL instruction with
00404         * the indicated opcode, and the second a 'bno'.
00405         */
00406 
00407        { 0x12000000, "brue",              I_FP,  FBRA,  1, { 0, 0, 0 }       },
00408        { 0x11000000, "brug",              I_FP,  FBRA,  1, { 0, 0, 0 }       },
00409        { 0x13000000, "bruge",      I_FP,  FBRA,  1, { 0, 0, 0 }       },
00410        { 0x14000000, "brul",              I_FP,  FBRA,  1, { 0, 0, 0 }       },
00411        { 0x16000000, "brule",      I_FP,  FBRA,  1, { 0, 0, 0 }       },
00412        { 0x15000000, "brulg",      I_FP,  FBRA,  1, { 0, 0, 0 }       },
00413 
00414 
00415        /* Decimal instructions */
00416 
00417        { R_3(0x642), "daddc",      I_DEC, REG,   3, { RSL,RSL,RS } },
00418        { R_3(0x643), "dsubc",      I_DEC, REG,   3, { RSL,RSL,RS } },
00419        { R_2D(0x644),       "dmovt",      I_DEC, REG,   2, { RSL,RS, 0 } },
00420 
00421 
00422        /* KX extensions */
00423 
00424        { R_2(0x600), "synmov",     I_KX,  REG,   2, { R,  R, 0 } },
00425        { R_2(0x601), "synmovl",    I_KX,  REG,   2, { R,  R, 0 } },
00426        { R_2(0x602), "synmovq",    I_KX,  REG,   2, { R,  R, 0 } },
00427        { R_2D(0x615),       "synld",      I_KX,  REG,   2, { R,  R, 0 } },
00428 
00429 
00430        /* MC extensions */
00431 
00432        { R_3(0x603), "cmpstr",     I_MIL, REG,   3, { R,  R,  RL } },
00433        { R_3(0x604), "movqstr",    I_MIL, REG,   3, { R,  R,  RL } },
00434        { R_3(0x605), "movstr",     I_MIL, REG,   3, { R,  R,  RL } },
00435        { R_2D(0x613),       "inspacc",    I_MIL, REG,   2, { R,  R, 0 } },
00436        { R_2D(0x614),       "ldphy",      I_MIL, REG,   2, { R,  R, 0 } },
00437        { R_3(0x617), "fill",              I_MIL, REG,   3, { R,  RL, RL } },
00438        { R_2D(0x646),       "condrec",    I_MIL, REG,   2, { R,  R, 0 } },
00439        { R_2D(0x656),       "receive",    I_MIL, REG,   2, { R,  R, 0 } },
00440        { R_3(0x662), "send",              I_MIL, REG,   3, { R,  RL, R } },
00441        { R_1(0x663), "sendserv",   I_MIL, REG,   1, { R, 0, 0 }       },
00442        { R_1(0x664), "resumprcs",  I_MIL, REG,   1, { R, 0, 0 }       },
00443        { R_1(0x665), "schedprcs",  I_MIL, REG,   1, { R, 0, 0 }       },
00444        { R_0(0x666), "saveprcs",   I_MIL, REG,   0, { 0, 0, 0 }       },
00445        { R_1(0x668), "condwait",   I_MIL, REG,   1, { R, 0, 0 }       },
00446        { R_1(0x669), "wait",              I_MIL, REG,   1, { R, 0, 0 }       },
00447        { R_1(0x66a), "signal",     I_MIL, REG,   1, { R, 0, 0 }       },
00448        { R_1D(0x673),       "ldtime",     I_MIL, REG,   1, { R2, 0, 0 }      },
00449 
00450 
00451        /* CX extensions */
00452 
00453        { R_3(0x5d8), "eshro",      I_CX2, REG,   3, { RSL,RSL,RS } },
00454        { R_3(0x630), "sdma",              I_CX,  REG,   3, { RSL,RSL,RL } },
00455        { R_3(0x631), "udma",              I_CX,  REG,   0, { 0, 0, 0 }       },
00456        { R_3(0x659), "sysctl",     I_CX2, REG,   3, { RSL,RSL,RL } },
00457 
00458 
00459        /* Jx extensions.  */
00460        { R_3(0x780), "addono",     I_JX,  REG,   3, { RSL,RSL,RS } },
00461        { R_3(0x790), "addog",      I_JX,  REG,   3, { RSL,RSL,RS } },
00462        { R_3(0x7a0), "addoe",      I_JX,  REG,   3, { RSL,RSL,RS } },
00463        { R_3(0x7b0), "addoge",     I_JX,  REG,   3, { RSL,RSL,RS } },
00464        { R_3(0x7c0), "addol",      I_JX,  REG,   3, { RSL,RSL,RS } },
00465        { R_3(0x7d0), "addone",     I_JX,  REG,   3, { RSL,RSL,RS } },
00466        { R_3(0x7e0), "addole",     I_JX,  REG,   3, { RSL,RSL,RS } },
00467        { R_3(0x7f0), "addoo",      I_JX,  REG,   3, { RSL,RSL,RS } },
00468        { R_3(0x781), "addino",     I_JX,  REG,   3, { RSL,RSL,RS } },
00469        { R_3(0x791), "addig",      I_JX,  REG,   3, { RSL,RSL,RS } },
00470        { R_3(0x7a1), "addie",      I_JX,  REG,   3, { RSL,RSL,RS } },
00471        { R_3(0x7b1), "addige",     I_JX,  REG,   3, { RSL,RSL,RS } },
00472        { R_3(0x7c1), "addil",      I_JX,  REG,   3, { RSL,RSL,RS } },
00473        { R_3(0x7d1), "addine",     I_JX,  REG,   3, { RSL,RSL,RS } },
00474        { R_3(0x7e1), "addile",     I_JX,  REG,   3, { RSL,RSL,RS } },
00475        { R_3(0x7f1), "addio",      I_JX,  REG,   3, { RSL,RSL,RS } },
00476 
00477        { R_2D(0x5ad),       "bswap",      I_JX,  REG,   2, { RSL, RS, 0 } },
00478 
00479        { R_2(0x594), "cmpob",      I_JX,  REG,   2, { RSL,RSL, 0 } },
00480        { R_2(0x595), "cmpib",      I_JX,  REG,   2, { RSL,RSL, 0 } },
00481        { R_2(0x596), "cmpos",      I_JX,  REG,   2, { RSL,RSL, 0 } },
00482        { R_2(0x597), "cmpis",      I_JX,  REG,   2, { RSL,RSL, 0 } },
00483 
00484        { R_3(0x784), "selno",      I_JX,  REG,   3, { RSL,RSL,RS } },
00485        { R_3(0x794), "selg",              I_JX,  REG,   3, { RSL,RSL,RS } },
00486        { R_3(0x7a4), "sele",              I_JX,  REG,   3, { RSL,RSL,RS } },
00487        { R_3(0x7b4), "selge",      I_JX,  REG,   3, { RSL,RSL,RS } },
00488        { R_3(0x7c4), "sell",              I_JX,  REG,   3, { RSL,RSL,RS } },
00489        { R_3(0x7d4), "selne",      I_JX,  REG,   3, { RSL,RSL,RS } },
00490        { R_3(0x7e4), "selle",      I_JX,  REG,   3, { RSL,RSL,RS } },
00491        { R_3(0x7f4), "selo",              I_JX,  REG,   3, { RSL,RSL,RS } },
00492 
00493        { R_3(0x782), "subono",     I_JX,  REG,   3, { RSL,RSL,RS } },
00494        { R_3(0x792), "subog",      I_JX,  REG,   3, { RSL,RSL,RS } },
00495        { R_3(0x7a2), "suboe",      I_JX,  REG,   3, { RSL,RSL,RS } },
00496        { R_3(0x7b2), "suboge",     I_JX,  REG,   3, { RSL,RSL,RS } },
00497        { R_3(0x7c2), "subol",      I_JX,  REG,   3, { RSL,RSL,RS } },
00498        { R_3(0x7d2), "subone",     I_JX,  REG,   3, { RSL,RSL,RS } },
00499        { R_3(0x7e2), "subole",     I_JX,  REG,   3, { RSL,RSL,RS } },
00500        { R_3(0x7f2), "suboo",      I_JX,  REG,   3, { RSL,RSL,RS } },
00501        { R_3(0x783), "subino",     I_JX,  REG,   3, { RSL,RSL,RS } },
00502        { R_3(0x793), "subig",      I_JX,  REG,   3, { RSL,RSL,RS } },
00503        { R_3(0x7a3), "subie",      I_JX,  REG,   3, { RSL,RSL,RS } },
00504        { R_3(0x7b3), "subige",     I_JX,  REG,   3, { RSL,RSL,RS } },
00505        { R_3(0x7c3), "subil",      I_JX,  REG,   3, { RSL,RSL,RS } },
00506        { R_3(0x7d3), "subine",     I_JX,  REG,   3, { RSL,RSL,RS } },
00507        { R_3(0x7e3), "subile",     I_JX,  REG,   3, { RSL,RSL,RS } },
00508        { R_3(0x7f3), "subio",      I_JX,  REG,   3, { RSL,RSL,RS } },
00509 
00510        { R_3(0x65c), "dcctl",      I_JX,  REG,   3, { RSL,RSL,RL } },
00511        { R_3(0x65b), "icctl",      I_JX,  REG,   3, { RSL,RSL,RS } },
00512        { R_2D(0x658),       "intctl",     I_JX,  REG,   2, { RSL, RS, 0 } },
00513        { R_0(0x5b4), "intdis",     I_JX,  REG,   0, {   0,  0, 0 } },
00514        { R_0(0x5b5), "inten",      I_JX,  REG,   0, {   0,  0, 0 } },
00515        { R_0(0x65d), "halt",              I_JX,  REG,   1, { RSL,  0, 0 } },
00516 
00517        /* Hx extensions.  */
00518        { 0xac000000, "dcinva",     I_HX,  MEM1,  1, {   M,  0, 0 } },
00519 
00520        /* END OF TABLE */
00521 
00522        { 0,          NULL,         0,     0,     0, { 0, 0, 0 }       }
00523 };
00524 
00525  /* end of i960-opcode.h */