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cell-binutils  2.17cvs20070401
i386.h
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00001 /* opcode/i386.h -- Intel 80386 opcode macros
00002    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
00003    2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
00004    Free Software Foundation, Inc.
00005 
00006    This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
00007 
00008    This program is free software; you can redistribute it and/or modify
00009    it under the terms of the GNU General Public License as published by
00010    the Free Software Foundation; either version 2 of the License, or
00011    (at your option) any later version.
00012 
00013    This program is distributed in the hope that it will be useful,
00014    but WITHOUT ANY WARRANTY; without even the implied warranty of
00015    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016    GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with this program; if not, write to the Free Software
00020    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00021 
00022 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
00023    ix86 Unix assemblers, generate floating point instructions with
00024    reversed source and destination registers in certain cases.
00025    Unfortunately, gcc and possibly many other programs use this
00026    reversed syntax, so we're stuck with it.
00027 
00028    eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
00029    `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
00030    the expected st(3) = st(3) - st
00031 
00032    This happens with all the non-commutative arithmetic floating point
00033    operations with two register operands, where the source register is
00034    %st, and destination register is %st(i).
00035 
00036    The affected opcode map is dceX, dcfX, deeX, defX.  */
00037 
00038 #ifndef SYSV386_COMPAT
00039 /* Set non-zero for broken, compatible instructions.  Set to zero for
00040    non-broken opcodes at your peril.  gcc generates SystemV/386
00041    compatible instructions.  */
00042 #define SYSV386_COMPAT 1
00043 #endif
00044 #ifndef OLDGCC_COMPAT
00045 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
00046    generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
00047    reversed.  */
00048 #define OLDGCC_COMPAT SYSV386_COMPAT
00049 #endif
00050 
00051 #define MOV_AX_DISP32 0xa0
00052 #define POP_SEG_SHORT 0x07
00053 #define JUMP_PC_RELATIVE 0xeb
00054 #define INT_OPCODE  0xcd
00055 #define INT3_OPCODE 0xcc
00056 /* The opcode for the fwait instruction, which disassembler treats as a
00057    prefix when it can.  */
00058 #define FWAIT_OPCODE 0x9b
00059 #define ADDR_PREFIX_OPCODE 0x67
00060 #define DATA_PREFIX_OPCODE 0x66
00061 #define LOCK_PREFIX_OPCODE 0xf0
00062 #define CS_PREFIX_OPCODE 0x2e
00063 #define DS_PREFIX_OPCODE 0x3e
00064 #define ES_PREFIX_OPCODE 0x26
00065 #define FS_PREFIX_OPCODE 0x64
00066 #define GS_PREFIX_OPCODE 0x65
00067 #define SS_PREFIX_OPCODE 0x36
00068 #define REPNE_PREFIX_OPCODE 0xf2
00069 #define REPE_PREFIX_OPCODE  0xf3
00070 
00071 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
00072 #define NOP_OPCODE (char) 0x90
00073 
00074 /* register numbers */
00075 #define EBP_REG_NUM 5
00076 #define ESP_REG_NUM 4
00077 
00078 /* modrm_byte.regmem for twobyte escape */
00079 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
00080 /* index_base_byte.index for no index register addressing */
00081 #define NO_INDEX_REGISTER ESP_REG_NUM
00082 /* index_base_byte.base for no base register addressing */
00083 #define NO_BASE_REGISTER EBP_REG_NUM
00084 #define NO_BASE_REGISTER_16 6
00085 
00086 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
00087 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
00088 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
00089 
00090 /* x86-64 extension prefix.  */
00091 #define REX_OPCODE   0x40
00092 
00093 /* Indicates 64 bit operand size.  */
00094 #define REX_W 8
00095 /* High extension to reg field of modrm byte.  */
00096 #define REX_R 4
00097 /* High extension to SIB index field.  */
00098 #define REX_X 2
00099 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
00100 #define REX_B 1
00101 
00102 /* max operands per insn */
00103 #define MAX_OPERANDS 4
00104 
00105 /* max immediates per insn (lcall, ljmp, insertq, extrq) */
00106 #define MAX_IMMEDIATE_OPERANDS 2
00107 
00108 /* max memory refs per insn (string ops) */
00109 #define MAX_MEMORY_OPERANDS 2
00110 
00111 /* max size of insn mnemonics.  */
00112 #define MAX_MNEM_SIZE 16
00113 
00114 /* max size of register name in insn mnemonics.  */
00115 #define MAX_REG_NAME_SIZE 8