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cell-binutils  2.17cvs20070401
Classes | Defines | Typedefs | Enumerations
h8300.h File Reference
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Classes

struct  code
struct  arg
struct  h8_opcode

Defines

#define MS32   (SRC | L_32 | MACREG)
#define MD32   (DST | L_32 | MACREG)

Typedefs

typedef int op_type

Enumerations

enum  h8_flags {
  L_2 = 0x10, L_3 = 0x20, L_3NZ = 0x30, L_4 = 0x40,
  L_5 = 0x50, L_8 = 0x60, L_8U = 0x70, L_16 = 0x80,
  L_16U = 0x90, L_24 = 0xA0, L_32 = 0xB0, L_P = 0xC0,
  SIZE = 0xF0, REG = 0x0100, ABS = 0x0200, MEMIND = 0x0300,
  IMM = 0x0400, DISP = 0x0500, IND = 0x0600, POSTINC = 0x0700,
  POSTDEC = 0x0800, PREINC = 0x0900, PREDEC = 0x0A00, PCREL = 0x0B00,
  KBIT = 0x0C00, DBIT = 0x0D00, CONST_2 = 0x0E00, CONST_4 = 0x0F00,
  CONST_8 = 0x1000, CONST_16 = 0x1100, INDEXB = 0x1200, INDEXW = 0x1300,
  INDEXL = 0x1400, PCIDXB = 0x1500, PCIDXW = 0x1600, PCIDXL = 0x1700,
  VECIND = 0x1800, LOWREG = 0x1900, DATA = 0x2000, INC = POSTINC,
  DEC = PREDEC, CCR = 0x4000, EXR = 0x4100, MACH = 0x4200,
  MACL = 0x4300, RESERV1 = 0x4400, RESERV2 = 0x4500, VBR = 0x4600,
  SBR = 0x4700, MACREG = 0x4800, CCR_EXR = 0x4900, VBR_SBR = 0x4A00,
  CC_EX_VB_SB = 0x4B00, RESERV3 = 0x4C00, RESERV4 = 0x4D00, RESERV5 = 0x4E00,
  RESERV6 = 0x4F00, MODE = 0x7F00, CTRL = 0x4000, NO_SYMBOLS = 0x8000,
  SRC = 0x10000, DST = 0x20000, OP3 = 0x40000, MEMRELAX = 0x80000,
  DISPREG = 0x100000, IGNORE = 0x200000, ABSJMP = 0x400000, B00 = 0x800000,
  B01 = 0x1000000, B10 = 0x2000000, B11 = 0x4000000, B20 = 0x8000000,
  B21 = 0x10000000, B30 = 0x20000000, B31 = 0x40000000, E = 0x80000000,
  IMM3 = IMM | L_3, IMM4 = IMM | L_4, IMM5 = IMM | L_5, IMM3NZ = IMM | L_3NZ,
  IMM2 = IMM | L_2, IMM8 = IMM | SRC | L_8, IMM8U = IMM | SRC | L_8U, IMM16 = IMM | SRC | L_16,
  IMM16U = IMM | SRC | L_16U, IMM32 = IMM | SRC | L_32, IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, IMM4_NS = IMM4 | NO_SYMBOLS,
  IMM8U_NS = IMM8U | NO_SYMBOLS, IMM16U_NS = IMM16U | NO_SYMBOLS, RD8 = DST | L_8 | REG, RD16 = DST | L_16 | REG,
  RD32 = DST | L_32 | REG, R3_8 = OP3 | L_8 | REG, R3_16 = OP3 | L_16 | REG, R3_32 = OP3 | L_32 | REG,
  RS8 = SRC | L_8 | REG, RS16 = SRC | L_16 | REG, RS32 = SRC | L_32 | REG, RSP = SRC | L_P | REG,
  RDP = DST | L_P | REG, PCREL8 = PCREL | L_8, PCREL16 = PCREL | L_16, OP3PCREL8 = OP3 | PCREL | L_8,
  OP3PCREL16 = OP3 | PCREL | L_16, INDEXB16 = INDEXB | L_16, INDEXW16 = INDEXW | L_16, INDEXL16 = INDEXL | L_16,
  INDEXB16D = INDEXB | L_16 | DST, INDEXW16D = INDEXW | L_16 | DST, INDEXL16D = INDEXL | L_16 | DST, INDEXB32 = INDEXB | L_32,
  INDEXW32 = INDEXW | L_32, INDEXL32 = INDEXL | L_32, INDEXB32D = INDEXB | L_32 | DST, INDEXW32D = INDEXW | L_32 | DST,
  INDEXL32D = INDEXL | L_32 | DST, DISP2SRC = DISP | L_2 | SRC, DISP16SRC = DISP | L_16 | SRC, DISP32SRC = DISP | L_32 | SRC,
  DISP2DST = DISP | L_2 | DST, DISP16DST = DISP | L_16 | DST, DISP32DST = DISP | L_32 | DST, DSTDISPREG = DST | DISPREG,
  SRCDISPREG = SRC | DISPREG, ABS8SRC = SRC | ABS | L_8, ABS16SRC = SRC | ABS | L_16U, ABS24SRC = SRC | ABS | L_24,
  ABS32SRC = SRC | ABS | L_32, ABS8DST = DST | ABS | L_8, ABS16DST = DST | ABS | L_16U, ABS24DST = DST | ABS | L_24,
  ABS32DST = DST | ABS | L_32, ABS8OP3 = OP3 | ABS | L_8, ABS16OP3 = OP3 | ABS | L_16U, ABS24OP3 = OP3 | ABS | L_24,
  ABS32OP3 = OP3 | ABS | L_32, RDDEC = DST | DEC, RSINC = SRC | INC, RDINC = DST | INC,
  RSPOSTINC = SRC | POSTINC, RDPOSTINC = DST | POSTINC, RSPREINC = SRC | PREINC, RDPREINC = DST | PREINC,
  RSPOSTDEC = SRC | POSTDEC, RDPOSTDEC = DST | POSTDEC, RSPREDEC = SRC | PREDEC, RDPREDEC = DST | PREDEC,
  RSIND = SRC | IND, RDIND = DST | IND, R3_IND = OP3 | IND, OR8 = RS8,
  OR16 = RS16, OR32 = RS32
}
enum  ctrlreg {
  C_CCR = 0, C_EXR = 1, C_MACH = 2, C_MACL = 3,
  C_VBR = 6, C_SBR = 7
}
enum  { MAX_CODE_NIBBLES = 33 }
enum  h8_model { AV_H8, AV_H8H, AV_H8S, AV_H8SX }

Class Documentation

struct code

Definition at line 242 of file h8300.h.

Collaboration diagram for code:
Class Members
op_type nib
struct arg

Definition at line 247 of file h8300.h.

Collaboration diagram for arg:
Class Members
int len
const char * name
op_type nib
const char * start
int value
struct h8_opcode

Definition at line 261 of file h8300.h.

Class Members
enum h8_model int time char
*name struct
arg
int how

Define Documentation

#define MD32   (DST | L_32 | MACREG)

Definition at line 217 of file h8300.h.

#define MS32   (SRC | L_32 | MACREG)

Definition at line 216 of file h8300.h.


Typedef Documentation

typedef int op_type

Definition at line 28 of file h8300.h.


Enumeration Type Documentation

anonymous enum
Enumerator:
MAX_CODE_NIBBLES 

Definition at line 240 of file h8300.h.

enum ctrlreg
Enumerator:
C_CCR 
C_EXR 
C_MACH 
C_MACL 
C_VBR 
C_SBR 

Definition at line 230 of file h8300.h.

{
  C_CCR  = 0, 
  C_EXR  = 1, 
  C_MACH = 2, 
  C_MACL = 3, 
  C_VBR  = 6, 
  C_SBR  = 7
};
enum h8_flags
Enumerator:
L_2 
L_3 
L_3NZ 
L_4 
L_5 
L_8 
L_8U 
L_16 
L_16U 
L_24 
L_32 
L_P 
SIZE 
REG 
ABS 
MEMIND 
IMM 
DISP 
IND 
POSTINC 
POSTDEC 
PREINC 
PREDEC 
PCREL 
KBIT 
DBIT 
CONST_2 
CONST_4 
CONST_8 
CONST_16 
INDEXB 
INDEXW 
INDEXL 
PCIDXB 
PCIDXW 
PCIDXL 
VECIND 
LOWREG 
DATA 
INC 
DEC 
CCR 
EXR 
MACH 
MACL 
RESERV1 
RESERV2 
VBR 
SBR 
MACREG 
CCR_EXR 
VBR_SBR 
CC_EX_VB_SB 
RESERV3 
RESERV4 
RESERV5 
RESERV6 
MODE 
CTRL 
NO_SYMBOLS 
SRC 
DST 
OP3 
MEMRELAX 
DISPREG 
IGNORE 
ABSJMP 
B00 
B01 
B10 
B11 
B20 
B21 
B30 
B31 
E 
IMM3 
IMM4 
IMM5 
IMM3NZ 
IMM2 
IMM8 
IMM8U 
IMM16 
IMM16U 
IMM32 
IMM3NZ_NS 
IMM4_NS 
IMM8U_NS 
IMM16U_NS 
RD8 
RD16 
RD32 
R3_8 
R3_16 
R3_32 
RS8 
RS16 
RS32 
RSP 
RDP 
PCREL8 
PCREL16 
OP3PCREL8 
OP3PCREL16 
INDEXB16 
INDEXW16 
INDEXL16 
INDEXB16D 
INDEXW16D 
INDEXL16D 
INDEXB32 
INDEXW32 
INDEXL32 
INDEXB32D 
INDEXW32D 
INDEXL32D 
DISP2SRC 
DISP16SRC 
DISP32SRC 
DISP2DST 
DISP16DST 
DISP32DST 
DSTDISPREG 
SRCDISPREG 
ABS8SRC 
ABS16SRC 
ABS24SRC 
ABS32SRC 
ABS8DST 
ABS16DST 
ABS24DST 
ABS32DST 
ABS8OP3 
ABS16OP3 
ABS24OP3 
ABS32OP3 
RDDEC 
RSINC 
RDINC 
RSPOSTINC 
RDPOSTINC 
RSPREINC 
RDPREINC 
RSPOSTDEC 
RDPOSTDEC 
RSPREDEC 
RDPREDEC 
RSIND 
RDIND 
R3_IND 
OR8 
OR16 
OR32 

Definition at line 30 of file h8300.h.

{
  L_2  =      0x10,
  L_3  =      0x20,
  /* 3 bit constant, zero not accepted.  */
  L_3NZ =     0x30,
  L_4  =      0x40,
  L_5  =      0x50,
  L_8  =      0x60,
  L_8U =      0x70,
  L_16 =      0x80,
  L_16U =     0x90,
  L_24 =      0xA0,
  L_32 =      0xB0,
  L_P  =      0xC0,

  /* Mask to isolate the L_x size bits.  */
  SIZE =      0xF0,

  REG =              0x0100,
  ABS =              0x0200,
  MEMIND =    0x0300,
  IMM =              0x0400,
  DISP =      0x0500,
  IND =              0x0600,
  POSTINC =   0x0700,
  POSTDEC =   0x0800,
  PREINC =    0x0900,
  PREDEC =    0x0A00,
  PCREL =     0x0B00,
  KBIT =      0x0C00,
  DBIT =      0x0D00,
  CONST_2 =     0x0E00,
  CONST_4 =     0x0F00,
  CONST_8 =     0x1000,
  CONST_16 =    0x1100,
  INDEXB =      0x1200,
  INDEXW =      0x1300,
  INDEXL =      0x1400,
  PCIDXB =      0x1500,
  PCIDXW =      0x1600,
  PCIDXL =      0x1700,
  VECIND =      0x1800,
  LOWREG =      0x1900,
  DATA   =      0x2000,

  /* Synonyms.  */
  INC =              POSTINC,
  DEC =              PREDEC,
  /* Control Registers.  */
  CCR =              0x4000,
  EXR =              0x4100,
  MACH =      0x4200,
  MACL =      0x4300,
  RESERV1 =   0x4400,
  RESERV2 =   0x4500,
  VBR =       0x4600,
  SBR =       0x4700,
  MACREG =    0x4800,
  CCR_EXR =   0x4900,
  VBR_SBR =   0x4A00,
  CC_EX_VB_SB =      0x4B00,
  RESERV3 =   0x4C00,
  RESERV4 =   0x4D00,
  RESERV5 =   0x4E00,
  RESERV6 =   0x4F00,

  /* Mask to isolate the addressing mode bits (REG .. PREDEC).  */
  MODE =      0x7F00,

  CTRL =      0x4000,

  NO_SYMBOLS =  0x8000,
  SRC =              0x10000,
  DST =              0x20000,
  OP3 =              0x40000,
  MEMRELAX =  0x80000,             /* Move insn which may relax.  */

  DISPREG =   0x100000,
  IGNORE =    0x200000,
  ABSJMP =    0x400000,

  B00 =         0x800000,          /* Bit 0 must be low.   */
  B01 =         0x1000000,         /* Bit 0 must be high.  */
  B10 =       0x2000000,           /* Bit 1 must be low.   */
  B11 =       0x4000000,           /* Bit 1 must be high.  */
  B20 =       0x8000000,           /* Bit 2 must be low.   */
  B21 =       0x10000000,          /* Bit 2 must be high.  */
  B30 =              0x20000000,          /* Bit 3 must be low.   */
  B31 =              0x40000000,          /* Bit 3 must be high.  */
  E =                0x80000000,          /* End of nibble sequence.  */

  /* Immediates smaller than 8 bits are always unsigned.  */
  IMM3 =      IMM | L_3,
  IMM4 =      IMM | L_4,
  IMM5 =      IMM | L_5,
  IMM3NZ =    IMM | L_3NZ,
  IMM2 =      IMM | L_2,

  IMM8 =      IMM | SRC | L_8,
  IMM8U =     IMM | SRC | L_8U,
  IMM16 =     IMM | SRC | L_16,
  IMM16U =    IMM | SRC | L_16U,
  IMM32 =     IMM | SRC | L_32,

  IMM3NZ_NS =   IMM3NZ | NO_SYMBOLS,
  IMM4_NS =   IMM4 | NO_SYMBOLS,
  IMM8U_NS =  IMM8U | NO_SYMBOLS,
  IMM16U_NS =   IMM16U | NO_SYMBOLS,

  RD8  =      DST | L_8  | REG,
  RD16 =      DST | L_16 | REG,
  RD32 =      DST | L_32 | REG,
  R3_8  =       OP3 | L_8  | REG,
  R3_16 =       OP3 | L_16 | REG,
  R3_32 =       OP3 | L_32 | REG,
  RS8  =      SRC | L_8  | REG,
  RS16 =      SRC | L_16 | REG,
  RS32 =      SRC | L_32 | REG,

  RSP =              SRC | L_P | REG,
  RDP =              DST | L_P | REG,

  PCREL8 =    PCREL | L_8,
  PCREL16 =   PCREL | L_16,

  OP3PCREL8 = OP3 | PCREL | L_8,
  OP3PCREL16 =       OP3 | PCREL | L_16,

  INDEXB16  = INDEXB | L_16,
  INDEXW16  = INDEXW | L_16,
  INDEXL16  = INDEXL | L_16,
  INDEXB16D = INDEXB | L_16 | DST,
  INDEXW16D = INDEXW | L_16 | DST,
  INDEXL16D = INDEXL | L_16 | DST,

  INDEXB32  = INDEXB | L_32,
  INDEXW32  = INDEXW | L_32,
  INDEXL32  = INDEXL | L_32,
  INDEXB32D = INDEXB | L_32 | DST,
  INDEXW32D = INDEXW | L_32 | DST,
  INDEXL32D = INDEXL | L_32 | DST,

  DISP2SRC =  DISP | L_2  | SRC,
  DISP16SRC = DISP | L_16 | SRC,
  DISP32SRC = DISP | L_32 | SRC,

  DISP2DST =  DISP | L_2  | DST,
  DISP16DST = DISP | L_16 | DST,
  DISP32DST = DISP | L_32 | DST,

  DSTDISPREG =  DST | DISPREG,
  SRCDISPREG =  SRC | DISPREG,

  ABS8SRC  =  SRC | ABS | L_8,
  ABS16SRC =  SRC | ABS | L_16U,
  ABS24SRC =  SRC | ABS | L_24,
  ABS32SRC =  SRC | ABS | L_32,

  ABS8DST  =  DST | ABS | L_8,
  ABS16DST =  DST | ABS | L_16U,
  ABS24DST =  DST | ABS | L_24,
  ABS32DST =  DST | ABS | L_32,

  ABS8OP3  =  OP3 | ABS | L_8,
  ABS16OP3 =  OP3 | ABS | L_16U,
  ABS24OP3 =  OP3 | ABS | L_24,
  ABS32OP3 =  OP3 | ABS | L_32,

  RDDEC =     DST | DEC,
  RSINC =     SRC | INC,
  RDINC =     DST | INC,

  RSPOSTINC = SRC | POSTINC,
  RDPOSTINC = DST | POSTINC,
  RSPREINC =  SRC | PREINC,
  RDPREINC =  DST | PREINC,
  RSPOSTDEC = SRC | POSTDEC,
  RDPOSTDEC = DST | POSTDEC,
  RSPREDEC =  SRC | PREDEC,
  RDPREDEC =  DST | PREDEC,

  RSIND =     SRC | IND,
  RDIND =     DST | IND,
  R3_IND =    OP3 | IND,

#define MS32  (SRC | L_32 | MACREG)
#define MD32  (DST | L_32 | MACREG)

#if 1
  OR8  =      RS8,          /* ??? OR as in One Register.  */
  OR16 =      RS16,
  OR32 =      RS32,
#else
  OR8  =      RD8,
  OR16 =      RD16,
  OR32 =      RD32
#endif
};
enum h8_model
Enumerator:
AV_H8 
AV_H8H 
AV_H8S 
AV_H8SX 

Definition at line 253 of file h8300.h.