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cell-binutils  2.17cvs20070401
dlx.h
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00001 /* Table of opcodes for the DLX microprocess.
00002    Copyright 2002 Free Software Foundation, Inc.
00003 
00004    This file is part of GDB and GAS.
00005 
00006    This program is free software; you can redistribute it and/or modify
00007    it under the terms of the GNU General Public License as published by
00008    the Free Software Foundation; either version 2 of the License, or
00009    (at your option) any later version.
00010 
00011    This program is distributed in the hope that it will be useful,
00012    but WITHOUT ANY WARRANTY; without even the implied warranty of
00013    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00014    GNU General Public License for more details.
00015 
00016    You should have received a copy of the GNU General Public License
00017    along with this program; if not, write to the Free Software
00018    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00019 
00020    Initially created by Kuang Hwa Lin, 2002.   */
00021 
00022 /* Following are the function codes for the Special OP (ALU).  */
00023 #define  ALUOP       0x00000000
00024 #define  SPECIALOP   0x00000000
00025 
00026 #define  NOPF        0x00000000
00027 #define  SLLF        0x00000004
00028 #define  SRLF        0x00000006
00029 #define  SRAF        0x00000007
00030 
00031 #define  SEQUF       0x00000010
00032 #define  SNEUF       0x00000011
00033 #define  SLTUF       0x00000012
00034 #define  SGTUF       0x00000013
00035 #define  SLEUF       0x00000014
00036 #define  SGEUF       0x00000015
00037 
00038 #define  ADDF        0x00000020
00039 #define  ADDUF       0x00000021
00040 #define  SUBF        0x00000022
00041 #define  SUBUF       0x00000023
00042 #define  ANDF        0x00000024
00043 #define  ORF         0x00000025
00044 #define  XORF        0x00000026
00045 
00046 #define  SEQF        0x00000028
00047 #define  SNEF        0x00000029
00048 #define  SLTF        0x0000002A
00049 #define  SGTF        0x0000002B
00050 #define  SLEF        0x0000002C
00051 #define  SGEF        0x0000002D
00052   /* Following special functions was not mentioned in the
00053      Hennessy's book but was implemented in the RTL.  */
00054 #define  MVTSF            0x00000030
00055 #define  MVFSF       0x00000031
00056 #define  BSWAPF      0x00000032
00057 #define  LUTF        0x00000033
00058 /* Following special functions was mentioned in the
00059    Hennessy's book but was not implemented in the RTL.  */
00060 #define  MULTF       0x00000005
00061 #define  MULTUF      0x00000006
00062 #define  DIVF        0x00000007
00063 #define  DIVUF       0x00000008
00064 
00065 
00066 /* Following are the rest of the OPcodes:
00067    JOP    = (0x002 << 26), JALOP  = (0x003 << 26), BEQOP = (0x004 << 26),   BNEOP  = (0x005 << 26)
00068    ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP      = (0x00A << 26), SUBUIOP= (0x00B << 26)
00069    ANDIOP = (0x00C << 26), ORIOP  = (0x00D << 26), XORIOP = (0x00E << 26),  LHIOP  = (0x00F << 26)
00070    RFEOP  = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26)
00071    BREAKOP= (0x014 << 26)
00072    SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26),  SGTIOP = (0x01B << 26)
00073    SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26)
00074    LBOP   = (0x020 << 26), LHOP   = (0x021 << 26), LWOP   = (0x023 << 26),  LBUOP  = (0x024 << 26)
00075    LHUOP  = (0x025 << 26), SBOP   = (0x028 << 26), SHOP   = (0x029 << 26),  SWOP   = (0x02B << 26)
00076    LSBUOP = (0x026 << 26), LSHU   = (0x027 << 26), LSW    = (0x02C << 26),
00077    SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26),  SGTUIOP= (0x033 << 26)
00078    SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26)
00079    SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26).  */
00080 #define  JOP       0x08000000
00081 #define  JALOP            0x0c000000
00082 #define  BEQOP            0x10000000
00083 #define  BNEOP            0x14000000
00084 
00085 #define  ADDIOP           0x20000000
00086 #define  ADDUIOP     0x24000000
00087 #define  SUBIOP           0x28000000
00088 #define  SUBUIOP     0x2c000000
00089 #define  ANDIOP      0x30000000
00090 #define  ORIOP       0x34000000
00091 #define  XORIOP      0x38000000
00092 #define  LHIOP       0x3c000000
00093 #define  RFEOP            0x40000000
00094 #define  TRAPOP      0x44000000
00095 #define  JROP      0x48000000
00096 #define  JALROP      0x4c000000
00097 #define  BREAKOP     0x50000000
00098 
00099 #define  SEQIOP      0x60000000
00100 #define  SNEIOP      0x64000000
00101 #define  SLTIOP      0x68000000
00102 #define  SGTIOP      0x6c000000
00103 #define  SLEIOP      0x70000000
00104 #define  SGEIOP      0x74000000
00105 
00106 #define  LBOP        0x80000000
00107 #define  LHOP        0x84000000
00108 #define  LWOP        0x8c000000
00109 #define  LBUOP       0x90000000
00110 #define  LHUOP            0x94000000
00111 #define  LDSTBU
00112 #define  LDSTHU
00113 #define  SBOP      0xa0000000
00114 #define  SHOP        0xa4000000
00115 #define  SWOP        0xac000000
00116 #define  LDST
00117 
00118 #define  SEQUIOP     0xc0000000
00119 #define  SNEUIOP     0xc4000000
00120 #define  SLTUIOP     0xc8000000
00121 #define  SGTUIOP     0xcc000000
00122 #define  SLEUIOP     0xd0000000
00123 #define  SGEUIOP     0xd4000000
00124 
00125 #define  SLLIOP      0xd8000000
00126 #define  SRLIOP      0xdc000000
00127 #define  SRAIOP      0xe0000000
00128 
00129 /* Following 3 ops was added to provide the MP atonmic operation.  */
00130 #define  LSBUOP      0x98000000
00131 #define  LSHUOP      0x9c000000
00132 #define  LSWOP       0xb0000000
00133 
00134 /* Following opcode was defined in the Hennessy's book as
00135    "normal" opcode but was implemented in the RTL as special
00136    functions.  */
00137 #if 0
00138 #define  MVTSOP           0x50000000
00139 #define  MVFSOP      0x54000000
00140 #endif
00141 
00142 struct dlx_opcode
00143 {
00144   /* Name of the instruction.  */
00145   char *name;
00146 
00147   /* Opcode word.  */
00148   unsigned long opcode;
00149 
00150   /* A string of characters which describe the operands.
00151      Valid characters are:
00152      ,        Itself.  The character appears in the assembly code.
00153      a        rs1      The register number is in bits 21-25 of the instruction.
00154      b        rs2/rd   The register number is in bits 16-20 of the instruction.
00155      c        rd.      The register number is in bits 11-15 of the instruction.
00156      f        FUNC bits 0-10 of the instruction.
00157      i        An immediate operand is in bits 0-16 of the instruction. 0 extended
00158      I        An immediate operand is in bits 0-16 of the instruction. sign extended
00159      d       An 16 bit PC relative displacement.
00160      D       An immediate operand is in bits 0-25 of the instruction.
00161      N       No opperands needed, for nops.
00162      P       it can be a register or a 16 bit operand.  */
00163   char *args;
00164 };
00165 
00166 static const struct dlx_opcode dlx_opcodes[] =
00167   {
00168   /* Arithmetic and Logic R-TYPE instructions.  */
00169     { "nop",      (ALUOP|NOPF),   "N"     },  /* NOP                          */
00170     { "add",      (ALUOP|ADDF),   "c,a,b" },  /* Add                          */
00171     { "addu",     (ALUOP|ADDUF),  "c,a,b" },  /* Add Unsigned                 */
00172     { "sub",      (ALUOP|SUBF),   "c,a,b" },  /* SUB                          */
00173     { "subu",     (ALUOP|SUBUF),  "c,a,b" },  /* Sub Unsigned                 */
00174     { "mult",     (ALUOP|MULTF),  "c,a,b" },  /* MULTIPLY                     */
00175     { "multu",    (ALUOP|MULTUF), "c,a,b" },  /* MULTIPLY Unsigned            */
00176     { "div",      (ALUOP|DIVF),   "c,a,b" },  /* DIVIDE                       */
00177     { "divu",     (ALUOP|DIVUF),  "c,a,b" },  /* DIVIDE Unsigned              */
00178     { "and",      (ALUOP|ANDF),   "c,a,b" },  /* AND                          */
00179     { "or",       (ALUOP|ORF),    "c,a,b" },  /* OR                           */
00180     { "xor",      (ALUOP|XORF),   "c,a,b" },  /* Exclusive OR                 */
00181     { "sll",      (ALUOP|SLLF),   "c,a,b" },  /* SHIFT LEFT LOGICAL           */
00182     { "sra",      (ALUOP|SRAF),   "c,a,b" },  /* SHIFT RIGHT ARITHMETIC       */
00183     { "srl",      (ALUOP|SRLF),   "c,a,b" },  /* SHIFT RIGHT LOGICAL          */
00184     { "seq",      (ALUOP|SEQF),   "c,a,b" },  /* Set if equal                 */
00185     { "sne",      (ALUOP|SNEF),   "c,a,b" },  /* Set if not equal             */
00186     { "slt",      (ALUOP|SLTF),   "c,a,b" },  /* Set if less                  */
00187     { "sgt",      (ALUOP|SGTF),   "c,a,b" },  /* Set if greater               */
00188     { "sle",      (ALUOP|SLEF),   "c,a,b" },  /* Set if less or equal         */
00189     { "sge",      (ALUOP|SGEF),   "c,a,b" },  /* Set if greater or equal      */
00190     { "sequ",     (ALUOP|SEQUF),  "c,a,b" },  /* Set if equal unsigned        */
00191     { "sneu",     (ALUOP|SNEUF),  "c,a,b" },  /* Set if not equal unsigned    */
00192     { "sltu",     (ALUOP|SLTUF),  "c,a,b" },  /* Set if less unsigned         */
00193     { "sgtu",     (ALUOP|SGTUF),  "c,a,b" },  /* Set if greater unsigned      */
00194     { "sleu",     (ALUOP|SLEUF),  "c,a,b" },  /* Set if less or equal unsigned*/
00195     { "sgeu",     (ALUOP|SGEUF),  "c,a,b" },  /* Set if greater or equal      */
00196     { "mvts",     (ALUOP|MVTSF),  "c,a"   },  /* Move to special register     */
00197     { "mvfs",     (ALUOP|MVFSF),  "c,a"   },  /* Move from special register   */
00198     { "bswap",    (ALUOP|BSWAPF), "c,a,b" },  /* ??? Was not documented       */
00199     { "lut",      (ALUOP|LUTF),   "c,a,b" },  /* ????? same as above          */
00200 
00201     /* Arithmetic and Logical Immediate I-TYPE instructions.  */
00202     { "addi",     ADDIOP,         "b,a,I" },  /* Add Immediate                */
00203     { "addui",    ADDUIOP,        "b,a,i" },  /* Add Usigned Immediate        */
00204     { "subi",     SUBIOP,         "b,a,I" },  /* Sub Immediate                */
00205     { "subui",    SUBUIOP,        "b,a,i" },  /* Sub Unsigned Immedated       */
00206     { "andi",     ANDIOP,         "b,a,i" },  /* AND Immediate                */
00207     { "ori",      ORIOP,          "b,a,i" },  /* OR  Immediate                */
00208     { "xori",     XORIOP,         "b,a,i" },  /* Exclusive OR  Immediate      */
00209     { "slli",     SLLIOP,         "b,a,i" },  /* SHIFT LEFT LOCICAL Immediate */
00210     { "srai",     SRAIOP,         "b,a,i" },  /* SHIFT RIGHT ARITH. Immediate */
00211     { "srli",     SRLIOP,         "b,a,i" },  /* SHIFT RIGHT LOGICAL Immediate*/
00212     { "seqi",     SEQIOP,         "b,a,i" },  /* Set if equal                 */
00213     { "snei",     SNEIOP,         "b,a,i" },  /* Set if not equal             */
00214     { "slti",     SLTIOP,         "b,a,i" },  /* Set if less                  */
00215     { "sgti",     SGTIOP,         "b,a,i" },  /* Set if greater               */
00216     { "slei",     SLEIOP,         "b,a,i" },  /* Set if less or equal         */
00217     { "sgei",     SGEIOP,         "b,a,i" },  /* Set if greater or equal      */
00218     { "sequi",    SEQUIOP,        "b,a,i" },  /* Set if equal                 */
00219     { "sneui",    SNEUIOP,        "b,a,i" },  /* Set if not equal             */
00220     { "sltui",    SLTUIOP,        "b,a,i" },  /* Set if less                  */
00221     { "sgtui",    SGTUIOP,        "b,a,i" },  /* Set if greater               */
00222     { "sleui",    SLEUIOP,        "b,a,i" },  /* Set if less or equal         */
00223     { "sgeui",    SGEUIOP,        "b,a,i" },  /* Set if greater or equal      */
00224     /* Macros for I type instructions.  */
00225     { "mov",      ADDIOP,         "b,P"   },  /* a move macro                 */
00226     { "movu",     ADDUIOP,        "b,P"   },  /* a move macro, unsigned       */
00227 
00228 #if 0
00229     /* Move special.  */
00230     { "mvts",     MVTSOP,         "b,a"   },  /* Move From Integer to Special */
00231     { "mvfs",     MVFSOP,         "b,a"   },  /* Move From Special to Integer */
00232 #endif
00233 
00234     /* Load high Immediate I-TYPE instruction.  */
00235     { "lhi",      LHIOP,          "b,i"   },  /* Load High Immediate          */
00236     { "lui",      LHIOP,          "b,i"   },  /* Load High Immediate          */
00237     { "sethi",    LHIOP,          "b,i"   },  /* Load High Immediate          */
00238 
00239   /* LOAD/STORE BYTE 8 bits I-TYPE.  */
00240     { "lb",       LBOP,           "b,a,I" },  /* Load Byte                    */
00241     { "lbu",      LBUOP,          "b,a,I" },  /* Load Byte Unsigned           */
00242     { "ldstbu",   LSBUOP,         "b,a,I" },  /* Load store Byte Unsigned     */
00243     { "sb",       SBOP,           "b,a,I" },  /* Store Byte                   */
00244 
00245     /* LOAD/STORE HALFWORD 16 bits.  */
00246     { "lh",       LHOP,           "b,a,I" },  /* Load Halfword                */
00247     { "lhu",      LHUOP,          "b,a,I" },  /* Load Halfword Unsigned       */
00248     { "ldsthu",   LSHUOP,         "b,a,I" },  /* Load Store Halfword Unsigned */
00249     { "sh",       SHOP,           "b,a,I" },  /* Store Halfword               */
00250 
00251   /* LOAD/STORE WORD 32 bits.  */
00252     { "lw",       LWOP,           "b,a,I" },  /* Load Word                    */
00253     { "sw",       SWOP,           "b,a,I" },  /* Store Word                   */
00254     { "ldstw",    LSWOP,          "b,a,I" },  /* Load Store Word              */
00255 
00256   /* Branch PC-relative, 16 bits offset.  */
00257     { "beqz",     BEQOP,          "a,d" },    /* Branch if a == 0             */
00258     { "bnez",     BNEOP,          "a,d" },    /* Branch if a != 0             */
00259     { "beq",      BEQOP,          "a,d" },    /* Branch if a == 0             */
00260     { "bne",      BNEOP,          "a,d" },    /* Branch if a != 0             */
00261 
00262     /* Jumps Trap and RFE J-TYPE.  */
00263     { "j",        JOP,            "D" },      /* Jump, PC-relative 26 bits    */
00264     { "jal",      JALOP,          "D" },      /* JAL, PC-relative 26 bits     */
00265     { "break",    BREAKOP,        "D" },      /* break to OS                  */
00266     { "trap" ,    TRAPOP,         "D" },      /* TRAP to OS                   */
00267     { "rfe",      RFEOP,          "N" },      /* Return From Exception        */
00268     /* Macros.  */
00269     { "call",     JOP,            "D" },      /* Jump, PC-relative 26 bits    */
00270 
00271     /* Jumps Trap and RFE I-TYPE.  */
00272     { "jr",       JROP,           "a" },      /* Jump Register, Abs (32 bits) */
00273     { "jalr",     JALROP,         "a" },      /* JALR, Abs (32 bits)          */
00274     /* Macros.  */
00275     { "retr",     JROP,           "a" },      /* Jump Register, Abs (32 bits) */
00276 
00277     { "", 0x0, "" }         /* Dummy entry, not included in NUM_OPCODES.
00278                                This lets code examine entry i + 1 without
00279                                checking if we've run off the end of the table.  */
00280   };
00281 
00282 const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1);