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cell-binutils  2.17cvs20070401
d30v.h
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00001 /* d30v.h -- Header file for D30V opcode table
00002    Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
00003    Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
00004 
00005 This file is part of GDB, GAS, and the GNU binutils.
00006 
00007 GDB, GAS, and the GNU binutils are free software; you can redistribute
00008 them and/or modify them under the terms of the GNU General Public
00009 License as published by the Free Software Foundation; either version
00010 1, or (at your option) any later version.
00011 
00012 GDB, GAS, and the GNU binutils are distributed in the hope that they
00013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015 the GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this file; see the file COPYING.  If not, write to the Free
00019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 #ifndef D30V_H
00022 #define D30V_H
00023 
00024 #define NOP 0x00F00000
00025 
00026 /* Structure to hold information about predefined registers.  */
00027 struct pd_reg
00028 {
00029   char *name;        /* name to recognize */
00030   char *pname;              /* name to print for this register */
00031   int value;
00032 };
00033 
00034 extern const struct pd_reg pre_defined_registers[];
00035 int reg_name_cnt (void);
00036 
00037 /* the number of control registers */
00038 #define MAX_CONTROL_REG     64
00039 
00040 /* define the format specifiers */
00041 #define FM00  0
00042 #define FM01  0x80000000
00043 #define FM10  0x8000000000000000LL
00044 #define FM11  0x8000000080000000LL
00045 
00046 /* define the opcode classes */
00047 #define BRA   0
00048 #define LOGIC 1
00049 #define IMEM  2
00050 #define IALU1 4
00051 #define IALU2 5
00052 
00053 /* define the execution condition codes */
00054 #define ECC_AL       0      /* ALways (default) */
00055 #define ECC_TX       1      /* F0=True, F1=Don't care */
00056 #define ECC_FX       2      /* F0=False, F1=Don't care */
00057 #define ECC_XT       3      /* F0=Don't care, F1=True */
00058 #define ECC_XF       4      /* F0=Don't care, F1=False */
00059 #define ECC_TT       5      /* F0=True, F1=True */
00060 #define ECC_TF       6      /* F0=True, F1=False */
00061 #define ECC_RESERVED 7      /* reserved */
00062 #define ECC_MAX      ECC_RESERVED
00063 
00064 extern const char *d30v_ecc_names[];
00065 
00066 /* condition code table for CMP and CMPU */
00067 extern const char *d30v_cc_names[];
00068 
00069 /* The opcode table is an array of struct d30v_opcode.  */
00070 struct d30v_opcode
00071 {
00072   /* The opcode name.  */
00073   const char *name;
00074 
00075   /* the opcode */
00076   int op1;    /* first part, "IALU1" for example */
00077   int op2;    /* the rest of the opcode */
00078 
00079   /* opcode format(s).  These numbers correspond to entries */
00080   /* in the d30v_format_table */
00081   unsigned char format[4];
00082 
00083 #define SHORT_M             1
00084 #define SHORT_M2     5      /* for ld2w and st2w */
00085 #define SHORT_A             9
00086 #define SHORT_B1     11
00087 #define SHORT_B2     12
00088 #define SHORT_B2r     13
00089 #define SHORT_B3      14
00090 #define SHORT_B3r     16
00091 #define SHORT_B3b     18
00092 #define SHORT_B3br    20
00093 #define SHORT_D1r     22
00094 #define SHORT_D2      24
00095 #define SHORT_D2r     26
00096 #define SHORT_D2Br    28
00097 #define SHORT_U       30      /* unary SHORT_A.  ABS for example */
00098 #define SHORT_F       31      /* SHORT_A with flag registers */
00099 #define SHORT_AF      33      /* SHORT_A with only the first register a flag register */
00100 #define SHORT_T       35      /* for trap instruction */
00101 #define SHORT_A5      36      /* SHORT_A with a 5-bit immediate instead of 6 */
00102 #define SHORT_CMP     38      /* special form for CMPcc */
00103 #define SHORT_CMPU    40      /* special form for CMPUcc */
00104 #define SHORT_A1      42      /* special form of SHORT_A for MACa opcodes where a=1 */
00105 #define SHORT_AA      44      /* SHORT_A with the first register an accumulator */
00106 #define SHORT_RA      46      /* SHORT_A with the second register an accumulator */
00107 #define SHORT_MODINC  48      
00108 #define SHORT_MODDEC  49
00109 #define SHORT_C1      50
00110 #define SHORT_C2      51
00111 #define SHORT_UF      52
00112 #define SHORT_A2      53
00113 #define SHORT_NONE    55      /* no operands */
00114 #define SHORT_AR      56      /* like SHORT_AA but only accept register as third parameter  */
00115 #define LONG          57
00116 #define LONG_U        58      /* unary LONG */
00117 #define LONG_Ur       59      /* LONG pc-relative */
00118 #define LONG_CMP      60      /* special form for CMPcc and CMPUcc */
00119 #define LONG_M        61      /* Memory long for ldb, stb */
00120 #define LONG_M2       62      /* Memory long for ld2w, st2w */
00121 #define LONG_2        63      /* LONG with 2 operands; jmptnz */
00122 #define LONG_2r       64      /* LONG with 2 operands; bratnz */
00123 #define LONG_2b       65      /* LONG_2 with modifier of 3 */
00124 #define LONG_2br      66      /* LONG_2r with modifier of 3 */
00125 #define LONG_D        67      /* for DJMPI */
00126 #define LONG_Dr       68      /* for DBRAI */
00127 #define LONG_Dbr      69      /* for repeati */
00128 
00129   /* the execution unit(s) used */
00130   int unit;
00131 #define EITHER       0
00132 #define IU    1
00133 #define MU    2
00134 #define EITHER_BUT_PREFER_MU 3
00135 
00136   /* this field is used to decide if two instructions */
00137   /* can be executed in parallel */
00138   long flags_used;
00139   long flags_set;
00140 #define FLAG_0              (1L<<0)
00141 #define FLAG_1              (1L<<1)
00142 #define FLAG_2              (1L<<2)
00143 #define FLAG_3              (1L<<3)
00144 #define FLAG_4              (1L<<4)              /* S (saturation) */
00145 #define FLAG_5              (1L<<5)              /* V (overflow) */
00146 #define FLAG_6              (1L<<6)              /* VA (accumulated overflow) */
00147 #define FLAG_7              (1L<<7)              /* C (carry/borrow) */
00148 #define FLAG_SM             (1L<<8)              /* SM (stack mode) */
00149 #define FLAG_RP             (1L<<9)              /* RP (repeat enable) */
00150 #define FLAG_CONTROL (1L<<10)      /* control registers */
00151 #define FLAG_A0             (1L<<11)      /* A0 */
00152 #define FLAG_A1             (1L<<12)      /* A1 */
00153 #define FLAG_JMP     (1L<<13)      /* instruction is a branch */
00154 #define FLAG_JSR     (1L<<14)      /* subroutine call.  must be aligned */
00155 #define FLAG_MEM     (1L<<15)      /* reads/writes memory */
00156 #define FLAG_NOT_WITH_ADDSUBppp     (1L<<16) /* Old meaning: a 2 word 4 byter operation
00157                                       New meaning: operation cannot be 
00158                                       combined in parallel with ADD/SUBppp. */
00159 #define FLAG_MUL16   (1L<<17)      /* 16 bit multiply */
00160 #define FLAG_MUL32   (1L<<18)      /* 32 bit multiply */
00161 #define FLAG_ADDSUBppp      (1L<<19)      /* ADDppp or SUBppp */
00162 #define FLAG_DELAY   (1L<<20)      /* This is a delayed branch or jump */
00163 #define FLAG_LKR     (1L<<21)      /* insn in left slot kills right slot */
00164 #define FLAG_CVVA    (FLAG_5|FLAG_6|FLAG_7)
00165 #define FLAG_C              FLAG_7
00166 #define FLAG_ALL     (FLAG_0 | \
00167                       FLAG_1 | \
00168                       FLAG_2 | \
00169                       FLAG_3 | \
00170                       FLAG_4 | \
00171                       FLAG_5 | \
00172                       FLAG_6 | \
00173                       FLAG_7 | \
00174                       FLAG_SM | \
00175                       FLAG_RP | \
00176                       FLAG_CONTROL)
00177 
00178   int reloc_flag;
00179 #define RELOC_PCREL  1
00180 #define RELOC_ABS    2
00181 };
00182 
00183 extern const struct d30v_opcode d30v_opcode_table[];
00184 extern const int d30v_num_opcodes;
00185 
00186 /* The operands table is an array of struct d30v_operand.  */
00187 struct d30v_operand
00188 {
00189   /* the length of the field */
00190   int length;
00191 
00192   /* The number of significant bits in the operand.  */
00193   int bits;
00194 
00195   /* position relative to Ra */
00196   int position;
00197 
00198   /* syntax flags.  */
00199   long flags;
00200 };
00201 extern const struct d30v_operand d30v_operand_table[];
00202 
00203 /* Values defined for the flags field of a struct d30v_operand.  */
00204 
00205 /* this is the destination register; it will be modified */
00206 /* this is used by the optimizer */
00207 #define OPERAND_DEST (1)
00208 
00209 /* number or symbol */
00210 #define OPERAND_NUM  (2)
00211 
00212 /* address or label */
00213 #define OPERAND_ADDR (4)
00214 
00215 /* register */
00216 #define OPERAND_REG  (8)
00217 
00218 /* postincrement +  */
00219 #define OPERAND_PLUS (0x10)
00220 
00221 /* postdecrement -  */
00222 #define OPERAND_MINUS       (0x20)
00223 
00224 /* signed number */
00225 #define OPERAND_SIGNED      (0x40)
00226 
00227 /* this operand must be shifted left by 3 */
00228 #define OPERAND_SHIFT       (0x80)
00229 
00230 /* flag register */
00231 #define OPERAND_FLAG (0x100)
00232 
00233 /* control register  */
00234 #define OPERAND_CONTROL     (0x200)
00235 
00236 /* accumulator */
00237 #define OPERAND_ACC  (0x400)
00238 
00239 /* @  */
00240 #define OPERAND_ATSIGN      (0x800)
00241 
00242 /* @(  */
00243 #define OPERAND_ATPAR       (0x1000)
00244 
00245 /* predecrement mode '@-sp'  */
00246 #define OPERAND_ATMINUS     (0x2000)
00247 
00248 /* this operand changes the instruction name */
00249 /* for example, CPMcc, CMPUcc */
00250 #define OPERAND_NAME (0x4000)
00251 
00252 /* fake operand for mvtsys and mvfsys */
00253 #define OPERAND_SPECIAL     (0x8000)
00254 
00255 /* let the optimizer know that two registers are affected */
00256 #define OPERAND_2REG (0x10000)
00257 
00258 /* This operand is pc-relative.  Note that repeati can have two immediate
00259    operands, one of which is pcrel, the other (the IMM6U one) is not.  */
00260 #define OPERAND_PCREL       (0x20000)
00261 
00262 /* The format table is an array of struct d30v_format.  */
00263 struct d30v_format
00264 {
00265   int  form;         /* SHORT_A, LONG, etc */
00266   int  modifier;     /* two bit modifier following opcode */
00267   unsigned char operands[5];
00268 };
00269 extern const struct d30v_format d30v_format_table[];
00270 
00271 
00272 /* an instruction is defined by an opcode and a format */
00273 /* for example, "add" has one opcode, but three different */
00274 /* formats, 2 SHORT_A forms and a LONG form. */
00275 struct d30v_insn
00276 {
00277   struct d30v_opcode *op;   /* pointer to an entry in the opcode table */
00278   struct d30v_format *form; /* pointer to an entry in the format table */
00279   int ecc;                  /* execution condition code */
00280 };
00281 
00282 /* an expressionS only has one register type, so we fake it */
00283 /* by setting high bits to indicate type */
00284 #define REGISTER_MASK       0xFF
00285 
00286 #endif /* D30V_H */