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cell-binutils  2.17cvs20070401
d10v.h
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00001 /* d10v.h -- Header file for D10V opcode table
00002    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
00003    Free Software Foundation, Inc.
00004    Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
00005 
00006 This file is part of GDB, GAS, and the GNU binutils.
00007 
00008 GDB, GAS, and the GNU binutils are free software; you can redistribute
00009 them and/or modify them under the terms of the GNU General Public
00010 License as published by the Free Software Foundation; either version
00011 1, or (at your option) any later version.
00012 
00013 GDB, GAS, and the GNU binutils are distributed in the hope that they
00014 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016 the GNU General Public License for more details.
00017 
00018 You should have received a copy of the GNU General Public License
00019 along with this file; see the file COPYING.  If not, write to the Free
00020 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00021 
00022 #ifndef D10V_H
00023 #define D10V_H
00024 
00025 /* Format Specifier */
00026 #define FM00  0
00027 #define FM01  0x40000000
00028 #define FM10  0x80000000
00029 #define FM11  0xC0000000
00030 
00031 #define NOP 0x5e00
00032 #define OPCODE_DIVS  0x14002800
00033 
00034 /* The opcode table is an array of struct d10v_opcode.  */
00035 
00036 struct d10v_opcode
00037 {
00038   /* The opcode name.  */
00039   const char *name;
00040 
00041   /* the opcode format */
00042   int format;
00043 
00044   /* These numbers were picked so we can do if( i & SHORT_OPCODE) */
00045 #define SHORT_OPCODE 1
00046 #define LONG_OPCODE  8
00047 #define SHORT_2           1        /* short with 2 operands */
00048 #define SHORT_B           3        /* short with 8-bit branch */
00049 #define LONG_B            8        /* long with 16-bit branch */
00050 #define LONG_L       10            /* long with 3 operands */
00051 #define LONG_R       12            /* reserved */
00052 
00053   /* just a placeholder for variable-length instructions */
00054   /* for example, "bra" will be a fake for "bra.s" and bra.l" */
00055   /* which will immediately follow in the opcode table.  */
00056 #define OPCODE_FAKE  32
00057 
00058   /* the number of cycles */
00059   int cycles;
00060 
00061   /* the execution unit(s) used */
00062   int unit;
00063 #define EITHER       0
00064 #define IU    1
00065 #define MU    2
00066 #define BOTH  3
00067 
00068   /* execution type; parallel or sequential */
00069   /* this field is used to decide if two instructions */
00070   /* can be executed in parallel */
00071   int exec_type;
00072 #define PARONLY 1    /* parallel only */
00073 #define SEQ   2      /* must be sequential */
00074 #define PAR   4      /* may be parallel */
00075 #define BRANCH_LINK 8       /* subroutine call.  must be aligned */
00076 #define RMEM     16  /* reads memory */
00077 #define WMEM     32  /* writes memory */
00078 #define RF0      64  /* reads f0 */
00079 #define WF0     128  /* modifies f0 */
00080 #define WCAR    256  /* write Carry */
00081 #define BRANCH  512  /* branch, no link */
00082 #define ALONE  1024  /* short but pack with a NOP if on asm line alone */
00083 
00084   /* the opcode */
00085   long opcode;
00086 
00087   /* mask.  if( (i & mask) == opcode ) then match */
00088   long mask;
00089 
00090   /* An array of operand codes.  Each code is an index into the
00091      operand table.  They appear in the order which the operands must
00092      appear in assembly code, and are terminated by a zero.  */
00093   unsigned char operands[6];
00094 };
00095 
00096 /* The table itself is sorted by major opcode number, and is otherwise
00097    in the order in which the disassembler should consider
00098    instructions.  */
00099 extern const struct d10v_opcode d10v_opcodes[];
00100 extern const int d10v_num_opcodes;
00101 
00102 /* The operands table is an array of struct d10v_operand.  */
00103 struct d10v_operand
00104 {
00105   /* The number of bits in the operand.  */
00106   int bits;
00107 
00108   /* How far the operand is left shifted in the instruction.  */
00109   int shift;
00110 
00111   /* One bit syntax flags.  */
00112   int flags;
00113 };
00114 
00115 /* Elements in the table are retrieved by indexing with values from
00116    the operands field of the d10v_opcodes table.  */
00117 
00118 extern const struct d10v_operand d10v_operands[];
00119 
00120 /* Values defined for the flags field of a struct d10v_operand.  */
00121 
00122 /* the operand must be an even number */
00123 #define OPERAND_EVEN (1)
00124 
00125 /* the operand must be an odd number */
00126 #define OPERAND_ODD  (2)    
00127 
00128 /* this is the destination register; it will be modified */
00129 /* this is used by the optimizer */
00130 #define OPERAND_DEST (4)
00131 
00132 /* number or symbol */
00133 #define OPERAND_NUM  (8)
00134 
00135 /* address or label */
00136 #define OPERAND_ADDR (0x10)
00137 
00138 /* register */
00139 #define OPERAND_REG  (0x20)
00140 
00141 /* postincrement +  */
00142 #define OPERAND_PLUS (0x40)
00143 
00144 /* postdecrement -  */
00145 #define OPERAND_MINUS       (0x80)
00146 
00147 /* @  */
00148 #define OPERAND_ATSIGN      (0x100)
00149 
00150 /* @(  */
00151 #define OPERAND_ATPAR       (0x200)
00152 
00153 /* accumulator 0 */
00154 #define OPERAND_ACC0 (0x400)
00155 
00156 /* accumulator 1 */
00157 #define OPERAND_ACC1 (0x800)
00158 
00159 /* f0 / f1 flag register */
00160 #define OPERAND_FFLAG       (0x1000)
00161 
00162 /* c flag register */
00163 #define OPERAND_CFLAG       (0x2000)
00164 
00165 /* control register  */
00166 #define OPERAND_CONTROL     (0x4000)
00167 
00168 /* predecrement mode '@-sp'  */
00169 #define OPERAND_ATMINUS     (0x8000)
00170 
00171 /* signed number */
00172 #define OPERAND_SIGNED      (0x10000)
00173 
00174 /* special accumulator shifts need a 4-bit number */
00175 /* 1 <= x <= 16 */
00176 #define OPERAND_SHIFT       (0x20000)
00177 
00178 /* general purpose register */
00179 #define OPERAND_GPR  (0x40000)
00180 
00181 /* special imm3 values with range restricted to -2 <= imm3 <= 3 */
00182 /* needed for rac/rachi */
00183 #define RESTRICTED_NUM3     (0x80000)
00184 
00185 /* Pre-decrement is only supported for SP.  */
00186 #define OPERAND_SP      (0x100000)
00187 
00188 /* Post-decrement is not supported for SP.  Like OPERAND_EVEN, and
00189    unlike OPERAND_SP, this flag doesn't prevent the instruction from
00190    matching, it only fails validation later on.  */
00191 #define OPERAND_NOSP    (0x200000)
00192 
00193 /* Structure to hold information about predefined registers.  */
00194 struct pd_reg
00195 {
00196   char *name;        /* name to recognize */
00197   char *pname;              /* name to print for this register */
00198   int value;
00199 };
00200 
00201 extern const struct pd_reg d10v_predefined_registers[];
00202 int d10v_reg_name_cnt (void);
00203 
00204 /* an expressionS only has one register type, so we fake it */
00205 /* by setting high bits to indicate type */
00206 #define REGISTER_MASK       0xFF
00207 
00208 #endif /* D10V_H */