Back to index

cell-binutils  2.17cvs20070401
crx.h
Go to the documentation of this file.
00001 /* crx.h -- Header file for CRX opcode and register tables.
00002    Copyright 2004 Free Software Foundation, Inc.
00003    Contributed by Tomer Levi, NSC, Israel.
00004    Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
00005    Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
00006 
00007    This file is part of GAS, GDB and the GNU binutils.
00008 
00009    GAS, GDB, and GNU binutils is free software; you can redistribute it
00010    and/or modify it under the terms of the GNU General Public License as
00011    published by the Free Software Foundation; either version 2, or (at your
00012    option) any later version.
00013 
00014    GAS, GDB, and GNU binutils are distributed in the hope that they will be
00015    useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
00016    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017    GNU General Public License for more details.
00018 
00019    You should have received a copy of the GNU General Public License
00020    along with this program; if not, write to the Free Software
00021    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00022 
00023 #ifndef _CRX_H_
00024 #define _CRX_H_
00025 
00026 /* CRX core/debug Registers :
00027    The enums are used as indices to CRX registers table (crx_regtab).
00028    Therefore, order MUST be preserved.  */
00029 
00030 typedef enum
00031   {
00032     /* 32-bit general purpose registers.  */
00033     r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
00034     r10, r11, r12, r13, r14, r15, ra, sp,
00035     /* 32-bit user registers.  */
00036     u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
00037     u10, u11, u12, u13, u14, u15, ura, usp,
00038     /* hi and lo registers.  */
00039     hi, lo,
00040     /* hi and lo user registers.  */
00041     uhi, ulo,
00042     /* Processor Status Register.  */
00043     psr,
00044     /* Interrupt Base Register.  */
00045     intbase,
00046     /* Interrupt Stack Pointer Register.  */
00047     isp,
00048     /* Configuration Register.  */
00049     cfg,
00050     /* Coprocessor Configuration Register.  */
00051     cpcfg,
00052     /* Coprocessor Enable Register.  */
00053     cen,
00054     /* Not a register.  */
00055     nullregister,
00056     MAX_REG
00057   }
00058 reg;
00059 
00060 /* CRX Coprocessor registers and special registers :
00061    The enums are used as indices to CRX coprocessor registers table
00062    (crx_copregtab). Therefore, order MUST be preserved.  */
00063 
00064 typedef enum
00065   {
00066     /* Coprocessor registers.  */
00067     c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
00068     c9, c10, c11, c12, c13, c14, c15,
00069     /* Coprocessor special registers.  */
00070     cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
00071     cs9, cs10, cs11, cs12, cs13, cs14, cs15,
00072     /* Not a Coprocessor register.  */
00073     nullcopregister,
00074     MAX_COPREG
00075   }
00076 copreg;
00077 
00078 /* CRX Register types. */
00079 
00080 typedef enum
00081   {
00082     CRX_R_REGTYPE,    /*  r<N>       */
00083     CRX_U_REGTYPE,    /*  u<N>       */
00084     CRX_C_REGTYPE,    /*  c<N>       */
00085     CRX_CS_REGTYPE,   /*  cs<N>      */
00086     CRX_CFG_REGTYPE   /*  configuration register   */
00087   }
00088 reg_type;
00089 
00090 /* CRX argument types :
00091    The argument types correspond to instructions operands
00092 
00093    Argument types :
00094    r - register
00095    c - constant
00096    i - immediate
00097    idxr - index register
00098    rbase - register base
00099    s - star ('*')
00100    copr - coprocessor register
00101    copsr - coprocessor special register.  */
00102 
00103 typedef enum
00104   {
00105     arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc,
00106     arg_idxr, arg_rbase, arg_copr, arg_copsr,
00107     /* Not an argument.  */
00108     nullargs
00109   }
00110 argtype;
00111 
00112 /* CRX operand types :
00113    The operand types correspond to instructions operands.  */
00114 
00115 typedef enum
00116   {
00117     dummy,
00118     /* 4-bit encoded constant.  */
00119     cst4,
00120     /* N-bit immediate.  */
00121     i16, i32,
00122     /* N-bit unsigned immediate.  */
00123     ui3, ui4, ui5, ui16,
00124     /* N-bit signed displacement.  */
00125     disps9, disps17, disps25, disps32,
00126     /* N-bit unsigned displacement.  */
00127     dispu5, 
00128     /* N-bit escaped displacement.  */
00129     dispe9,
00130     /* N-bit absolute address.  */
00131     abs16, abs32,
00132     /* Register relative.  */
00133     rbase, rbase_dispu4,
00134     rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
00135     /* Register index.  */
00136     rindex_disps6, rindex_disps22,
00137     /* 4-bit genaral-purpose register specifier.  */
00138     regr, 
00139     /* 8-bit register address space.  */
00140     regr8,
00141     /* coprocessor register.  */
00142     copregr, 
00143     /* coprocessor special register.  */
00144     copsregr,
00145     /* Not an operand.  */
00146     nulloperand,
00147     /* Maximum supported operand.  */
00148     MAX_OPRD
00149   }
00150 operand_type;
00151 
00152 /* CRX instruction types.  */
00153 
00154 #define NO_TYPE_INS       0
00155 #define ARITH_INS         1
00156 #define LD_STOR_INS       2
00157 #define BRANCH_INS        3
00158 #define ARITH_BYTE_INS    4
00159 #define CMPBR_INS         5
00160 #define SHIFT_INS         6
00161 #define BRANCH_NEQ_INS    7
00162 #define LD_STOR_INS_INC   8
00163 #define STOR_IMM_INS   9
00164 #define CSTBIT_INS       10
00165 #define COP_BRANCH_INS   11
00166 #define COP_REG_INS      12
00167 #define COPS_REG_INS     13
00168 #define DCR_BRANCH_INS   14
00169 
00170 /* Maximum value supported for instruction types.  */
00171 #define CRX_INS_MAX  (1 << 4)
00172 /* Mask to record an instruction type.  */
00173 #define CRX_INS_MASK (CRX_INS_MAX - 1)
00174 /* Return instruction type, given instruction's attributes.  */
00175 #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
00176 
00177 /* Indicates whether this instruction has a register list as parameter.  */
00178 #define REG_LIST     CRX_INS_MAX
00179 /* The operands in binary and assembly are placed in reverse order.
00180    load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
00181 #define REVERSE_MATCH  (1 << 5)
00182 
00183 /* Kind of displacement map used DISPU[BWD]4.  */
00184 #define DISPUB4             (1 << 6)
00185 #define DISPUW4             (1 << 7)
00186 #define DISPUD4             (1 << 8)
00187 #define DISPU4MAP      (DISPUB4 | DISPUW4 | DISPUD4)
00188 
00189 /* Printing formats, where the instruction prefix isn't consecutive.  */
00190 #define FMT_1        (1 << 9)   /* 0xF0F00000 */
00191 #define FMT_2        (1 << 10)   /* 0xFFF0FF00 */
00192 #define FMT_3        (1 << 11)   /* 0xFFF00F00 */
00193 #define FMT_4        (1 << 12)   /* 0xFFF0F000 */
00194 #define FMT_5        (1 << 13)   /* 0xFFF0FFF0 */
00195 #define FMT_CRX             (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
00196 
00197 /* Indicates whether this instruction can be relaxed.  */
00198 #define RELAXABLE      (1 << 14)
00199 
00200 /* Indicates that instruction uses user registers (and not 
00201    general-purpose registers) as operands.  */
00202 #define USER_REG       (1 << 15)
00203 
00204 /* Indicates that instruction can perfom a cst4 mapping.  */
00205 #define CST4MAP             (1 << 16)
00206 
00207 /* Instruction shouldn't allow 'sp' usage.  */
00208 #define NO_SP        (1 << 17)
00209 
00210 /* Instruction shouldn't allow to push a register which is used as a rptr.  */
00211 #define NO_RPTR             (1 << 18)
00212 
00213 /* Maximum operands per instruction.  */
00214 #define MAX_OPERANDS   5
00215 /* Maximum register name length. */
00216 #define MAX_REGNAME_LEN       10
00217 /* Maximum instruction length. */
00218 #define MAX_INST_LEN   256
00219 
00220 
00221 /* Values defined for the flags field of a struct operand_entry.  */
00222 
00223 /* Operand must be an unsigned number.  */
00224 #define OP_UNSIGNED   (1 << 0)
00225 /* Operand must be a signed number.  */
00226 #define OP_SIGNED     (1 << 1)
00227 /* A special arithmetic 4-bit constant operand.  */
00228 #define OP_CST4            (1 << 2)
00229 /* A special load/stor 4-bit unsigned displacement operand.  */
00230 #define OP_DISPU4     (1 << 3)
00231 /* Operand must be an even number.  */
00232 #define OP_EVEN            (1 << 4)
00233 /* Operand is shifted right.  */
00234 #define OP_SHIFT      (1 << 5)
00235 /* Operand is shifted right and decremented.  */
00236 #define OP_SHIFT_DEC  (1 << 6)
00237 /* Operand has reserved escape sequences.  */
00238 #define OP_ESC             (1 << 7)
00239 /* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF).  */
00240 #define OP_UPPER_64KB (1 << 8)
00241 
00242 /* Single operand description.  */
00243 
00244 typedef struct
00245   {
00246     /* Operand type.  */
00247     operand_type op_type;
00248     /* Operand location within the opcode.  */
00249     unsigned int shift;
00250   }
00251 operand_desc;
00252 
00253 /* Instruction data structure used in instruction table.  */
00254 
00255 typedef struct
00256   {
00257     /* Name.  */
00258     const char *mnemonic;
00259     /* Size (in words).  */
00260     unsigned int size;
00261     /* Constant prefix (matched by the disassembler).  */
00262     unsigned long match;
00263     /* Match size (in bits).  */
00264     int match_bits;
00265     /* Attributes.  */
00266     unsigned int flags;
00267     /* Operands (always last, so unreferenced operands are initialized).  */
00268     operand_desc operands[MAX_OPERANDS];
00269   }
00270 inst;
00271 
00272 /* Data structure for a single instruction's arguments (Operands).  */
00273 
00274 typedef struct
00275   {
00276     /* Register or base register.  */
00277     reg r;
00278     /* Index register.  */
00279     reg i_r;
00280     /* Coprocessor register.  */
00281     copreg cr;
00282     /* Constant/immediate/absolute value.  */
00283     long constant;
00284     /* Scaled index mode.  */
00285     unsigned int scale;
00286     /* Argument type.  */
00287     argtype type;
00288     /* Size of the argument (in bits) required to represent.  */
00289     int size;
00290   /* The type of the expression.  */
00291     unsigned char X_op;
00292   }
00293 argument;
00294 
00295 /* Internal structure to hold the various entities
00296    corresponding to the current assembling instruction.  */
00297 
00298 typedef struct
00299   {
00300     /* Number of arguments.  */
00301     int nargs;
00302     /* The argument data structure for storing args (operands).  */
00303     argument arg[MAX_OPERANDS];
00304 /* The following fields are required only by CRX-assembler.  */
00305 #ifdef TC_CRX
00306     /* Expression used for setting the fixups (if any).  */
00307     expressionS exp;
00308     bfd_reloc_code_real_type rtype;
00309 #endif /* TC_CRX */
00310     /* Instruction size (in bytes).  */
00311     int size;
00312   }
00313 ins;
00314 
00315 /* Structure to hold information about predefined operands.  */
00316 
00317 typedef struct
00318   {
00319     /* Size (in bits).  */
00320     unsigned int bit_size;
00321     /* Argument type.  */
00322     argtype arg_type;
00323     /* One bit syntax flags.  */
00324     int flags;
00325   }
00326 operand_entry;
00327 
00328 /* Structure to hold trap handler information.  */
00329 
00330 typedef struct
00331   {
00332     /* Trap name.  */
00333     char *name;
00334     /* Index in dispatch table.  */
00335     unsigned int entry;
00336   }
00337 trap_entry;
00338 
00339 /* Structure to hold information about predefined registers.  */
00340 
00341 typedef struct
00342   {
00343     /* Name (string representation).  */
00344     char *name;
00345     /* Value (enum representation).  */
00346     union
00347     {
00348       /* Register.  */
00349       reg reg_val;
00350       /* Coprocessor register.  */
00351       copreg copreg_val;
00352     } value;
00353     /* Register image.  */
00354     int image;
00355     /* Register type.  */
00356     reg_type type;
00357   }
00358 reg_entry;
00359 
00360 /* Structure to hold a cst4 operand mapping.  */
00361 
00362 /* CRX opcode table.  */
00363 extern const inst crx_instruction[];
00364 extern const int crx_num_opcodes;
00365 #define NUMOPCODES crx_num_opcodes
00366 
00367 /* CRX operands table.  */
00368 extern const operand_entry crx_optab[];
00369 
00370 /* CRX registers table.  */
00371 extern const reg_entry crx_regtab[];
00372 extern const int crx_num_regs;
00373 #define NUMREGS crx_num_regs
00374 
00375 /* CRX coprocessor registers table.  */
00376 extern const reg_entry crx_copregtab[];
00377 extern const int crx_num_copregs;
00378 #define NUMCOPREGS crx_num_copregs
00379 
00380 /* CRX trap/interrupt table.  */
00381 extern const trap_entry crx_traps[];
00382 extern const int crx_num_traps;
00383 #define NUMTRAPS crx_num_traps
00384 
00385 /* cst4 operand mapping.  */
00386 extern const long cst4_map[];
00387 extern const int cst4_maps;
00388 
00389 /* Table of instructions with no operands.  */
00390 extern const char* no_op_insn[];
00391 
00392 /* Current instruction we're assembling.  */
00393 extern const inst *instruction;
00394 
00395 /* A macro for representing the instruction "constant" opcode, that is,
00396    the FIXED part of the instruction. The "constant" opcode is represented
00397    as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
00398    over that range.  */
00399 #define BIN(OPC,SHIFT)      (OPC << SHIFT)
00400 
00401 /* Is the current instruction type is TYPE ?  */
00402 #define IS_INSN_TYPE(TYPE)        \
00403   (CRX_INS_TYPE(instruction->flags) == TYPE)
00404 
00405 /* Is the current instruction mnemonic is MNEMONIC ?  */
00406 #define IS_INSN_MNEMONIC(MNEMONIC)    \
00407   (strcmp(instruction->mnemonic,MNEMONIC) == 0)
00408 
00409 /* Does the current instruction has register list ?  */
00410 #define INST_HAS_REG_LIST         \
00411   (instruction->flags & REG_LIST)
00412 
00413 /* Long long type handling.  */
00414 /* Replace all appearances of 'long long int' with LONGLONG.  */
00415 typedef long long int LONGLONG;
00416 typedef unsigned long long ULONGLONG;
00417 
00418 #endif /* _CRX_H_ */