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cris.h
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00001 /* cris.h -- Header file for CRIS opcode and register tables.
00002    Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
00003    Contributed by Axis Communications AB, Lund, Sweden.
00004    Originally written for GAS 1.38.1 by Mikael Asker.
00005    Updated, BFDized and GNUified by Hans-Peter Nilsson.
00006 
00007 This file is part of GAS, GDB and the GNU binutils.
00008 
00009 GAS, GDB, and GNU binutils is free software; you can redistribute it
00010 and/or modify it under the terms of the GNU General Public License as
00011 published by the Free Software Foundation; either version 2, or (at your
00012 option) any later version.
00013 
00014 GAS, GDB, and GNU binutils are distributed in the hope that they will be
00015 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License
00020 along with this program; if not, write to the Free Software
00021 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00022 
00023 #ifndef __CRIS_H_INCLUDED_
00024 #define __CRIS_H_INCLUDED_
00025 
00026 #if !defined(__STDC__) && !defined(const)
00027 #define const
00028 #endif
00029 
00030 
00031 /* Registers.  */
00032 #define MAX_REG (15)
00033 #define REG_SP (14)
00034 #define REG_PC (15)
00035 
00036 /* CPU version control of disassembly and assembly of instructions.
00037    May affect how the instruction is assembled, at least the size of
00038    immediate operands.  */
00039 enum cris_insn_version_usage
00040 {
00041   /* Any version.  */
00042   cris_ver_version_all=0,
00043 
00044   /* Indeterminate (intended for disassembly only, or obsolete).  */
00045   cris_ver_warning,
00046 
00047   /* Only for v0..3 (Etrax 1..4).  */
00048   cris_ver_v0_3,
00049 
00050   /* Only for v3 or higher (ETRAX 4 and beyond).  */
00051   cris_ver_v3p,
00052 
00053   /* Only for v8 (Etrax 100).  */
00054   cris_ver_v8,
00055 
00056   /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
00057   cris_ver_v8p,
00058 
00059   /* Only for v0..10.  FIXME: Not sure what to do with this.  */
00060   cris_ver_sim_v0_10,
00061 
00062   /* Only for v0..10.  */
00063   cris_ver_v0_10,
00064 
00065   /* Only for v3..10.  (ETRAX 4, ETRAX 100 and ETRAX 100 LX).  */
00066   cris_ver_v3_10,
00067 
00068   /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX).  */
00069   cris_ver_v8_10,
00070 
00071   /* Only for v10 (ETRAX 100 LX) and same series.  */
00072   cris_ver_v10,
00073 
00074   /* Only for v10 (ETRAX 100 LX) and same series.  */
00075   cris_ver_v10p,
00076 
00077   /* Only for v32 or higher (codename GUINNESS).
00078      Of course some or all these of may change to cris_ver_v32p if/when
00079      there's a new revision. */
00080   cris_ver_v32p
00081 };
00082 
00083 
00084 /* Special registers.  */
00085 struct cris_spec_reg
00086 {
00087   const char *const name;
00088   unsigned int number;
00089 
00090   /* The size of the register.  */
00091   unsigned int reg_size;
00092 
00093   /* What CPU version the special register of that name is implemented
00094      in.  If cris_ver_warning, emit an unimplemented-warning.  */
00095   enum cris_insn_version_usage applicable_version;
00096 
00097   /* There might be a specific warning for using a special register
00098      here.  */
00099   const char *const warning;
00100 };
00101 extern const struct cris_spec_reg cris_spec_regs[];
00102 
00103 
00104 /* Support registers (kind of special too, but not named as such).  */
00105 struct cris_support_reg
00106 {
00107   const char *const name;
00108   unsigned int number;
00109 };
00110 extern const struct cris_support_reg cris_support_regs[];
00111 
00112 struct cris_cond15
00113 {
00114   /* The name of the condition.  */
00115   const char *const name;
00116 
00117   /* What CPU version this condition name applies to.  */
00118   enum cris_insn_version_usage applicable_version;
00119 };
00120 extern const struct cris_cond15 cris_conds15[];
00121 
00122 /* Opcode-dependent constants.  */
00123 #define AUTOINCR_BIT (0x04)
00124 
00125 /* Prefixes.  */
00126 #define BDAP_QUICK_OPCODE (0x0100)
00127 #define BDAP_QUICK_Z_BITS (0x0e00)
00128 
00129 #define BIAP_OPCODE    (0x0540)
00130 #define BIAP_Z_BITS    (0x0a80)
00131 
00132 #define DIP_OPCODE     (0x0970)
00133 #define DIP_Z_BITS     (0xf280)
00134 
00135 #define BDAP_INDIR_LOW        (0x40)
00136 #define BDAP_INDIR_LOW_Z  (0x80)
00137 #define BDAP_INDIR_HIGH       (0x09)
00138 #define BDAP_INDIR_HIGH_Z (0x02)
00139 
00140 #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
00141 #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
00142 #define BDAP_PC_LOW    (BDAP_INDIR_LOW + REG_PC)
00143 #define BDAP_INCR_HIGH        (BDAP_INDIR_HIGH + AUTOINCR_BIT)
00144 
00145 /* No prefix must have this code for its "match" bits in the
00146    opcode-table.  "BCC .+2" will do nicely.  */
00147 #define NO_CRIS_PREFIX 0
00148 
00149 /* Definitions for condition codes.  */
00150 #define CC_CC  0x0
00151 #define CC_HS  0x0
00152 #define CC_CS  0x1
00153 #define CC_LO  0x1
00154 #define CC_NE  0x2
00155 #define CC_EQ  0x3
00156 #define CC_VC  0x4
00157 #define CC_VS  0x5
00158 #define CC_PL  0x6
00159 #define CC_MI  0x7
00160 #define CC_LS  0x8
00161 #define CC_HI  0x9
00162 #define CC_GE  0xA
00163 #define CC_LT  0xB
00164 #define CC_GT  0xC
00165 #define CC_LE  0xD
00166 #define CC_A   0xE
00167 #define CC_EXT 0xF
00168 
00169 /* A table of strings "cc", "cs"... indexed with condition code
00170    values as above.  */
00171 extern const char *const cris_cc_strings[];
00172 
00173 /* Bcc quick.  */
00174 #define BRANCH_QUICK_LOW  (0)
00175 #define BRANCH_QUICK_HIGH (0)
00176 #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
00177 #define BRANCH_QUICK_Z_BITS (0x0F00)
00178 
00179 /* BA quick.  */
00180 #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
00181 #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
00182 
00183 /* Bcc [PC+].  */
00184 #define BRANCH_PC_LOW        (0xFF)
00185 #define BRANCH_INCR_HIGH (0x0D)
00186 #define BA_PC_INCR_OPCODE \
00187  ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
00188 
00189 /* Jump.  */
00190 /* Note that old versions generated special register 8 (in high bits)
00191    and not-that-old versions recognized it as a jump-instruction.
00192    That opcode now belongs to JUMPU.  */
00193 #define JUMP_INDIR_OPCODE (0x0930)
00194 #define JUMP_INDIR_Z_BITS (0xf2c0)
00195 #define JUMP_PC_INCR_OPCODE \
00196  (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
00197 
00198 #define MOVE_M_TO_PREG_OPCODE 0x0a30
00199 #define MOVE_M_TO_PREG_ZBITS 0x01c0
00200 
00201 /* BDAP.D N,PC.  */
00202 #define MOVE_PC_INCR_OPCODE_PREFIX \
00203  (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
00204 #define MOVE_PC_INCR_OPCODE_SUFFIX \
00205  (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
00206 
00207 #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
00208 
00209 /* BA DWORD (V32).  */
00210 #define BA_DWORD_OPCODE (0x0EBF)
00211 
00212 /* Nop.  */
00213 #define NOP_OPCODE (0x050F)
00214 #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
00215 
00216 #define NOP_OPCODE_V32 (0x05B0)
00217 #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
00218 
00219 /* For the compatibility mode, let's use "MOVE R0,P0".  Doesn't affect
00220    registers or flags.  Unfortunately shuts off interrupts for one cycle
00221    for < v32, but there doesn't seem to be any alternative without that
00222    effect.  */
00223 #define NOP_OPCODE_COMMON (0x630)
00224 #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
00225 
00226 /* LAPC.D  */
00227 #define LAPC_DWORD_OPCODE (0x0D7F)
00228 #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
00229 
00230 /* Structure of an opcode table entry.  */
00231 enum cris_imm_oprnd_size_type
00232 {
00233   /* No size is applicable.  */
00234   SIZE_NONE,
00235 
00236   /* Always 32 bits.  */
00237   SIZE_FIX_32,
00238 
00239   /* Indicated by size of special register.  */
00240   SIZE_SPEC_REG,
00241 
00242   /* Indicated by size field, signed.  */
00243   SIZE_FIELD_SIGNED,
00244 
00245   /* Indicated by size field, unsigned.  */
00246   SIZE_FIELD_UNSIGNED,
00247 
00248   /* Indicated by size field, no sign implied.  */
00249   SIZE_FIELD
00250 };
00251 
00252 /* For GDB.  FIXME: Is this the best way to handle opcode
00253    interpretation?  */
00254 enum cris_op_type
00255 {
00256   cris_not_implemented_op = 0,
00257   cris_abs_op,
00258   cris_addi_op,
00259   cris_asr_op,
00260   cris_asrq_op,
00261   cris_ax_ei_setf_op,
00262   cris_bdap_prefix,
00263   cris_biap_prefix,
00264   cris_break_op,
00265   cris_btst_nop_op,
00266   cris_clearf_di_op,
00267   cris_dip_prefix,
00268   cris_dstep_logshift_mstep_neg_not_op,
00269   cris_eight_bit_offset_branch_op,
00270   cris_move_mem_to_reg_movem_op,
00271   cris_move_reg_to_mem_movem_op,
00272   cris_move_to_preg_op,
00273   cris_muls_op,
00274   cris_mulu_op,
00275   cris_none_reg_mode_add_sub_cmp_and_or_move_op,
00276   cris_none_reg_mode_clear_test_op,
00277   cris_none_reg_mode_jump_op,
00278   cris_none_reg_mode_move_from_preg_op,
00279   cris_quick_mode_add_sub_op,
00280   cris_quick_mode_and_cmp_move_or_op,
00281   cris_quick_mode_bdap_prefix,
00282   cris_reg_mode_add_sub_cmp_and_or_move_op,
00283   cris_reg_mode_clear_op,
00284   cris_reg_mode_jump_op,
00285   cris_reg_mode_move_from_preg_op,
00286   cris_reg_mode_test_op,
00287   cris_scc_op,
00288   cris_sixteen_bit_offset_branch_op,
00289   cris_three_operand_add_sub_cmp_and_or_op,
00290   cris_three_operand_bound_op,
00291   cris_two_operand_bound_op,
00292   cris_xor_op
00293 };
00294 
00295 struct cris_opcode
00296 {
00297   /* The name of the insn.  */
00298   const char *name;
00299 
00300   /* Bits that must be 1 for a match.  */
00301   unsigned int match;
00302 
00303   /* Bits that must be 0 for a match.  */
00304   unsigned int lose;
00305 
00306   /* See the table in "opcodes/cris-opc.c".  */
00307   const char *args;
00308 
00309   /* Nonzero if this is a delayed branch instruction.  */
00310   char delayed;
00311 
00312   /* Size of immediate operands.  */
00313   enum cris_imm_oprnd_size_type imm_oprnd_size;
00314 
00315   /* Indicates which version this insn was first implemented in.  */
00316   enum cris_insn_version_usage applicable_version;
00317 
00318   /* What kind of operation this is.  */
00319   enum cris_op_type op;
00320 };
00321 extern const struct cris_opcode cris_opcodes[];
00322 
00323 
00324 /* These macros are for the target-specific flags in disassemble_info
00325    used at disassembly.  */
00326 
00327 /* This insn accesses memory.  This flag is more trustworthy than
00328    checking insn_type for "dis_dref" which does not work for
00329    e.g. "JSR [foo]".  */
00330 #define CRIS_DIS_FLAG_MEMREF (1 << 0)
00331 
00332 /* The "target" field holds a register number.  */
00333 #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
00334 
00335 /* The "target2" field holds a register number; add it to "target".  */
00336 #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
00337 
00338 /* Yet another add-on: the register in "target2" must be multiplied
00339    by 2 before adding to "target".  */
00340 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
00341 
00342 /* Yet another add-on: the register in "target2" must be multiplied
00343    by 4 (mutually exclusive with .._MULT2).  */ 
00344 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
00345 
00346 /* The register in "target2" is an indirect memory reference (of the
00347    register there), add to "target".  Assumed size is dword (mutually
00348    exclusive with .._MULT[24]).  */
00349 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
00350 
00351 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
00352    sign-extended before adding to "target".  */
00353 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
00354 
00355 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
00356    sign-extended before adding to "target".  */
00357 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
00358 
00359 #endif /* __CRIS_H_INCLUDED_ */
00360 
00361 /*
00362  * Local variables:
00363  * eval: (c-set-style "gnu")
00364  * indent-tabs-mode: t
00365  * End:
00366  */