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alpha.h
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00001 /* alpha.h -- Header file for Alpha opcode table
00002    Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc.
00003    Contributed by Richard Henderson <rth@tamu.edu>,
00004    patterned after the PPC opcode table written by Ian Lance Taylor.
00005 
00006 This file is part of GDB, GAS, and the GNU binutils.
00007 
00008 GDB, GAS, and the GNU binutils are free software; you can redistribute
00009 them and/or modify them under the terms of the GNU General Public
00010 License as published by the Free Software Foundation; either version
00011 1, or (at your option) any later version.
00012 
00013 GDB, GAS, and the GNU binutils are distributed in the hope that they
00014 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016 the GNU General Public License for more details.
00017 
00018 You should have received a copy of the GNU General Public License
00019 along with this file; see the file COPYING.  If not, write to the Free
00020 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00021 
00022 #ifndef OPCODE_ALPHA_H
00023 #define OPCODE_ALPHA_H
00024 
00025 /* The opcode table is an array of struct alpha_opcode.  */
00026 
00027 struct alpha_opcode
00028 {
00029   /* The opcode name.  */
00030   const char *name;
00031 
00032   /* The opcode itself.  Those bits which will be filled in with
00033      operands are zeroes.  */
00034   unsigned opcode;
00035 
00036   /* The opcode mask.  This is used by the disassembler.  This is a
00037      mask containing ones indicating those bits which must match the
00038      opcode field, and zeroes indicating those bits which need not
00039      match (and are presumably filled in by operands).  */
00040   unsigned mask;
00041 
00042   /* One bit flags for the opcode.  These are primarily used to
00043      indicate specific processors and environments support the
00044      instructions.  The defined values are listed below. */
00045   unsigned flags;
00046 
00047   /* An array of operand codes.  Each code is an index into the
00048      operand table.  They appear in the order which the operands must
00049      appear in assembly code, and are terminated by a zero.  */
00050   unsigned char operands[4];
00051 };
00052 
00053 /* The table itself is sorted by major opcode number, and is otherwise
00054    in the order in which the disassembler should consider
00055    instructions.  */
00056 extern const struct alpha_opcode alpha_opcodes[];
00057 extern const unsigned alpha_num_opcodes;
00058 
00059 /* Values defined for the flags field of a struct alpha_opcode.  */
00060 
00061 /* CPU Availability */
00062 #define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
00063 #define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
00064 #define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
00065 #define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */
00066 #define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
00067 #define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
00068 #define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
00069 
00070 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
00071 
00072 /* A macro to extract the major opcode from an instruction.  */
00073 #define AXP_OP(i)    (((i) >> 26) & 0x3F)
00074 
00075 /* The total number of major opcodes. */
00076 #define AXP_NOPS     0x40
00077 
00078 
00079 /* The operands table is an array of struct alpha_operand.  */
00080 
00081 struct alpha_operand
00082 {
00083   /* The number of bits in the operand.  */
00084   unsigned int bits : 5;
00085 
00086   /* How far the operand is left shifted in the instruction.  */
00087   unsigned int shift : 5;
00088 
00089   /* The default relocation type for this operand.  */
00090   signed int default_reloc : 16;
00091 
00092   /* One bit syntax flags.  */
00093   unsigned int flags : 16;
00094 
00095   /* Insertion function.  This is used by the assembler.  To insert an
00096      operand value into an instruction, check this field.
00097 
00098      If it is NULL, execute
00099          i |= (op & ((1 << o->bits) - 1)) << o->shift;
00100      (i is the instruction which we are filling in, o is a pointer to
00101      this structure, and op is the opcode value; this assumes twos
00102      complement arithmetic).
00103 
00104      If this field is not NULL, then simply call it with the
00105      instruction and the operand value.  It will return the new value
00106      of the instruction.  If the ERRMSG argument is not NULL, then if
00107      the operand value is illegal, *ERRMSG will be set to a warning
00108      string (the operand will be inserted in any case).  If the
00109      operand value is legal, *ERRMSG will be unchanged (most operands
00110      can accept any value).  */
00111   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
00112 
00113   /* Extraction function.  This is used by the disassembler.  To
00114      extract this operand type from an instruction, check this field.
00115 
00116      If it is NULL, compute
00117          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
00118         if ((o->flags & AXP_OPERAND_SIGNED) != 0
00119             && (op & (1 << (o->bits - 1))) != 0)
00120           op -= 1 << o->bits;
00121      (i is the instruction, o is a pointer to this structure, and op
00122      is the result; this assumes twos complement arithmetic).
00123 
00124      If this field is not NULL, then simply call it with the
00125      instruction value.  It will return the value of the operand.  If
00126      the INVALID argument is not NULL, *INVALID will be set to
00127      non-zero if this operand type can not actually be extracted from
00128      this operand (i.e., the instruction does not match).  If the
00129      operand is valid, *INVALID will not be changed.  */
00130   int (*extract) (unsigned instruction, int *invalid);
00131 };
00132 
00133 /* Elements in the table are retrieved by indexing with values from
00134    the operands field of the alpha_opcodes table.  */
00135 
00136 extern const struct alpha_operand alpha_operands[];
00137 extern const unsigned alpha_num_operands;
00138 
00139 /* Values defined for the flags field of a struct alpha_operand.  */
00140 
00141 /* Mask for selecting the type for typecheck purposes */
00142 #define AXP_OPERAND_TYPECHECK_MASK                             \
00143   (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |          \
00144    AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED |      \
00145    AXP_OPERAND_UNSIGNED)
00146 
00147 /* This operand does not actually exist in the assembler input.  This
00148    is used to support extended mnemonics, for which two operands fields
00149    are identical.  The assembler should call the insert function with
00150    any op value.  The disassembler should call the extract function,
00151    ignore the return value, and check the value placed in the invalid
00152    argument.  */
00153 #define AXP_OPERAND_FAKE    01
00154 
00155 /* The operand should be wrapped in parentheses rather than separated
00156    from the previous by a comma.  This is used for the load and store
00157    instructions which want their operands to look like "Ra,disp(Rb)".  */
00158 #define AXP_OPERAND_PARENS  02
00159 
00160 /* Used in combination with PARENS, this supresses the supression of
00161    the comma.  This is used for "jmp Ra,(Rb),hint".  */
00162 #define AXP_OPERAND_COMMA   04
00163 
00164 /* This operand names an integer register.  */
00165 #define AXP_OPERAND_IR             010
00166 
00167 /* This operand names a floating point register.  */
00168 #define AXP_OPERAND_FPR            020
00169 
00170 /* This operand is a relative branch displacement.  The disassembler
00171    prints these symbolically if possible.  */
00172 #define AXP_OPERAND_RELATIVE       040
00173 
00174 /* This operand takes signed values.  */
00175 #define AXP_OPERAND_SIGNED  0100
00176 
00177 /* This operand takes unsigned values.  This exists primarily so that
00178    a flags value of 0 can be treated as end-of-arguments.  */
00179 #define AXP_OPERAND_UNSIGNED       0200
00180 
00181 /* Supress overflow detection on this field.  This is used for hints. */
00182 #define AXP_OPERAND_NOOVERFLOW     0400
00183 
00184 /* Mask for optional argument default value.  */
00185 #define AXP_OPERAND_OPTIONAL_MASK 07000
00186 
00187 /* This operand defaults to zero.  This is used for jump hints.  */
00188 #define AXP_OPERAND_DEFAULT_ZERO 01000
00189 
00190 /* This operand should default to the first (real) operand and is used
00191    in conjunction with AXP_OPERAND_OPTIONAL.  This allows
00192    "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
00193    it, but it's what DEC does.  */
00194 #define AXP_OPERAND_DEFAULT_FIRST 02000
00195 
00196 /* Similarly, this operand should default to the second (real) operand.
00197    This allows "negl $0" instead of "negl $0,$0".  */
00198 #define AXP_OPERAND_DEFAULT_SECOND 04000
00199 
00200 
00201 /* Register common names */
00202 
00203 #define AXP_REG_V0   0
00204 #define AXP_REG_T0   1
00205 #define AXP_REG_T1   2
00206 #define AXP_REG_T2   3
00207 #define AXP_REG_T3   4
00208 #define AXP_REG_T4   5
00209 #define AXP_REG_T5   6
00210 #define AXP_REG_T6   7
00211 #define AXP_REG_T7   8
00212 #define AXP_REG_S0   9
00213 #define AXP_REG_S1   10
00214 #define AXP_REG_S2   11
00215 #define AXP_REG_S3   12
00216 #define AXP_REG_S4   13
00217 #define AXP_REG_S5   14
00218 #define AXP_REG_FP   15
00219 #define AXP_REG_A0   16
00220 #define AXP_REG_A1   17
00221 #define AXP_REG_A2   18
00222 #define AXP_REG_A3   19
00223 #define AXP_REG_A4   20
00224 #define AXP_REG_A5   21
00225 #define AXP_REG_T8   22
00226 #define AXP_REG_T9   23
00227 #define AXP_REG_T10  24
00228 #define AXP_REG_T11  25
00229 #define AXP_REG_RA   26
00230 #define AXP_REG_PV   27
00231 #define AXP_REG_T12  27
00232 #define AXP_REG_AT   28
00233 #define AXP_REG_GP   29
00234 #define AXP_REG_SP   30
00235 #define AXP_REG_ZERO 31
00236 
00237 #endif /* OPCODE_ALPHA_H */