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cell-binutils  2.17cvs20070401
mt-opc.c
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00001 /* Instruction opcode table for mt.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include "ansidecl.h"
00027 #include "bfd.h"
00028 #include "symcat.h"
00029 #include "mt-desc.h"
00030 #include "mt-opc.h"
00031 #include "libiberty.h"
00032 
00033 /* -- opc.c */
00034 #include "safe-ctype.h"
00035 
00036 /* Special check to ensure that instruction exists for given machine.  */
00037 
00038 int
00039 mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
00040 {
00041   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
00042 
00043   /* No mach attribute?  Assume it's supported for all machs.  */
00044   if (machs == 0)
00045     return 1;
00046   
00047   return ((machs & cd->machs) != 0);
00048 }
00049 
00050 /* A better hash function for instruction mnemonics.  */
00051 
00052 unsigned int
00053 mt_asm_hash (const char* insn)
00054 {
00055   unsigned int hash;
00056   const char* m = insn;
00057 
00058   for (hash = 0; *m && ! ISSPACE (*m); m++)
00059     hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
00060 
00061   /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
00062 
00063   return hash % CGEN_ASM_HASH_SIZE;
00064 }
00065 
00066 
00067 /* -- asm.c */
00068 /* The hash functions are recorded here to help keep assembler code out of
00069    the disassembler and vice versa.  */
00070 
00071 static int asm_hash_insn_p        (const CGEN_INSN *);
00072 static unsigned int asm_hash_insn (const char *);
00073 static int dis_hash_insn_p        (const CGEN_INSN *);
00074 static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
00075 
00076 /* Instruction formats.  */
00077 
00078 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00079 #define F(f) & mt_cgen_ifld_table[MT_##f]
00080 #else
00081 #define F(f) & mt_cgen_ifld_table[MT_f]
00082 #endif
00083 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
00084   0, 0, 0x0, { { 0 } }
00085 };
00086 
00087 static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
00088   32, 32, 0xff000fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } }
00089 };
00090 
00091 static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
00092   32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16S) }, { 0 } }
00093 };
00094 
00095 static const CGEN_IFMT ifmt_addui ATTRIBUTE_UNUSED = {
00096   32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } }
00097 };
00098 
00099 static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
00100   32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU24) }, { 0 } }
00101 };
00102 
00103 static const CGEN_IFMT ifmt_ldui ATTRIBUTE_UNUSED = {
00104   32, 32, 0xfff00000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } }
00105 };
00106 
00107 static const CGEN_IFMT ifmt_brlt ATTRIBUTE_UNUSED = {
00108   32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } }
00109 };
00110 
00111 static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = {
00112   32, 32, 0xffff0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } }
00113 };
00114 
00115 static const CGEN_IFMT ifmt_jal ATTRIBUTE_UNUSED = {
00116   32, 32, 0xff0f0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } }
00117 };
00118 
00119 static const CGEN_IFMT ifmt_dbnz ATTRIBUTE_UNUSED = {
00120   32, 32, 0xff0f0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } }
00121 };
00122 
00123 static const CGEN_IFMT ifmt_ei ATTRIBUTE_UNUSED = {
00124   32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } }
00125 };
00126 
00127 static const CGEN_IFMT ifmt_si ATTRIBUTE_UNUSED = {
00128   32, 32, 0xffff0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } }
00129 };
00130 
00131 static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = {
00132   32, 32, 0xff0fffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } }
00133 };
00134 
00135 static const CGEN_IFMT ifmt_stw ATTRIBUTE_UNUSED = {
00136   32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } }
00137 };
00138 
00139 static const CGEN_IFMT ifmt_ldctxt ATTRIBUTE_UNUSED = {
00140   32, 32, 0xff000e00, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_RC) }, { F (F_RCNUM) }, { F (F_UU_3_11) }, { F (F_CONTNUM) }, { 0 } }
00141 };
00142 
00143 static const CGEN_IFMT ifmt_ldfb ATTRIBUTE_UNUSED = {
00144   32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16U) }, { 0 } }
00145 };
00146 
00147 static const CGEN_IFMT ifmt_fbcb ATTRIBUTE_UNUSED = {
00148   32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_4_15) }, { F (F_RC) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00149 };
00150 
00151 static const CGEN_IFMT ifmt_mfbcb ATTRIBUTE_UNUSED = {
00152   32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_4_15) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00153 };
00154 
00155 static const CGEN_IFMT ifmt_fbcci ATTRIBUTE_UNUSED = {
00156   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00157 };
00158 
00159 static const CGEN_IFMT ifmt_mfbcci ATTRIBUTE_UNUSED = {
00160   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00161 };
00162 
00163 static const CGEN_IFMT ifmt_fbcbdr ATTRIBUTE_UNUSED = {
00164   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_BALL2) }, { F (F_BRC2) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00165 };
00166 
00167 static const CGEN_IFMT ifmt_rcfbcb ATTRIBUTE_UNUSED = {
00168   32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00169 };
00170 
00171 static const CGEN_IFMT ifmt_mrcfbcb ATTRIBUTE_UNUSED = {
00172   32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00173 };
00174 
00175 static const CGEN_IFMT ifmt_cbcast ATTRIBUTE_UNUSED = {
00176   32, 32, 0xfc000380, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_UU_3_9) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
00177 };
00178 
00179 static const CGEN_IFMT ifmt_dupcbcast ATTRIBUTE_UNUSED = {
00180   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_CELL) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
00181 };
00182 
00183 static const CGEN_IFMT ifmt_wfbi ATTRIBUTE_UNUSED = {
00184   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_BANKADDR) }, { F (F_ROWNUM1) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00185 };
00186 
00187 static const CGEN_IFMT ifmt_wfb ATTRIBUTE_UNUSED = {
00188   32, 32, 0xff000040, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_UU_1_6) }, { F (F_CTXDISP) }, { 0 } }
00189 };
00190 
00191 static const CGEN_IFMT ifmt_rcrisc ATTRIBUTE_UNUSED = {
00192   32, 32, 0xfc080000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_UU_1_19) }, { F (F_COLNUM) }, { F (F_DRRR) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00193 };
00194 
00195 static const CGEN_IFMT ifmt_fbcbinc ATTRIBUTE_UNUSED = {
00196   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_INCAMT) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00197 };
00198 
00199 static const CGEN_IFMT ifmt_rcxmode ATTRIBUTE_UNUSED = {
00200   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_XMODE) }, { F (F_MASK1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
00201 };
00202 
00203 static const CGEN_IFMT ifmt_interleaver ATTRIBUTE_UNUSED = {
00204   32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MODE) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ID) }, { F (F_SIZE) }, { 0 } }
00205 };
00206 
00207 static const CGEN_IFMT ifmt_wfbinc ATTRIBUTE_UNUSED = {
00208   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00209 };
00210 
00211 static const CGEN_IFMT ifmt_mwfbinc ATTRIBUTE_UNUSED = {
00212   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00213 };
00214 
00215 static const CGEN_IFMT ifmt_wfbincr ATTRIBUTE_UNUSED = {
00216   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00217 };
00218 
00219 static const CGEN_IFMT ifmt_mwfbincr ATTRIBUTE_UNUSED = {
00220   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00221 };
00222 
00223 static const CGEN_IFMT ifmt_fbcbincs ATTRIBUTE_UNUSED = {
00224   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_A23) }, { F (F_CR) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00225 };
00226 
00227 static const CGEN_IFMT ifmt_mfbcbincs ATTRIBUTE_UNUSED = {
00228   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00229 };
00230 
00231 static const CGEN_IFMT ifmt_fbcbincrs ATTRIBUTE_UNUSED = {
00232   32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00233 };
00234 
00235 static const CGEN_IFMT ifmt_mfbcbincrs ATTRIBUTE_UNUSED = {
00236   32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } }
00237 };
00238 
00239 static const CGEN_IFMT ifmt_loop ATTRIBUTE_UNUSED = {
00240   32, 32, 0xff0fff00, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU8) }, { F (F_LOOPO) }, { 0 } }
00241 };
00242 
00243 static const CGEN_IFMT ifmt_loopi ATTRIBUTE_UNUSED = {
00244   32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_IMM16L) }, { F (F_LOOPO) }, { 0 } }
00245 };
00246 
00247 static const CGEN_IFMT ifmt_dfbc ATTRIBUTE_UNUSED = {
00248   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_RC3) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
00249 };
00250 
00251 static const CGEN_IFMT ifmt_dwfb ATTRIBUTE_UNUSED = {
00252   32, 32, 0xfc000080, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_UU1) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
00253 };
00254 
00255 static const CGEN_IFMT ifmt_dfbr ATTRIBUTE_UNUSED = {
00256   32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } }
00257 };
00258 
00259 #undef F
00260 
00261 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00262 #define A(a) (1 << CGEN_INSN_##a)
00263 #else
00264 #define A(a) (1 << CGEN_INSN_a)
00265 #endif
00266 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00267 #define OPERAND(op) MT_OPERAND_##op
00268 #else
00269 #define OPERAND(op) MT_OPERAND_op
00270 #endif
00271 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
00272 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00273 
00274 /* The instruction table.  */
00275 
00276 static const CGEN_OPCODE mt_cgen_insn_opcode_table[MAX_INSNS] =
00277 {
00278   /* Special null first entry.
00279      A `num' value of zero is thus invalid.
00280      Also, the special `invalid' insn resides here.  */
00281   { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
00282 /* add $frdrrr,$frsr1,$frsr2 */
00283   {
00284     { 0, 0, 0, 0 },
00285     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00286     & ifmt_add, { 0x0 }
00287   },
00288 /* addu $frdrrr,$frsr1,$frsr2 */
00289   {
00290     { 0, 0, 0, 0 },
00291     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00292     & ifmt_add, { 0x2000000 }
00293   },
00294 /* addi $frdr,$frsr1,#$imm16 */
00295   {
00296     { 0, 0, 0, 0 },
00297     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00298     & ifmt_addi, { 0x1000000 }
00299   },
00300 /* addui $frdr,$frsr1,#$imm16z */
00301   {
00302     { 0, 0, 0, 0 },
00303     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00304     & ifmt_addui, { 0x3000000 }
00305   },
00306 /* sub $frdrrr,$frsr1,$frsr2 */
00307   {
00308     { 0, 0, 0, 0 },
00309     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00310     & ifmt_add, { 0x4000000 }
00311   },
00312 /* subu $frdrrr,$frsr1,$frsr2 */
00313   {
00314     { 0, 0, 0, 0 },
00315     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00316     & ifmt_add, { 0x6000000 }
00317   },
00318 /* subi $frdr,$frsr1,#$imm16 */
00319   {
00320     { 0, 0, 0, 0 },
00321     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00322     & ifmt_addi, { 0x5000000 }
00323   },
00324 /* subui $frdr,$frsr1,#$imm16z */
00325   {
00326     { 0, 0, 0, 0 },
00327     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00328     & ifmt_addui, { 0x7000000 }
00329   },
00330 /* mul $frdrrr,$frsr1,$frsr2 */
00331   {
00332     { 0, 0, 0, 0 },
00333     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00334     & ifmt_add, { 0x8000000 }
00335   },
00336 /* muli $frdr,$frsr1,#$imm16 */
00337   {
00338     { 0, 0, 0, 0 },
00339     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00340     & ifmt_addi, { 0x9000000 }
00341   },
00342 /* and $frdrrr,$frsr1,$frsr2 */
00343   {
00344     { 0, 0, 0, 0 },
00345     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00346     & ifmt_add, { 0x10000000 }
00347   },
00348 /* andi $frdr,$frsr1,#$imm16z */
00349   {
00350     { 0, 0, 0, 0 },
00351     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00352     & ifmt_addui, { 0x11000000 }
00353   },
00354 /* or $frdrrr,$frsr1,$frsr2 */
00355   {
00356     { 0, 0, 0, 0 },
00357     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00358     & ifmt_add, { 0x12000000 }
00359   },
00360 /* nop */
00361   {
00362     { 0, 0, 0, 0 },
00363     { { MNEM, 0 } },
00364     & ifmt_nop, { 0x12000000 }
00365   },
00366 /* ori $frdr,$frsr1,#$imm16z */
00367   {
00368     { 0, 0, 0, 0 },
00369     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00370     & ifmt_addui, { 0x13000000 }
00371   },
00372 /* xor $frdrrr,$frsr1,$frsr2 */
00373   {
00374     { 0, 0, 0, 0 },
00375     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00376     & ifmt_add, { 0x14000000 }
00377   },
00378 /* xori $frdr,$frsr1,#$imm16z */
00379   {
00380     { 0, 0, 0, 0 },
00381     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00382     & ifmt_addui, { 0x15000000 }
00383   },
00384 /* nand $frdrrr,$frsr1,$frsr2 */
00385   {
00386     { 0, 0, 0, 0 },
00387     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00388     & ifmt_add, { 0x16000000 }
00389   },
00390 /* nandi $frdr,$frsr1,#$imm16z */
00391   {
00392     { 0, 0, 0, 0 },
00393     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00394     & ifmt_addui, { 0x17000000 }
00395   },
00396 /* nor $frdrrr,$frsr1,$frsr2 */
00397   {
00398     { 0, 0, 0, 0 },
00399     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00400     & ifmt_add, { 0x18000000 }
00401   },
00402 /* nori $frdr,$frsr1,#$imm16z */
00403   {
00404     { 0, 0, 0, 0 },
00405     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00406     & ifmt_addui, { 0x19000000 }
00407   },
00408 /* xnor $frdrrr,$frsr1,$frsr2 */
00409   {
00410     { 0, 0, 0, 0 },
00411     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00412     & ifmt_add, { 0x1a000000 }
00413   },
00414 /* xnori $frdr,$frsr1,#$imm16z */
00415   {
00416     { 0, 0, 0, 0 },
00417     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } },
00418     & ifmt_addui, { 0x1b000000 }
00419   },
00420 /* ldui $frdr,#$imm16z */
00421   {
00422     { 0, 0, 0, 0 },
00423     { { MNEM, ' ', OP (FRDR), ',', '#', OP (IMM16Z), 0 } },
00424     & ifmt_ldui, { 0x1d000000 }
00425   },
00426 /* lsl $frdrrr,$frsr1,$frsr2 */
00427   {
00428     { 0, 0, 0, 0 },
00429     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00430     & ifmt_add, { 0x20000000 }
00431   },
00432 /* lsli $frdr,$frsr1,#$imm16 */
00433   {
00434     { 0, 0, 0, 0 },
00435     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00436     & ifmt_addi, { 0x21000000 }
00437   },
00438 /* lsr $frdrrr,$frsr1,$frsr2 */
00439   {
00440     { 0, 0, 0, 0 },
00441     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00442     & ifmt_add, { 0x22000000 }
00443   },
00444 /* lsri $frdr,$frsr1,#$imm16 */
00445   {
00446     { 0, 0, 0, 0 },
00447     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00448     & ifmt_addi, { 0x23000000 }
00449   },
00450 /* asr $frdrrr,$frsr1,$frsr2 */
00451   {
00452     { 0, 0, 0, 0 },
00453     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } },
00454     & ifmt_add, { 0x24000000 }
00455   },
00456 /* asri $frdr,$frsr1,#$imm16 */
00457   {
00458     { 0, 0, 0, 0 },
00459     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00460     & ifmt_addi, { 0x25000000 }
00461   },
00462 /* brlt $frsr1,$frsr2,$imm16o */
00463   {
00464     { 0, 0, 0, 0 },
00465     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
00466     & ifmt_brlt, { 0x31000000 }
00467   },
00468 /* brle $frsr1,$frsr2,$imm16o */
00469   {
00470     { 0, 0, 0, 0 },
00471     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
00472     & ifmt_brlt, { 0x33000000 }
00473   },
00474 /* breq $frsr1,$frsr2,$imm16o */
00475   {
00476     { 0, 0, 0, 0 },
00477     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
00478     & ifmt_brlt, { 0x35000000 }
00479   },
00480 /* brne $frsr1,$frsr2,$imm16o */
00481   {
00482     { 0, 0, 0, 0 },
00483     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } },
00484     & ifmt_brlt, { 0x3b000000 }
00485   },
00486 /* jmp $imm16o */
00487   {
00488     { 0, 0, 0, 0 },
00489     { { MNEM, ' ', OP (IMM16O), 0 } },
00490     & ifmt_jmp, { 0x37000000 }
00491   },
00492 /* jal $frdrrr,$frsr1 */
00493   {
00494     { 0, 0, 0, 0 },
00495     { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), 0 } },
00496     & ifmt_jal, { 0x38000000 }
00497   },
00498 /* dbnz $frsr1,$imm16o */
00499   {
00500     { 0, 0, 0, 0 },
00501     { { MNEM, ' ', OP (FRSR1), ',', OP (IMM16O), 0 } },
00502     & ifmt_dbnz, { 0x3d000000 }
00503   },
00504 /* ei */
00505   {
00506     { 0, 0, 0, 0 },
00507     { { MNEM, 0 } },
00508     & ifmt_ei, { 0x60000000 }
00509   },
00510 /* di */
00511   {
00512     { 0, 0, 0, 0 },
00513     { { MNEM, 0 } },
00514     & ifmt_ei, { 0x62000000 }
00515   },
00516 /* si $frdrrr */
00517   {
00518     { 0, 0, 0, 0 },
00519     { { MNEM, ' ', OP (FRDRRR), 0 } },
00520     & ifmt_si, { 0x64000000 }
00521   },
00522 /* reti $frsr1 */
00523   {
00524     { 0, 0, 0, 0 },
00525     { { MNEM, ' ', OP (FRSR1), 0 } },
00526     & ifmt_reti, { 0x66000000 }
00527   },
00528 /* ldw $frdr,$frsr1,#$imm16 */
00529   {
00530     { 0, 0, 0, 0 },
00531     { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00532     & ifmt_addi, { 0x41000000 }
00533   },
00534 /* stw $frsr2,$frsr1,#$imm16 */
00535   {
00536     { 0, 0, 0, 0 },
00537     { { MNEM, ' ', OP (FRSR2), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } },
00538     & ifmt_stw, { 0x43000000 }
00539   },
00540 /* break */
00541   {
00542     { 0, 0, 0, 0 },
00543     { { MNEM, 0 } },
00544     & ifmt_nop, { 0x68000000 }
00545   },
00546 /* iflush */
00547   {
00548     { 0, 0, 0, 0 },
00549     { { MNEM, 0 } },
00550     & ifmt_nop, { 0x6a000000 }
00551   },
00552 /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
00553   {
00554     { 0, 0, 0, 0 },
00555     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RC), ',', '#', OP (RCNUM), ',', '#', OP (CONTNUM), 0 } },
00556     & ifmt_ldctxt, { 0x80000000 }
00557   },
00558 /* ldfb $frsr1,$frsr2,#$imm16z */
00559   {
00560     { 0, 0, 0, 0 },
00561     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } },
00562     & ifmt_ldfb, { 0x84000000 }
00563   },
00564 /* stfb $frsr1,$frsr2,#$imm16z */
00565   {
00566     { 0, 0, 0, 0 },
00567     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } },
00568     & ifmt_ldfb, { 0x88000000 }
00569   },
00570 /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00571   {
00572     { 0, 0, 0, 0 },
00573     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00574     & ifmt_fbcb, { 0x8c000000 }
00575   },
00576 /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00577   {
00578     { 0, 0, 0, 0 },
00579     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00580     & ifmt_mfbcb, { 0x90000000 }
00581   },
00582 /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00583   {
00584     { 0, 0, 0, 0 },
00585     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00586     & ifmt_fbcci, { 0x94000000 }
00587   },
00588 /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00589   {
00590     { 0, 0, 0, 0 },
00591     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00592     & ifmt_fbcci, { 0x98000000 }
00593   },
00594 /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00595   {
00596     { 0, 0, 0, 0 },
00597     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00598     & ifmt_fbcci, { 0x9c000000 }
00599   },
00600 /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00601   {
00602     { 0, 0, 0, 0 },
00603     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00604     & ifmt_fbcci, { 0xa0000000 }
00605   },
00606 /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00607   {
00608     { 0, 0, 0, 0 },
00609     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00610     & ifmt_mfbcci, { 0xa4000000 }
00611   },
00612 /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00613   {
00614     { 0, 0, 0, 0 },
00615     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00616     & ifmt_mfbcci, { 0xa8000000 }
00617   },
00618 /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00619   {
00620     { 0, 0, 0, 0 },
00621     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00622     & ifmt_mfbcci, { 0xac000000 }
00623   },
00624 /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00625   {
00626     { 0, 0, 0, 0 },
00627     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00628     & ifmt_mfbcci, { 0xb0000000 }
00629   },
00630 /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00631   {
00632     { 0, 0, 0, 0 },
00633     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00634     & ifmt_fbcbdr, { 0xb4000000 }
00635   },
00636 /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00637   {
00638     { 0, 0, 0, 0 },
00639     { { MNEM, ' ', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00640     & ifmt_rcfbcb, { 0xb8000000 }
00641   },
00642 /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00643   {
00644     { 0, 0, 0, 0 },
00645     { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00646     & ifmt_mrcfbcb, { 0xbc000000 }
00647   },
00648 /* cbcast #$mask,#$rc2,#$ctxdisp */
00649   {
00650     { 0, 0, 0, 0 },
00651     { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00652     & ifmt_cbcast, { 0xc0000000 }
00653   },
00654 /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
00655   {
00656     { 0, 0, 0, 0 },
00657     { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (CELL), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00658     & ifmt_dupcbcast, { 0xc4000000 }
00659   },
00660 /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
00661   {
00662     { 0, 0, 0, 0 },
00663     { { MNEM, ' ', '#', OP (BANKADDR), ',', '#', OP (ROWNUM1), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00664     & ifmt_wfbi, { 0xc8000000 }
00665   },
00666 /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
00667   {
00668     { 0, 0, 0, 0 },
00669     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (CTXDISP), 0 } },
00670     & ifmt_wfb, { 0xcc000000 }
00671   },
00672 /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00673   {
00674     { 0, 0, 0, 0 },
00675     { { MNEM, ' ', OP (FRDRRR), ',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00676     & ifmt_rcrisc, { 0xd0000000 }
00677   },
00678 /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00679   {
00680     { 0, 0, 0, 0 },
00681     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00682     & ifmt_fbcbinc, { 0xd4000000 }
00683   },
00684 /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
00685   {
00686     { 0, 0, 0, 0 },
00687     { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (XMODE), ',', '#', OP (MASK1), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00688     & ifmt_rcxmode, { 0xd8000000 }
00689   },
00690 /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
00691   {
00692     { 0, 0, 0, 0 },
00693     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (MODE), ',', OP (FRSR2), ',', '#', OP (ID), ',', '#', OP (SIZE), 0 } },
00694     & ifmt_interleaver, { 0xdc000000 }
00695   },
00696 /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00697   {
00698     { 0, 0, 0, 0 },
00699     { { MNEM, ' ', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00700     & ifmt_wfbinc, { 0xe0000000 }
00701   },
00702 /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00703   {
00704     { 0, 0, 0, 0 },
00705     { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00706     & ifmt_mwfbinc, { 0xe4000000 }
00707   },
00708 /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00709   {
00710     { 0, 0, 0, 0 },
00711     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00712     & ifmt_wfbincr, { 0xe8000000 }
00713   },
00714 /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00715   {
00716     { 0, 0, 0, 0 },
00717     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00718     & ifmt_mwfbincr, { 0xec000000 }
00719   },
00720 /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00721   {
00722     { 0, 0, 0, 0 },
00723     { { MNEM, ' ', '#', OP (PERM), ',', '#', OP (A23), ',', '#', OP (CR), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00724     & ifmt_fbcbincs, { 0xf0000000 }
00725   },
00726 /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00727   {
00728     { 0, 0, 0, 0 },
00729     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00730     & ifmt_mfbcbincs, { 0xf4000000 }
00731   },
00732 /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00733   {
00734     { 0, 0, 0, 0 },
00735     { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00736     & ifmt_fbcbincrs, { 0xf8000000 }
00737   },
00738 /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00739   {
00740     { 0, 0, 0, 0 },
00741     { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } },
00742     & ifmt_mfbcbincrs, { 0xfc000000 }
00743   },
00744 /* loop $frsr1,$loopsize */
00745   {
00746     { 0, 0, 0, 0 },
00747     { { MNEM, ' ', OP (FRSR1), ',', OP (LOOPSIZE), 0 } },
00748     & ifmt_loop, { 0x3e000000 }
00749   },
00750 /* loopi #$imm16l,$loopsize */
00751   {
00752     { 0, 0, 0, 0 },
00753     { { MNEM, ' ', '#', OP (IMM16L), ',', OP (LOOPSIZE), 0 } },
00754     & ifmt_loopi, { 0x3f000000 }
00755   },
00756 /* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
00757   {
00758     { 0, 0, 0, 0 },
00759     { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00760     & ifmt_dfbc, { 0x80000000 }
00761   },
00762 /* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
00763   {
00764     { 0, 0, 0, 0 },
00765     { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00766     & ifmt_dwfb, { 0x84000000 }
00767   },
00768 /* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
00769   {
00770     { 0, 0, 0, 0 },
00771     { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00772     & ifmt_dfbc, { 0x88000000 }
00773   },
00774 /* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
00775   {
00776     { 0, 0, 0, 0 },
00777     { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', OP (FRSR2), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } },
00778     & ifmt_dfbr, { 0x8c000000 }
00779   },
00780 };
00781 
00782 #undef A
00783 #undef OPERAND
00784 #undef MNEM
00785 #undef OP
00786 
00787 /* Formats for ALIAS macro-insns.  */
00788 
00789 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00790 #define F(f) & mt_cgen_ifld_table[MT_##f]
00791 #else
00792 #define F(f) & mt_cgen_ifld_table[MT_f]
00793 #endif
00794 #undef F
00795 
00796 /* Each non-simple macro entry points to an array of expansion possibilities.  */
00797 
00798 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00799 #define A(a) (1 << CGEN_INSN_##a)
00800 #else
00801 #define A(a) (1 << CGEN_INSN_a)
00802 #endif
00803 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00804 #define OPERAND(op) MT_OPERAND_##op
00805 #else
00806 #define OPERAND(op) MT_OPERAND_op
00807 #endif
00808 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
00809 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00810 
00811 /* The macro instruction table.  */
00812 
00813 static const CGEN_IBASE mt_cgen_macro_insn_table[] =
00814 {
00815 };
00816 
00817 /* The macro instruction opcode table.  */
00818 
00819 static const CGEN_OPCODE mt_cgen_macro_insn_opcode_table[] =
00820 {
00821 };
00822 
00823 #undef A
00824 #undef OPERAND
00825 #undef MNEM
00826 #undef OP
00827 
00828 #ifndef CGEN_ASM_HASH_P
00829 #define CGEN_ASM_HASH_P(insn) 1
00830 #endif
00831 
00832 #ifndef CGEN_DIS_HASH_P
00833 #define CGEN_DIS_HASH_P(insn) 1
00834 #endif
00835 
00836 /* Return non-zero if INSN is to be added to the hash table.
00837    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
00838 
00839 static int
00840 asm_hash_insn_p (insn)
00841      const CGEN_INSN *insn ATTRIBUTE_UNUSED;
00842 {
00843   return CGEN_ASM_HASH_P (insn);
00844 }
00845 
00846 static int
00847 dis_hash_insn_p (insn)
00848      const CGEN_INSN *insn;
00849 {
00850   /* If building the hash table and the NO-DIS attribute is present,
00851      ignore.  */
00852   if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
00853     return 0;
00854   return CGEN_DIS_HASH_P (insn);
00855 }
00856 
00857 #ifndef CGEN_ASM_HASH
00858 #define CGEN_ASM_HASH_SIZE 127
00859 #ifdef CGEN_MNEMONIC_OPERANDS
00860 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
00861 #else
00862 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
00863 #endif
00864 #endif
00865 
00866 /* It doesn't make much sense to provide a default here,
00867    but while this is under development we do.
00868    BUFFER is a pointer to the bytes of the insn, target order.
00869    VALUE is the first base_insn_bitsize bits as an int in host order.  */
00870 
00871 #ifndef CGEN_DIS_HASH
00872 #define CGEN_DIS_HASH_SIZE 256
00873 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
00874 #endif
00875 
00876 /* The result is the hash value of the insn.
00877    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
00878 
00879 static unsigned int
00880 asm_hash_insn (mnem)
00881      const char * mnem;
00882 {
00883   return CGEN_ASM_HASH (mnem);
00884 }
00885 
00886 /* BUF is a pointer to the bytes of the insn, target order.
00887    VALUE is the first base_insn_bitsize bits as an int in host order.  */
00888 
00889 static unsigned int
00890 dis_hash_insn (buf, value)
00891      const char * buf ATTRIBUTE_UNUSED;
00892      CGEN_INSN_INT value ATTRIBUTE_UNUSED;
00893 {
00894   return CGEN_DIS_HASH (buf, value);
00895 }
00896 
00897 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
00898 
00899 static void
00900 set_fields_bitsize (CGEN_FIELDS *fields, int size)
00901 {
00902   CGEN_FIELDS_BITSIZE (fields) = size;
00903 }
00904 
00905 /* Function to call before using the operand instance table.
00906    This plugs the opcode entries and macro instructions into the cpu table.  */
00907 
00908 void
00909 mt_cgen_init_opcode_table (CGEN_CPU_DESC cd)
00910 {
00911   int i;
00912   int num_macros = (sizeof (mt_cgen_macro_insn_table) /
00913                   sizeof (mt_cgen_macro_insn_table[0]));
00914   const CGEN_IBASE *ib = & mt_cgen_macro_insn_table[0];
00915   const CGEN_OPCODE *oc = & mt_cgen_macro_insn_opcode_table[0];
00916   CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
00917 
00918   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
00919   for (i = 0; i < num_macros; ++i)
00920     {
00921       insns[i].base = &ib[i];
00922       insns[i].opcode = &oc[i];
00923       mt_cgen_build_insn_regex (& insns[i]);
00924     }
00925   cd->macro_insn_table.init_entries = insns;
00926   cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
00927   cd->macro_insn_table.num_init_entries = num_macros;
00928 
00929   oc = & mt_cgen_insn_opcode_table[0];
00930   insns = (CGEN_INSN *) cd->insn_table.init_entries;
00931   for (i = 0; i < MAX_INSNS; ++i)
00932     {
00933       insns[i].opcode = &oc[i];
00934       mt_cgen_build_insn_regex (& insns[i]);
00935     }
00936 
00937   cd->sizeof_fields = sizeof (CGEN_FIELDS);
00938   cd->set_fields_bitsize = set_fields_bitsize;
00939 
00940   cd->asm_hash_p = asm_hash_insn_p;
00941   cd->asm_hash = asm_hash_insn;
00942   cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
00943 
00944   cd->dis_hash_p = dis_hash_insn_p;
00945   cd->dis_hash = dis_hash_insn;
00946   cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
00947 }