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cell-binutils  2.17cvs20070401
mt-desc.h
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00001 /* CPU data header for mt.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef MT_CPU_H
00026 #define MT_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH mt
00031 
00032 /* Given symbol S, return mt_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) mt##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) mt_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_MS1BF
00042 #define HAVE_CPU_MS1_003BF
00043 #define HAVE_CPU_MS2BF
00044 
00045 #define CGEN_INSN_LSB0_P 1
00046 
00047 /* Minimum size of any insn (in bytes).  */
00048 #define CGEN_MIN_INSN_SIZE 4
00049 
00050 /* Maximum size of any insn (in bytes).  */
00051 #define CGEN_MAX_INSN_SIZE 4
00052 
00053 #define CGEN_INT_INSN_P 1
00054 
00055 /* Maximum number of syntax elements in an instruction.  */
00056 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40
00057 
00058 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00059    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00060    we can't hash on everything up to the space.  */
00061 #define CGEN_MNEMONIC_OPERANDS
00062 
00063 /* Maximum number of fields in an instruction.  */
00064 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14
00065 
00066 /* Enums.  */
00067 
00068 /* Enum declaration for msys enums.  */
00069 typedef enum insn_msys {
00070   MSYS_NO, MSYS_YES
00071 } INSN_MSYS;
00072 
00073 /* Enum declaration for opc enums.  */
00074 typedef enum insn_opc {
00075   OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3
00076  , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10
00077  , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
00078  , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
00079  , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
00080  , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32
00081  , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50
00082  , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53
00083 } INSN_OPC;
00084 
00085 /* Enum declaration for msopc enums.  */
00086 typedef enum insn_msopc {
00087   MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB
00088  , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI
00089  , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI
00090  , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB
00091  , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB
00092  , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR
00093  , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR
00094  , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS
00095 } INSN_MSOPC;
00096 
00097 /* Enum declaration for imm enums.  */
00098 typedef enum insn_imm {
00099   IMM_NO, IMM_YES
00100 } INSN_IMM;
00101 
00102 /* Enum declaration for .  */
00103 typedef enum msys_syms {
00104   H_NIL_DUP = 1, H_NIL_XX = 0
00105 } MSYS_SYMS;
00106 
00107 /* Attributes.  */
00108 
00109 /* Enum declaration for machine type selection.  */
00110 typedef enum mach_attr {
00111   MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2
00112  , MACH_MAX
00113 } MACH_ATTR;
00114 
00115 /* Enum declaration for instruction set selection.  */
00116 typedef enum isa_attr {
00117   ISA_MT, ISA_MAX
00118 } ISA_ATTR;
00119 
00120 /* Number of architecture variants.  */
00121 #define MAX_ISAS  1
00122 #define MAX_MACHS ((int) MACH_MAX)
00123 
00124 /* Ifield support.  */
00125 
00126 /* Ifield attribute indices.  */
00127 
00128 /* Enum declaration for cgen_ifld attrs.  */
00129 typedef enum cgen_ifld_attr {
00130   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00131  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00132  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00133 } CGEN_IFLD_ATTR;
00134 
00135 /* Number of non-boolean elements in cgen_ifld_attr.  */
00136 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00137 
00138 /* cgen_ifld attribute accessor macros.  */
00139 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00140 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00141 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00142 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00143 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00144 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00145 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00146 
00147 /* Enum declaration for mt ifield types.  */
00148 typedef enum ifield_type {
00149   MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC
00150  , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2
00151  , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S
00152  , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12
00153  , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC
00154  , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA
00155  , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE
00156  , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23
00157  , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR
00158  , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19
00159  , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR
00160  , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15
00161  , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX
00162  , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11
00163  , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB
00164  , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM
00165  , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP
00166  , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL
00167  , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2
00168  , MT_F_BRC2, MT_F_BALL2, MT_F_MAX
00169 } IFIELD_TYPE;
00170 
00171 #define MAX_IFLD ((int) MT_F_MAX)
00172 
00173 /* Hardware attribute indices.  */
00174 
00175 /* Enum declaration for cgen_hw attrs.  */
00176 typedef enum cgen_hw_attr {
00177   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00178  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00179 } CGEN_HW_ATTR;
00180 
00181 /* Number of non-boolean elements in cgen_hw_attr.  */
00182 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00183 
00184 /* cgen_hw attribute accessor macros.  */
00185 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00186 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00187 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00188 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00189 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00190 
00191 /* Enum declaration for mt hardware types.  */
00192 typedef enum cgen_hw_type {
00193   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00194  , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX
00195 } CGEN_HW_TYPE;
00196 
00197 #define MAX_HW ((int) HW_MAX)
00198 
00199 /* Operand attribute indices.  */
00200 
00201 /* Enum declaration for cgen_operand attrs.  */
00202 typedef enum cgen_operand_attr {
00203   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00204  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00205  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00206 } CGEN_OPERAND_ATTR;
00207 
00208 /* Number of non-boolean elements in cgen_operand_attr.  */
00209 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00210 
00211 /* cgen_operand attribute accessor macros.  */
00212 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00213 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00214 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00215 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00216 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00217 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00218 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00219 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00220 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00221 
00222 /* Enum declaration for mt operand types.  */
00223 typedef enum cgen_operand_type {
00224   MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR
00225  , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O
00226  , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC
00227  , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2
00228  , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL
00229  , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE
00230  , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE
00231  , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA
00232  , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM
00233  , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR
00234  , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB
00235  , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR
00236  , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL
00237  , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX
00238 } CGEN_OPERAND_TYPE;
00239 
00240 /* Number of operands types.  */
00241 #define MAX_OPERANDS 55
00242 
00243 /* Maximum number of operands referenced by any insn.  */
00244 #define MAX_OPERAND_INSTANCES 8
00245 
00246 /* Insn attribute indices.  */
00247 
00248 /* Enum declaration for cgen_insn attrs.  */
00249 typedef enum cgen_insn_attr {
00250   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00251  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00252  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
00253  , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD
00254  , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2
00255  , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
00256  , CGEN_INSN_END_NBOOLS
00257 } CGEN_INSN_ATTR;
00258 
00259 /* Number of non-boolean elements in cgen_insn_attr.  */
00260 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00261 
00262 /* cgen_insn attribute accessor macros.  */
00263 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00264 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00265 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00266 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00267 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00268 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00269 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00270 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00271 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00272 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00273 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00274 #define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
00275 #define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0)
00276 #define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0)
00277 #define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0)
00278 #define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0)
00279 #define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_JAL_HAZARD)) != 0)
00280 #define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0)
00281 #define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
00282 #define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0)
00283 #define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR2)) != 0)
00284 #define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0)
00285 
00286 /* cgen.h uses things we just defined.  */
00287 #include "opcode/cgen.h"
00288 
00289 extern const struct cgen_ifld mt_cgen_ifld_table[];
00290 
00291 /* Attributes.  */
00292 extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[];
00293 extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[];
00294 extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[];
00295 extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[];
00296 
00297 /* Hardware decls.  */
00298 
00299 extern CGEN_KEYWORD mt_cgen_opval_h_spr;
00300 
00301 extern const CGEN_HW_ENTRY mt_cgen_hw_table[];
00302 
00303 
00304 
00305 #endif /* MT_CPU_H */