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cell-binutils  2.17cvs20070401
mt-desc.c
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00001 /* CPU data for mt.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "mt-desc.h"
00032 #include "mt-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "ms1", MACH_MS1 },
00050   { "ms1_003", MACH_MS1_003 },
00051   { "ms2", MACH_MS2 },
00052   { "max", MACH_MAX },
00053   { 0, 0 }
00054 };
00055 
00056 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00057 {
00058   { "mt", ISA_MT },
00059   { "max", ISA_MAX },
00060   { 0, 0 }
00061 };
00062 
00063 const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] =
00064 {
00065   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00066   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00067   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00068   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00069   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00070   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00071   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00072   { 0, 0, 0 }
00073 };
00074 
00075 const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] =
00076 {
00077   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00078   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00079   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00080   { "PC", &bool_attr[0], &bool_attr[0] },
00081   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00082   { 0, 0, 0 }
00083 };
00084 
00085 const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] =
00086 {
00087   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00088   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00089   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00090   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00091   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00092   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00093   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00094   { "RELAX", &bool_attr[0], &bool_attr[0] },
00095   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00096   { 0, 0, 0 }
00097 };
00098 
00099 const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] =
00100 {
00101   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00102   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00103   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00104   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00105   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00106   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00107   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00108   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00109   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00110   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00111   { "PBB", &bool_attr[0], &bool_attr[0] },
00112   { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
00113   { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] },
00114   { "AL-INSN", &bool_attr[0], &bool_attr[0] },
00115   { "IO-INSN", &bool_attr[0], &bool_attr[0] },
00116   { "BR-INSN", &bool_attr[0], &bool_attr[0] },
00117   { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] },
00118   { "USES-FRDR", &bool_attr[0], &bool_attr[0] },
00119   { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] },
00120   { "USES-FRSR1", &bool_attr[0], &bool_attr[0] },
00121   { "USES-FRSR2", &bool_attr[0], &bool_attr[0] },
00122   { "SKIPA", &bool_attr[0], &bool_attr[0] },
00123   { 0, 0, 0 }
00124 };
00125 
00126 /* Instruction set variants.  */
00127 
00128 static const CGEN_ISA mt_cgen_isa_table[] = {
00129   { "mt", 32, 32, 32, 32 },
00130   { 0, 0, 0, 0, 0 }
00131 };
00132 
00133 /* Machine variants.  */
00134 
00135 static const CGEN_MACH mt_cgen_mach_table[] = {
00136   { "ms1", "ms1", MACH_MS1, 0 },
00137   { "ms1-003", "ms1-003", MACH_MS1_003, 0 },
00138   { "ms2", "ms2", MACH_MS2, 0 },
00139   { 0, 0, 0, 0 }
00140 };
00141 
00142 static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] =
00143 {
00144   { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 },
00145   { "XX", 0, {0, {{{0, 0}}}}, 0, 0 }
00146 };
00147 
00148 CGEN_KEYWORD mt_cgen_opval_msys_syms =
00149 {
00150   & mt_cgen_opval_msys_syms_entries[0],
00151   2,
00152   0, 0, 0, 0, ""
00153 };
00154 
00155 static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] =
00156 {
00157   { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
00158   { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
00159   { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
00160   { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
00161   { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
00162   { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
00163   { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
00164   { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
00165   { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
00166   { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
00167   { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
00168   { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
00169   { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
00170   { "fp", 12, {0, {{{0, 0}}}}, 0, 0 },
00171   { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
00172   { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
00173   { "R14", 14, {0, {{{0, 0}}}}, 0, 0 },
00174   { "ra", 14, {0, {{{0, 0}}}}, 0, 0 },
00175   { "R15", 15, {0, {{{0, 0}}}}, 0, 0 },
00176   { "ira", 15, {0, {{{0, 0}}}}, 0, 0 }
00177 };
00178 
00179 CGEN_KEYWORD mt_cgen_opval_h_spr =
00180 {
00181   & mt_cgen_opval_h_spr_entries[0],
00182   20,
00183   0, 0, 0, 0, ""
00184 };
00185 
00186 
00187 /* The hardware table.  */
00188 
00189 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00190 #define A(a) (1 << CGEN_HW_##a)
00191 #else
00192 #define A(a) (1 << CGEN_HW_a)
00193 #endif
00194 
00195 const CGEN_HW_ENTRY mt_cgen_hw_table[] =
00196 {
00197   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00198   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00199   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00200   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00201   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00202   { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00203   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00204   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00205 };
00206 
00207 #undef A
00208 
00209 
00210 /* The instruction field table.  */
00211 
00212 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00213 #define A(a) (1 << CGEN_IFLD_##a)
00214 #else
00215 #define A(a) (1 << CGEN_IFLD_a)
00216 #endif
00217 
00218 const CGEN_IFLD mt_cgen_ifld_table[] =
00219 {
00220   { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00221   { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00222   { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00223   { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00224   { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00225   { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00226   { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00227   { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00228   { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00229   { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00230   { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00231   { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00232   { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00233   { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00234   { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00235   { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00236   { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00237   { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00238   { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00239   { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00240   { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00241   { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00242   { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00243   { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00244   { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00245   { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00246   { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00247   { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00248   { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00249   { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00250   { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00251   { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00252   { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00253   { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00254   { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00255   { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00256   { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00257   { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00258   { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00259   { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00260   { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00261   { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00262   { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00263   { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00264   { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00265   { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00266   { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00267   { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00268   { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00269   { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00270   { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00271   { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00272   { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00273   { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00274   { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00275   { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00276   { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00277   { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00278   { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00279   { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00280   { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00281   { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00282   { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00283   { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00284   { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00285   { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00286   { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00287   { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00288   { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00289   { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00290   { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00291   { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00292   { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
00293   { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
00294   { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00295   { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00296   { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00297   { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00298   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00299 };
00300 
00301 #undef A
00302 
00303 
00304 
00305 /* multi ifield declarations */
00306 
00307 
00308 
00309 /* multi ifield definitions */
00310 
00311 
00312 /* The operand table.  */
00313 
00314 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00315 #define A(a) (1 << CGEN_OPERAND_##a)
00316 #else
00317 #define A(a) (1 << CGEN_OPERAND_a)
00318 #endif
00319 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00320 #define OPERAND(op) MT_OPERAND_##op
00321 #else
00322 #define OPERAND(op) MT_OPERAND_op
00323 #endif
00324 
00325 const CGEN_OPERAND mt_cgen_operand_table[] =
00326 {
00327 /* pc: program counter */
00328   { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
00329     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } }, 
00330     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00331 /* frsr1: register */
00332   { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
00333     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } }, 
00334     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00335 /* frsr2: register */
00336   { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
00337     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } }, 
00338     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00339 /* frdr: register */
00340   { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
00341     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } }, 
00342     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00343 /* frdrrr: register */
00344   { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
00345     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } }, 
00346     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00347 /* imm16: immediate value - sign extd */
00348   { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
00349     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } }, 
00350     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00351 /* imm16z: immediate value - zero extd */
00352   { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
00353     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } }, 
00354     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00355 /* imm16o: immediate value */
00356   { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
00357     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } }, 
00358     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00359 /* rc: rc */
00360   { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
00361     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } }, 
00362     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00363 /* rcnum: rcnum */
00364   { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
00365     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } }, 
00366     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00367 /* contnum: context number */
00368   { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
00369     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } }, 
00370     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00371 /* rbbc: omega network configuration */
00372   { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
00373     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } }, 
00374     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00375 /* colnum: column number */
00376   { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
00377     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } }, 
00378     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00379 /* rownum: row number */
00380   { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
00381     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } }, 
00382     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00383 /* rownum1: row number */
00384   { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
00385     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } }, 
00386     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00387 /* rownum2: row number */
00388   { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
00389     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } }, 
00390     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00391 /* rc1: rc1 */
00392   { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
00393     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } }, 
00394     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00395 /* rc2: rc2 */
00396   { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
00397     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } }, 
00398     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00399 /* cbrb: data-bus orientation */
00400   { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
00401     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } }, 
00402     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00403 /* cell: cell */
00404   { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
00405     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } }, 
00406     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00407 /* dup: dup */
00408   { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
00409     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } }, 
00410     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00411 /* ctxdisp: context displacement */
00412   { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
00413     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } }, 
00414     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00415 /* fbdisp: frame buffer displacement */
00416   { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
00417     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } }, 
00418     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00419 /* type: type */
00420   { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
00421     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } }, 
00422     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00423 /* mask: mask */
00424   { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
00425     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } }, 
00426     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00427 /* bankaddr: bank address */
00428   { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
00429     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } }, 
00430     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00431 /* incamt: increment amount */
00432   { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
00433     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } }, 
00434     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00435 /* xmode: xmode */
00436   { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
00437     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } }, 
00438     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00439 /* mask1: mask1 */
00440   { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
00441     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } }, 
00442     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00443 /* ball: b_all */
00444   { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
00445     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } }, 
00446     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00447 /* brc: b_r_c */
00448   { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
00449     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } }, 
00450     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00451 /* rda: rd */
00452   { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
00453     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } }, 
00454     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00455 /* wr: wr */
00456   { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
00457     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } }, 
00458     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00459 /* ball2: b_all2 */
00460   { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
00461     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } }, 
00462     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00463 /* brc2: b_r_c2 */
00464   { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
00465     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } }, 
00466     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00467 /* perm: perm */
00468   { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
00469     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } }, 
00470     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00471 /* a23: a23 */
00472   { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
00473     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } }, 
00474     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00475 /* cr: c-r */
00476   { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
00477     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } }, 
00478     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00479 /* cbs: cbs */
00480   { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
00481     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } }, 
00482     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00483 /* incr: incr */
00484   { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
00485     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } }, 
00486     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00487 /* length: length */
00488   { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
00489     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } }, 
00490     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00491 /* cbx: cbx */
00492   { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
00493     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } }, 
00494     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00495 /* ccb: ccb */
00496   { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
00497     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } }, 
00498     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00499 /* cdb: cdb */
00500   { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
00501     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } }, 
00502     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00503 /* mode: mode */
00504   { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
00505     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } }, 
00506     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00507 /* id: i/d */
00508   { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
00509     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } }, 
00510     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00511 /* size: size */
00512   { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
00513     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } }, 
00514     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00515 /* fbincr: fb incr */
00516   { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
00517     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } }, 
00518     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00519 /* loopsize: immediate value */
00520   { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
00521     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } }, 
00522     { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } }  },
00523 /* imm16l: immediate value */
00524   { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
00525     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } }, 
00526     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
00527 /* rc3: rc3 */
00528   { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
00529     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } }, 
00530     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
00531 /* cb1sel: cb1sel */
00532   { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
00533     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } }, 
00534     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
00535 /* cb2sel: cb2sel */
00536   { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
00537     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } }, 
00538     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
00539 /* cb1incr: cb1incr */
00540   { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
00541     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } }, 
00542     { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
00543 /* cb2incr: cb2incr */
00544   { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
00545     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } }, 
00546     { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
00547 /* sentinel */
00548   { 0, 0, 0, 0, 0,
00549     { 0, { (const PTR) 0 } },
00550     { 0, { { { (1<<MACH_BASE), 0 } } } } }
00551 };
00552 
00553 #undef A
00554 
00555 
00556 /* The instruction table.  */
00557 
00558 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00559 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00560 #define A(a) (1 << CGEN_INSN_##a)
00561 #else
00562 #define A(a) (1 << CGEN_INSN_a)
00563 #endif
00564 
00565 static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] =
00566 {
00567   /* Special null first entry.
00568      A `num' value of zero is thus invalid.
00569      Also, the special `invalid' insn resides here.  */
00570   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00571 /* add $frdrrr,$frsr1,$frsr2 */
00572   {
00573     MT_INSN_ADD, "add", "add", 32,
00574     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00575   },
00576 /* addu $frdrrr,$frsr1,$frsr2 */
00577   {
00578     MT_INSN_ADDU, "addu", "addu", 32,
00579     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00580   },
00581 /* addi $frdr,$frsr1,#$imm16 */
00582   {
00583     MT_INSN_ADDI, "addi", "addi", 32,
00584     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00585   },
00586 /* addui $frdr,$frsr1,#$imm16z */
00587   {
00588     MT_INSN_ADDUI, "addui", "addui", 32,
00589     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00590   },
00591 /* sub $frdrrr,$frsr1,$frsr2 */
00592   {
00593     MT_INSN_SUB, "sub", "sub", 32,
00594     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00595   },
00596 /* subu $frdrrr,$frsr1,$frsr2 */
00597   {
00598     MT_INSN_SUBU, "subu", "subu", 32,
00599     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00600   },
00601 /* subi $frdr,$frsr1,#$imm16 */
00602   {
00603     MT_INSN_SUBI, "subi", "subi", 32,
00604     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00605   },
00606 /* subui $frdr,$frsr1,#$imm16z */
00607   {
00608     MT_INSN_SUBUI, "subui", "subui", 32,
00609     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00610   },
00611 /* mul $frdrrr,$frsr1,$frsr2 */
00612   {
00613     MT_INSN_MUL, "mul", "mul", 32,
00614     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00615   },
00616 /* muli $frdr,$frsr1,#$imm16 */
00617   {
00618     MT_INSN_MULI, "muli", "muli", 32,
00619     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00620   },
00621 /* and $frdrrr,$frsr1,$frsr2 */
00622   {
00623     MT_INSN_AND, "and", "and", 32,
00624     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00625   },
00626 /* andi $frdr,$frsr1,#$imm16z */
00627   {
00628     MT_INSN_ANDI, "andi", "andi", 32,
00629     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00630   },
00631 /* or $frdrrr,$frsr1,$frsr2 */
00632   {
00633     MT_INSN_OR, "or", "or", 32,
00634     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00635   },
00636 /* nop */
00637   {
00638     MT_INSN_NOP, "nop", "nop", 32,
00639     { 0, { { { (1<<MACH_BASE), 0 } } } }
00640   },
00641 /* ori $frdr,$frsr1,#$imm16z */
00642   {
00643     MT_INSN_ORI, "ori", "ori", 32,
00644     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00645   },
00646 /* xor $frdrrr,$frsr1,$frsr2 */
00647   {
00648     MT_INSN_XOR, "xor", "xor", 32,
00649     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00650   },
00651 /* xori $frdr,$frsr1,#$imm16z */
00652   {
00653     MT_INSN_XORI, "xori", "xori", 32,
00654     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00655   },
00656 /* nand $frdrrr,$frsr1,$frsr2 */
00657   {
00658     MT_INSN_NAND, "nand", "nand", 32,
00659     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00660   },
00661 /* nandi $frdr,$frsr1,#$imm16z */
00662   {
00663     MT_INSN_NANDI, "nandi", "nandi", 32,
00664     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00665   },
00666 /* nor $frdrrr,$frsr1,$frsr2 */
00667   {
00668     MT_INSN_NOR, "nor", "nor", 32,
00669     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00670   },
00671 /* nori $frdr,$frsr1,#$imm16z */
00672   {
00673     MT_INSN_NORI, "nori", "nori", 32,
00674     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00675   },
00676 /* xnor $frdrrr,$frsr1,$frsr2 */
00677   {
00678     MT_INSN_XNOR, "xnor", "xnor", 32,
00679     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00680   },
00681 /* xnori $frdr,$frsr1,#$imm16z */
00682   {
00683     MT_INSN_XNORI, "xnori", "xnori", 32,
00684     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00685   },
00686 /* ldui $frdr,#$imm16z */
00687   {
00688     MT_INSN_LDUI, "ldui", "ldui", 32,
00689     { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
00690   },
00691 /* lsl $frdrrr,$frsr1,$frsr2 */
00692   {
00693     MT_INSN_LSL, "lsl", "lsl", 32,
00694     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
00695   },
00696 /* lsli $frdr,$frsr1,#$imm16 */
00697   {
00698     MT_INSN_LSLI, "lsli", "lsli", 32,
00699     { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
00700   },
00701 /* lsr $frdrrr,$frsr1,$frsr2 */
00702   {
00703     MT_INSN_LSR, "lsr", "lsr", 32,
00704     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
00705   },
00706 /* lsri $frdr,$frsr1,#$imm16 */
00707   {
00708     MT_INSN_LSRI, "lsri", "lsri", 32,
00709     { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
00710   },
00711 /* asr $frdrrr,$frsr1,$frsr2 */
00712   {
00713     MT_INSN_ASR, "asr", "asr", 32,
00714     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
00715   },
00716 /* asri $frdr,$frsr1,#$imm16 */
00717   {
00718     MT_INSN_ASRI, "asri", "asri", 32,
00719     { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
00720   },
00721 /* brlt $frsr1,$frsr2,$imm16o */
00722   {
00723     MT_INSN_BRLT, "brlt", "brlt", 32,
00724     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
00725   },
00726 /* brle $frsr1,$frsr2,$imm16o */
00727   {
00728     MT_INSN_BRLE, "brle", "brle", 32,
00729     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
00730   },
00731 /* breq $frsr1,$frsr2,$imm16o */
00732   {
00733     MT_INSN_BREQ, "breq", "breq", 32,
00734     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
00735   },
00736 /* brne $frsr1,$frsr2,$imm16o */
00737   {
00738     MT_INSN_BRNE, "brne", "brne", 32,
00739     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
00740   },
00741 /* jmp $imm16o */
00742   {
00743     MT_INSN_JMP, "jmp", "jmp", 32,
00744     { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00745   },
00746 /* jal $frdrrr,$frsr1 */
00747   {
00748     MT_INSN_JAL, "jal", "jal", 32,
00749     { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00750   },
00751 /* dbnz $frsr1,$imm16o */
00752   {
00753     MT_INSN_DBNZ, "dbnz", "dbnz", 32,
00754     { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00755   },
00756 /* ei */
00757   {
00758     MT_INSN_EI, "ei", "ei", 32,
00759     { 0, { { { (1<<MACH_BASE), 0 } } } }
00760   },
00761 /* di */
00762   {
00763     MT_INSN_DI, "di", "di", 32,
00764     { 0, { { { (1<<MACH_BASE), 0 } } } }
00765   },
00766 /* si $frdrrr */
00767   {
00768     MT_INSN_SI, "si", "si", 32,
00769     { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00770   },
00771 /* reti $frsr1 */
00772   {
00773     MT_INSN_RETI, "reti", "reti", 32,
00774     { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00775   },
00776 /* ldw $frdr,$frsr1,#$imm16 */
00777   {
00778     MT_INSN_LDW, "ldw", "ldw", 32,
00779     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
00780   },
00781 /* stw $frsr2,$frsr1,#$imm16 */
00782   {
00783     MT_INSN_STW, "stw", "stw", 32,
00784     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } }
00785   },
00786 /* break */
00787   {
00788     MT_INSN_BREAK, "break", "break", 32,
00789     { 0, { { { (1<<MACH_BASE), 0 } } } }
00790   },
00791 /* iflush */
00792   {
00793     MT_INSN_IFLUSH, "iflush", "iflush", 32,
00794     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00795   },
00796 /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
00797   {
00798     MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
00799     { 0, { { { (1<<MACH_MS1), 0 } } } }
00800   },
00801 /* ldfb $frsr1,$frsr2,#$imm16z */
00802   {
00803     MT_INSN_LDFB, "ldfb", "ldfb", 32,
00804     { 0, { { { (1<<MACH_MS1), 0 } } } }
00805   },
00806 /* stfb $frsr1,$frsr2,#$imm16z */
00807   {
00808     MT_INSN_STFB, "stfb", "stfb", 32,
00809     { 0, { { { (1<<MACH_MS1), 0 } } } }
00810   },
00811 /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00812   {
00813     MT_INSN_FBCB, "fbcb", "fbcb", 32,
00814     { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
00815   },
00816 /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00817   {
00818     MT_INSN_MFBCB, "mfbcb", "mfbcb", 32,
00819     { 0, { { { (1<<MACH_BASE), 0 } } } }
00820   },
00821 /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00822   {
00823     MT_INSN_FBCCI, "fbcci", "fbcci", 32,
00824     { 0, { { { (1<<MACH_BASE), 0 } } } }
00825   },
00826 /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00827   {
00828     MT_INSN_FBRCI, "fbrci", "fbrci", 32,
00829     { 0, { { { (1<<MACH_BASE), 0 } } } }
00830   },
00831 /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00832   {
00833     MT_INSN_FBCRI, "fbcri", "fbcri", 32,
00834     { 0, { { { (1<<MACH_BASE), 0 } } } }
00835   },
00836 /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00837   {
00838     MT_INSN_FBRRI, "fbrri", "fbrri", 32,
00839     { 0, { { { (1<<MACH_BASE), 0 } } } }
00840   },
00841 /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00842   {
00843     MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
00844     { 0, { { { (1<<MACH_BASE), 0 } } } }
00845   },
00846 /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00847   {
00848     MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
00849     { 0, { { { (1<<MACH_BASE), 0 } } } }
00850   },
00851 /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00852   {
00853     MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
00854     { 0, { { { (1<<MACH_BASE), 0 } } } }
00855   },
00856 /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
00857   {
00858     MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
00859     { 0, { { { (1<<MACH_BASE), 0 } } } }
00860   },
00861 /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00862   {
00863     MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
00864     { 0, { { { (1<<MACH_BASE), 0 } } } }
00865   },
00866 /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00867   {
00868     MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
00869     { 0, { { { (1<<MACH_BASE), 0 } } } }
00870   },
00871 /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00872   {
00873     MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
00874     { 0, { { { (1<<MACH_BASE), 0 } } } }
00875   },
00876 /* cbcast #$mask,#$rc2,#$ctxdisp */
00877   {
00878     MT_INSN_CBCAST, "cbcast", "cbcast", 32,
00879     { 0, { { { (1<<MACH_BASE), 0 } } } }
00880   },
00881 /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
00882   {
00883     MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
00884     { 0, { { { (1<<MACH_BASE), 0 } } } }
00885   },
00886 /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
00887   {
00888     MT_INSN_WFBI, "wfbi", "wfbi", 32,
00889     { 0, { { { (1<<MACH_BASE), 0 } } } }
00890   },
00891 /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
00892   {
00893     MT_INSN_WFB, "wfb", "wfb", 32,
00894     { 0, { { { (1<<MACH_BASE), 0 } } } }
00895   },
00896 /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00897   {
00898     MT_INSN_RCRISC, "rcrisc", "rcrisc", 32,
00899     { 0, { { { (1<<MACH_BASE), 0 } } } }
00900   },
00901 /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
00902   {
00903     MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
00904     { 0, { { { (1<<MACH_BASE), 0 } } } }
00905   },
00906 /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
00907   {
00908     MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
00909     { 0, { { { (1<<MACH_BASE), 0 } } } }
00910   },
00911 /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
00912   {
00913     MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
00914     { 0, { { { (1<<MACH_BASE), 0 } } } }
00915   },
00916 /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00917   {
00918     MT_INSN_WFBINC, "wfbinc", "wfbinc", 32,
00919     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00920   },
00921 /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00922   {
00923     MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
00924     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00925   },
00926 /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00927   {
00928     MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
00929     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00930   },
00931 /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
00932   {
00933     MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
00934     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00935   },
00936 /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00937   {
00938     MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
00939     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00940   },
00941 /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00942   {
00943     MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
00944     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00945   },
00946 /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00947   {
00948     MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
00949     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00950   },
00951 /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
00952   {
00953     MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
00954     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
00955   },
00956 /* loop $frsr1,$loopsize */
00957   {
00958     MT_INSN_LOOP, "loop", "loop", 32,
00959     { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
00960   },
00961 /* loopi #$imm16l,$loopsize */
00962   {
00963     MT_INSN_LOOPI, "loopi", "loopi", 32,
00964     { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
00965   },
00966 /* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
00967   {
00968     MT_INSN_DFBC, "dfbc", "dfbc", 32,
00969     { 0, { { { (1<<MACH_MS2), 0 } } } }
00970   },
00971 /* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
00972   {
00973     MT_INSN_DWFB, "dwfb", "dwfb", 32,
00974     { 0, { { { (1<<MACH_MS2), 0 } } } }
00975   },
00976 /* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
00977   {
00978     MT_INSN_FBWFB, "fbwfb", "fbwfb", 32,
00979     { 0, { { { (1<<MACH_MS2), 0 } } } }
00980   },
00981 /* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
00982   {
00983     MT_INSN_DFBR, "dfbr", "dfbr", 32,
00984     { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
00985   },
00986 };
00987 
00988 #undef OP
00989 #undef A
00990 
00991 /* Initialize anything needed to be done once, before any cpu_open call.  */
00992 
00993 static void
00994 init_tables (void)
00995 {
00996 }
00997 
00998 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
00999 static void build_hw_table      (CGEN_CPU_TABLE *);
01000 static void build_ifield_table  (CGEN_CPU_TABLE *);
01001 static void build_operand_table (CGEN_CPU_TABLE *);
01002 static void build_insn_table    (CGEN_CPU_TABLE *);
01003 static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *);
01004 
01005 /* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name.  */
01006 
01007 static const CGEN_MACH *
01008 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
01009 {
01010   while (table->name)
01011     {
01012       if (strcmp (name, table->bfd_name) == 0)
01013        return table;
01014       ++table;
01015     }
01016   abort ();
01017 }
01018 
01019 /* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
01020 
01021 static void
01022 build_hw_table (CGEN_CPU_TABLE *cd)
01023 {
01024   int i;
01025   int machs = cd->machs;
01026   const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0];
01027   /* MAX_HW is only an upper bound on the number of selected entries.
01028      However each entry is indexed by it's enum so there can be holes in
01029      the table.  */
01030   const CGEN_HW_ENTRY **selected =
01031     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01032 
01033   cd->hw_table.init_entries = init;
01034   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01035   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01036   /* ??? For now we just use machs to determine which ones we want.  */
01037   for (i = 0; init[i].name != NULL; ++i)
01038     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01039        & machs)
01040       selected[init[i].type] = &init[i];
01041   cd->hw_table.entries = selected;
01042   cd->hw_table.num_entries = MAX_HW;
01043 }
01044 
01045 /* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
01046 
01047 static void
01048 build_ifield_table (CGEN_CPU_TABLE *cd)
01049 {
01050   cd->ifld_table = & mt_cgen_ifld_table[0];
01051 }
01052 
01053 /* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
01054 
01055 static void
01056 build_operand_table (CGEN_CPU_TABLE *cd)
01057 {
01058   int i;
01059   int machs = cd->machs;
01060   const CGEN_OPERAND *init = & mt_cgen_operand_table[0];
01061   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01062      However each entry is indexed by it's enum so there can be holes in
01063      the table.  */
01064   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
01065 
01066   cd->operand_table.init_entries = init;
01067   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01068   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01069   /* ??? For now we just use mach to determine which ones we want.  */
01070   for (i = 0; init[i].name != NULL; ++i)
01071     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01072        & machs)
01073       selected[init[i].type] = &init[i];
01074   cd->operand_table.entries = selected;
01075   cd->operand_table.num_entries = MAX_OPERANDS;
01076 }
01077 
01078 /* Subroutine of mt_cgen_cpu_open to build the hardware table.
01079    ??? This could leave out insns not supported by the specified mach/isa,
01080    but that would cause errors like "foo only supported by bar" to become
01081    "unknown insn", so for now we include all insns and require the app to
01082    do the checking later.
01083    ??? On the other hand, parsing of such insns may require their hardware or
01084    operand elements to be in the table [which they mightn't be].  */
01085 
01086 static void
01087 build_insn_table (CGEN_CPU_TABLE *cd)
01088 {
01089   int i;
01090   const CGEN_IBASE *ib = & mt_cgen_insn_table[0];
01091   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01092 
01093   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01094   for (i = 0; i < MAX_INSNS; ++i)
01095     insns[i].base = &ib[i];
01096   cd->insn_table.init_entries = insns;
01097   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01098   cd->insn_table.num_init_entries = MAX_INSNS;
01099 }
01100 
01101 /* Subroutine of mt_cgen_cpu_open to rebuild the tables.  */
01102 
01103 static void
01104 mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
01105 {
01106   int i;
01107   CGEN_BITSET *isas = cd->isas;
01108   unsigned int machs = cd->machs;
01109 
01110   cd->int_insn_p = CGEN_INT_INSN_P;
01111 
01112   /* Data derived from the isa spec.  */
01113 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01114   cd->default_insn_bitsize = UNSET;
01115   cd->base_insn_bitsize = UNSET;
01116   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
01117   cd->max_insn_bitsize = 0;
01118   for (i = 0; i < MAX_ISAS; ++i)
01119     if (cgen_bitset_contains (isas, i))
01120       {
01121        const CGEN_ISA *isa = & mt_cgen_isa_table[i];
01122 
01123        /* Default insn sizes of all selected isas must be
01124           equal or we set the result to 0, meaning "unknown".  */
01125        if (cd->default_insn_bitsize == UNSET)
01126          cd->default_insn_bitsize = isa->default_insn_bitsize;
01127        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
01128          ; /* This is ok.  */
01129        else
01130          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
01131 
01132        /* Base insn sizes of all selected isas must be equal
01133           or we set the result to 0, meaning "unknown".  */
01134        if (cd->base_insn_bitsize == UNSET)
01135          cd->base_insn_bitsize = isa->base_insn_bitsize;
01136        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
01137          ; /* This is ok.  */
01138        else
01139          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
01140 
01141        /* Set min,max insn sizes.  */
01142        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
01143          cd->min_insn_bitsize = isa->min_insn_bitsize;
01144        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
01145          cd->max_insn_bitsize = isa->max_insn_bitsize;
01146       }
01147 
01148   /* Data derived from the mach spec.  */
01149   for (i = 0; i < MAX_MACHS; ++i)
01150     if (((1 << i) & machs) != 0)
01151       {
01152        const CGEN_MACH *mach = & mt_cgen_mach_table[i];
01153 
01154        if (mach->insn_chunk_bitsize != 0)
01155        {
01156          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
01157            {
01158              fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
01159                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
01160              abort ();
01161            }
01162 
01163          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
01164        }
01165       }
01166 
01167   /* Determine which hw elements are used by MACH.  */
01168   build_hw_table (cd);
01169 
01170   /* Build the ifield table.  */
01171   build_ifield_table (cd);
01172 
01173   /* Determine which operands are used by MACH/ISA.  */
01174   build_operand_table (cd);
01175 
01176   /* Build the instruction table.  */
01177   build_insn_table (cd);
01178 }
01179 
01180 /* Initialize a cpu table and return a descriptor.
01181    It's much like opening a file, and must be the first function called.
01182    The arguments are a set of (type/value) pairs, terminated with
01183    CGEN_CPU_OPEN_END.
01184 
01185    Currently supported values:
01186    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
01187    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
01188    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
01189    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
01190    CGEN_CPU_OPEN_END:     terminates arguments
01191 
01192    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
01193    precluded.
01194 
01195    ??? We only support ISO C stdargs here, not K&R.
01196    Laziness, plus experiment to see if anything requires K&R - eventually
01197    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01198 
01199 CGEN_CPU_DESC
01200 mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
01201 {
01202   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
01203   static int init_p;
01204   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
01205   unsigned int machs = 0; /* 0 = "unspecified" */
01206   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
01207   va_list ap;
01208 
01209   if (! init_p)
01210     {
01211       init_tables ();
01212       init_p = 1;
01213     }
01214 
01215   memset (cd, 0, sizeof (*cd));
01216 
01217   va_start (ap, arg_type);
01218   while (arg_type != CGEN_CPU_OPEN_END)
01219     {
01220       switch (arg_type)
01221        {
01222        case CGEN_CPU_OPEN_ISAS :
01223          isas = va_arg (ap, CGEN_BITSET *);
01224          break;
01225        case CGEN_CPU_OPEN_MACHS :
01226          machs = va_arg (ap, unsigned int);
01227          break;
01228        case CGEN_CPU_OPEN_BFDMACH :
01229          {
01230            const char *name = va_arg (ap, const char *);
01231            const CGEN_MACH *mach =
01232              lookup_mach_via_bfd_name (mt_cgen_mach_table, name);
01233 
01234            machs |= 1 << mach->num;
01235            break;
01236          }
01237        case CGEN_CPU_OPEN_ENDIAN :
01238          endian = va_arg (ap, enum cgen_endian);
01239          break;
01240        default :
01241          fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n",
01242                  arg_type);
01243          abort (); /* ??? return NULL? */
01244        }
01245       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
01246     }
01247   va_end (ap);
01248 
01249   /* Mach unspecified means "all".  */
01250   if (machs == 0)
01251     machs = (1 << MAX_MACHS) - 1;
01252   /* Base mach is always selected.  */
01253   machs |= 1;
01254   if (endian == CGEN_ENDIAN_UNKNOWN)
01255     {
01256       /* ??? If target has only one, could have a default.  */
01257       fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n");
01258       abort ();
01259     }
01260 
01261   cd->isas = cgen_bitset_copy (isas);
01262   cd->machs = machs;
01263   cd->endian = endian;
01264   /* FIXME: for the sparc case we can determine insn-endianness statically.
01265      The worry here is where both data and insn endian can be independently
01266      chosen, in which case this function will need another argument.
01267      Actually, will want to allow for more arguments in the future anyway.  */
01268   cd->insn_endian = endian;
01269 
01270   /* Table (re)builder.  */
01271   cd->rebuild_tables = mt_cgen_rebuild_tables;
01272   mt_cgen_rebuild_tables (cd);
01273 
01274   /* Default to not allowing signed overflow.  */
01275   cd->signed_overflow_ok_p = 0;
01276   
01277   return (CGEN_CPU_DESC) cd;
01278 }
01279 
01280 /* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01281    MACH_NAME is the bfd name of the mach.  */
01282 
01283 CGEN_CPU_DESC
01284 mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
01285 {
01286   return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01287                             CGEN_CPU_OPEN_ENDIAN, endian,
01288                             CGEN_CPU_OPEN_END);
01289 }
01290 
01291 /* Close a cpu table.
01292    ??? This can live in a machine independent file, but there's currently
01293    no place to put this file (there's no libcgen).  libopcodes is the wrong
01294    place as some simulator ports use this but they don't use libopcodes.  */
01295 
01296 void
01297 mt_cgen_cpu_close (CGEN_CPU_DESC cd)
01298 {
01299   unsigned int i;
01300   const CGEN_INSN *insns;
01301 
01302   if (cd->macro_insn_table.init_entries)
01303     {
01304       insns = cd->macro_insn_table.init_entries;
01305       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01306        if (CGEN_INSN_RX ((insns)))
01307          regfree (CGEN_INSN_RX (insns));
01308     }
01309 
01310   if (cd->insn_table.init_entries)
01311     {
01312       insns = cd->insn_table.init_entries;
01313       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01314        if (CGEN_INSN_RX (insns))
01315          regfree (CGEN_INSN_RX (insns));
01316     }  
01317 
01318   if (cd->macro_insn_table.init_entries)
01319     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01320 
01321   if (cd->insn_table.init_entries)
01322     free ((CGEN_INSN *) cd->insn_table.init_entries);
01323 
01324   if (cd->hw_table.entries)
01325     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01326 
01327   if (cd->operand_table.entries)
01328     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01329 
01330   free (cd);
01331 }
01332