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cell-binutils  2.17cvs20070401
mips16-opc.c
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00001 /* mips16-opc.c.  Mips16 opcode table.
00002    Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc.
00003    Contributed by Ian Lance Taylor, Cygnus Support
00004 
00005 This file is part of GDB, GAS, and the GNU binutils.
00006 
00007 GDB, GAS, and the GNU binutils are free software; you can redistribute
00008 them and/or modify them under the terms of the GNU General Public
00009 License as published by the Free Software Foundation; either version
00010 1, or (at your option) any later version.
00011 
00012 GDB, GAS, and the GNU binutils are distributed in the hope that they
00013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015 the GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this file; see the file COPYING.  If not, write to the Free
00019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00020 02110-1301, USA.  */
00021 
00022 #include <stdio.h>
00023 #include "sysdep.h"
00024 #include "opcode/mips.h"
00025 
00026 /* This is the opcodes table for the mips16 processor.  The format of
00027    this table is intentionally identical to the one in mips-opc.c.
00028    However, the special letters that appear in the argument string are
00029    different, and the table uses some different flags.  */
00030 
00031 /* Use some short hand macros to keep down the length of the lines in
00032    the opcodes table.  */
00033 
00034 #define UBD     INSN_UNCOND_BRANCH_DELAY
00035 #define BR      MIPS16_INSN_BRANCH
00036 
00037 #define WR_x  MIPS16_INSN_WRITE_X
00038 #define WR_y  MIPS16_INSN_WRITE_Y
00039 #define WR_z  MIPS16_INSN_WRITE_Z
00040 #define WR_T  MIPS16_INSN_WRITE_T
00041 #define WR_SP MIPS16_INSN_WRITE_SP
00042 #define WR_31 MIPS16_INSN_WRITE_31
00043 #define WR_Y  MIPS16_INSN_WRITE_GPR_Y
00044 
00045 #define RD_x  MIPS16_INSN_READ_X
00046 #define RD_y  MIPS16_INSN_READ_Y
00047 #define RD_Z  MIPS16_INSN_READ_Z
00048 #define RD_T  MIPS16_INSN_READ_T
00049 #define RD_SP MIPS16_INSN_READ_SP
00050 #define RD_31 MIPS16_INSN_READ_31
00051 #define RD_PC MIPS16_INSN_READ_PC
00052 #define RD_X  MIPS16_INSN_READ_GPR_X
00053 
00054 #define WR_HI INSN_WRITE_HI
00055 #define WR_LO INSN_WRITE_LO
00056 #define RD_HI INSN_READ_HI
00057 #define RD_LO INSN_READ_LO
00058 
00059 #define TRAP  INSN_TRAP
00060 
00061 #define I1    INSN_ISA1
00062 #define I3    INSN_ISA3
00063 #define I32   INSN_ISA32
00064 #define I64   INSN_ISA64
00065 #define T3    INSN_3900
00066 
00067 const struct mips_opcode mips16_opcodes[] =
00068 {
00069 /* name,    args,    match, mask,  pinfo,               pinfo2, membership */
00070 {"nop",           "",              0x6500, 0xffff, RD_Z,              0,     I1 }, /* move $0,$Z */
00071 {"la",     "x,A",    0x0800, 0xf800, WR_x|RD_PC, 0,     I1 },
00072 {"abs",           "x,w",    0, (int) M_ABS, INSN_MACRO, 0,     I1 },
00073 {"addiu",   "y,x,4", 0x4000, 0xf810, WR_y|RD_x,  0,     I1 },
00074 {"addiu",   "x,k",   0x4800, 0xf800, WR_x|RD_x,  0,     I1 },
00075 {"addiu",   "S,K",   0x6300, 0xff00, WR_SP|RD_SP,       0,     I1 },
00076 {"addiu",   "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP,       0,     I1 },
00077 {"addiu",   "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0,     I1 },
00078 {"addiu",   "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0,     I1 },
00079 {"addu",    "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y,    0,     I1 },
00080 {"addu",    "y,x,4", 0x4000, 0xf810, WR_y|RD_x,  0,     I1 },
00081 {"addu",    "x,k",   0x4800, 0xf800, WR_x|RD_x,  0,     I1 },
00082 {"addu",    "S,K",   0x6300, 0xff00, WR_SP|RD_SP,       0,     I1 },
00083 {"addu",    "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP,       0,     I1 },
00084 {"addu",    "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0,     I1 },
00085 {"addu",    "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0,     I1 },
00086 {"and",           "x,y",    0xe80c, 0xf81f, WR_x|RD_x|RD_y,    0,     I1 },
00087 {"b",      "q",      0x1000, 0xf800, BR,         0,     I1 },
00088 {"beq",           "x,y,p",  0, (int) M_BEQ, INSN_MACRO, 0,     I1 },
00089 {"beq",     "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO,      0,     I1 },
00090 {"beqz",    "x,p",   0x2000, 0xf800, BR|RD_x,    0,     I1 },
00091 {"bge",           "x,y,p",  0, (int) M_BGE, INSN_MACRO, 0,     I1 },
00092 {"bge",     "x,8,p", 0, (int) M_BGE_I, INSN_MACRO,      0,     I1 },
00093 {"bgeu",    "x,y,p", 0, (int) M_BGEU, INSN_MACRO,       0,     I1 },
00094 {"bgeu",    "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO,     0,     I1 },
00095 {"bgt",           "x,y,p",  0, (int) M_BGT, INSN_MACRO, 0,     I1 },
00096 {"bgt",     "x,8,p", 0, (int) M_BGT_I, INSN_MACRO,      0,     I1 },
00097 {"bgtu",    "x,y,p", 0, (int) M_BGTU, INSN_MACRO,       0,     I1 },
00098 {"bgtu",    "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO,     0,     I1 },
00099 {"ble",           "x,y,p",  0, (int) M_BLE, INSN_MACRO, 0,     I1 },
00100 {"ble",     "x,8,p", 0, (int) M_BLE_I, INSN_MACRO,      0,     I1 },
00101 {"bleu",    "x,y,p", 0, (int) M_BLEU, INSN_MACRO,       0,     I1 },
00102 {"bleu",    "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO,     0,     I1 },
00103 {"blt",           "x,y,p",  0, (int) M_BLT, INSN_MACRO, 0,     I1 },
00104 {"blt",     "x,8,p", 0, (int) M_BLT_I, INSN_MACRO,      0,     I1 },
00105 {"bltu",    "x,y,p", 0, (int) M_BLTU, INSN_MACRO,       0,     I1 },
00106 {"bltu",    "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO,     0,     I1 },
00107 {"bne",           "x,y,p",  0, (int) M_BNE, INSN_MACRO, 0,     I1 },
00108 {"bne",     "x,U,p", 0, (int) M_BNE_I, INSN_MACRO,      0,     I1 },
00109 {"bnez",    "x,p",   0x2800, 0xf800, BR|RD_x,    0,     I1 },
00110 {"break",   "6",     0xe805, 0xf81f, TRAP,              0,     I1 },
00111 {"bteqz",   "p",     0x6000, 0xff00, BR|RD_T,    0,     I1 },
00112 {"btnez",   "p",     0x6100, 0xff00, BR|RD_T,    0,     I1 },
00113 {"cmpi",    "x,U",   0x7000, 0xf800, WR_T|RD_x,  0,     I1 },
00114 {"cmp",           "x,y",    0xe80a, 0xf81f, WR_T|RD_x|RD_y,    0,     I1 },
00115 {"cmp",     "x,U",   0x7000, 0xf800, WR_T|RD_x,  0,     I1 },
00116 {"dla",           "y,E",    0xfe00, 0xff00, WR_y|RD_PC,        0,     I3 },
00117 {"daddiu",  "y,x,4", 0x4010, 0xf810, WR_y|RD_x,  0,     I3 },
00118 {"daddiu",  "y,j",   0xfd00, 0xff00, WR_y|RD_y,  0,     I3 },
00119 {"daddiu",  "S,K",   0xfb00, 0xff00, WR_SP|RD_SP,       0,     I3 },
00120 {"daddiu",  "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP,       0,     I3 },
00121 {"daddiu",  "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC,        0,     I3 },
00122 {"daddiu",  "y,S,W", 0xff00, 0xff00, WR_y|RD_SP,        0,     I3 },
00123 {"daddu",   "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
00124 {"daddu",   "y,x,4", 0x4010, 0xf810, WR_y|RD_x,  0,     I3 },
00125 {"daddu",   "y,j",   0xfd00, 0xff00, WR_y|RD_y,  0,     I3 },
00126 {"daddu",   "S,K",   0xfb00, 0xff00, WR_SP|RD_SP,       0,     I3 },
00127 {"daddu",   "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP,       0,     I3 },
00128 {"daddu",   "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC,        0,     I3 },
00129 {"daddu",   "y,S,W", 0xff00, 0xff00, WR_y|RD_SP,        0,     I3 },
00130 {"ddiv",    "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I3 },
00131 {"ddiv",    "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO,     0,     I1 },
00132 {"ddivu",   "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
00133 {"ddivu",   "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO,    0,     I1 },
00134 {"div",     "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I1 },
00135 {"div",     "z,v,y", 0, (int) M_DIV_3, INSN_MACRO,      0,     I1 },
00136 {"divu",    "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I1 },
00137 {"divu",    "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO,     0,     I1 },
00138 {"dmul",    "z,v,y", 0, (int) M_DMUL, INSN_MACRO,       0,     I3 },
00139 {"dmult",   "x,y",   0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
00140 {"dmultu",  "x,y",   0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
00141 {"drem",    "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
00142 {"drem",    "z,v,y", 0, (int) M_DREM_3, INSN_MACRO,     0,     I1 },
00143 {"dremu",   "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
00144 {"dremu",   "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO,    0,     I1 },
00145 {"dsllv",   "y,x",   0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
00146 {"dsll",    "x,w,[", 0x3001, 0xf803, WR_x|RD_y,  0,     I3 },
00147 {"dsll",    "y,x",   0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
00148 {"dsrav",   "y,x",   0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
00149 {"dsra",    "y,]",   0xe813, 0xf81f, WR_y|RD_y,  0,     I3 },
00150 {"dsra",    "y,x",   0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
00151 {"dsrlv",   "y,x",   0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
00152 {"dsrl",    "y,]",   0xe808, 0xf81f, WR_y|RD_y,  0,     I3 },
00153 {"dsrl",    "y,x",   0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
00154 {"dsubu",   "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
00155 {"dsubu",   "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO,    0,     I1 },
00156 {"dsubu",   "y,j",   0, (int) M_DSUBU_I_2, INSN_MACRO, 0,      I1 },
00157 {"exit",    "L",     0xed09, 0xff1f, TRAP,              0,     I1 },
00158 {"exit",    "L",     0xee09, 0xff1f, TRAP,              0,     I1 },
00159 {"exit",    "L",     0xef09, 0xff1f, TRAP,              0,     I1 },
00160 {"entry",   "l",     0xe809, 0xf81f, TRAP,              0,     I1 },
00161 {"extend",  "e",     0xf000, 0xf800, 0,          0,     I1 },
00162 {"jalr",    "x",     0xe840, 0xf8ff, UBD|WR_31|RD_x,    0,     I1 },
00163 {"jalr",    "R,x",   0xe840, 0xf8ff, UBD|WR_31|RD_x,    0,     I1 },
00164 {"jal",     "x",     0xe840, 0xf8ff, UBD|WR_31|RD_x,    0,     I1 },
00165 {"jal",     "R,x",   0xe840, 0xf8ff, UBD|WR_31|RD_x,    0,     I1 },
00166 {"jal",           "a",      0x1800, 0xfc00, UBD|WR_31,  0,     I1 },
00167 {"jalx",    "a",     0x1c00, 0xfc00, UBD|WR_31,  0,     I1 },
00168 {"jr",     "x",      0xe800, 0xf8ff, UBD|RD_x,   0,     I1 },
00169 {"jr",     "R",      0xe820, 0xffff, UBD|RD_31,  0,     I1 },
00170 {"j",      "x",      0xe800, 0xf8ff, UBD|RD_x,   0,     I1 },
00171 {"j",      "R",      0xe820, 0xffff, UBD|RD_31,  0,     I1 },
00172 {"lb",     "y,5(x)", 0x8000, 0xf800, WR_y|RD_x,  0,     I1 },
00173 {"lbu",           "y,5(x)", 0xa000, 0xf800, WR_y|RD_x,  0,     I1 },
00174 {"ld",     "y,D(x)", 0x3800, 0xf800, WR_y|RD_x,  0,     I3 },
00175 {"ld",     "y,B",    0xfc00, 0xff00, WR_y|RD_PC,        0,     I3 },
00176 {"ld",     "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC,        0,     I3 },
00177 {"ld",     "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP,        0,     I3 },
00178 {"lh",     "y,H(x)", 0x8800, 0xf800, WR_y|RD_x,  0,     I1 },
00179 {"lhu",           "y,H(x)", 0xa800, 0xf800, WR_y|RD_x,  0,     I1 },
00180 {"li",     "x,U",    0x6800, 0xf800, WR_x,              0,     I1 },
00181 {"lw",     "y,W(x)", 0x9800, 0xf800, WR_y|RD_x,  0,     I1 },
00182 {"lw",     "x,A",    0xb000, 0xf800, WR_x|RD_PC, 0,     I1 },
00183 {"lw",     "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0,     I1 },
00184 {"lw",     "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0,     I1 },
00185 {"lwu",     "y,W(x)",       0xb800, 0xf800, WR_y|RD_x,  0,     I3 },
00186 {"mfhi",    "x",     0xe810, 0xf8ff, WR_x|RD_HI, 0,     I1 },
00187 {"mflo",    "x",     0xe812, 0xf8ff, WR_x|RD_LO, 0,     I1 },
00188 {"move",    "y,X",   0x6700, 0xff00, WR_y|RD_X,  0,     I1 },
00189 {"move",    "Y,Z",   0x6500, 0xff00, WR_Y|RD_Z,  0,     I1 },
00190 {"mul",     "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0,     I1 },
00191 {"mult",    "x,y",   0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I1 },
00192 {"multu",   "x,y",   0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I1 },
00193 {"neg",           "x,w",    0xe80b, 0xf81f, WR_x|RD_y,  0,     I1 },
00194 {"not",           "x,w",    0xe80f, 0xf81f, WR_x|RD_y,  0,     I1 },
00195 {"or",     "x,y",    0xe80d, 0xf81f, WR_x|RD_x|RD_y,    0,     I1 },
00196 {"rem",     "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I1 },
00197 {"rem",     "z,v,y", 0, (int) M_REM_3, INSN_MACRO,      0,     I1 },
00198 {"remu",    "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,    0,     I1 },
00199 {"remu",    "z,v,y", 0, (int) M_REMU_3, INSN_MACRO,     0,     I1 },
00200 {"sb",     "y,5(x)", 0xc000, 0xf800, RD_y|RD_x,  0,     I1 },
00201 {"sd",     "y,D(x)", 0x7800, 0xf800, RD_y|RD_x,  0,     I3 },
00202 {"sd",     "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC,        0,     I3 },
00203 {"sd",     "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC,       0,     I1 },
00204 {"sh",     "y,H(x)", 0xc800, 0xf800, RD_y|RD_x,  0,     I1 },
00205 {"sllv",    "y,x",   0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
00206 {"sll",           "x,w,<",  0x3000, 0xf803, WR_x|RD_y,  0,     I1 },
00207 {"sll",     "y,x",   0xe804, 0xf81f, WR_y|RD_y|RD_x,    0,     I1 },
00208 {"slti",    "x,8",   0x5000, 0xf800, WR_T|RD_x,  0,     I1 },
00209 {"slt",           "x,y",    0xe802, 0xf81f, WR_T|RD_x|RD_y,    0,     I1 },
00210 {"slt",     "x,8",   0x5000, 0xf800, WR_T|RD_x,  0,     I1 },
00211 {"sltiu",   "x,8",   0x5800, 0xf800, WR_T|RD_x,  0,     I1 },
00212 {"sltu",    "x,y",   0xe803, 0xf81f, WR_T|RD_x|RD_y,    0,     I1 },
00213 {"sltu",    "x,8",   0x5800, 0xf800, WR_T|RD_x,  0,     I1 },
00214 {"srav",    "y,x",   0xe807, 0xf81f, WR_y|RD_y|RD_x,    0,     I1 },
00215 {"sra",           "x,w,<",  0x3003, 0xf803, WR_x|RD_y,  0,     I1 },
00216 {"sra",     "y,x",   0xe807, 0xf81f, WR_y|RD_y|RD_x,    0,     I1 },
00217 {"srlv",    "y,x",   0xe806, 0xf81f, WR_y|RD_y|RD_x,    0,     I1 },
00218 {"srl",           "x,w,<",  0x3002, 0xf803, WR_x|RD_y,  0,     I1 },
00219 {"srl",     "y,x",   0xe806, 0xf81f, WR_y|RD_y|RD_x,    0,     I1 },
00220 {"subu",    "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y,    0,     I1 },
00221 {"subu",    "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO,     0,     I1 },
00222 {"subu",    "x,k",   0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 },
00223 {"sw",     "y,W(x)", 0xd800, 0xf800, RD_y|RD_x,  0,     I1 },
00224 {"sw",     "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0,     I1 },
00225 {"sw",     "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP,       0,     I1 },
00226 {"xor",           "x,y",    0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
00227   /* MIPS16e additions */
00228 {"jalrc",   "x",     0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     I32 },
00229 {"jalrc",   "R,x",   0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     I32 },
00230 {"jrc",     "x",     0xe880, 0xf8ff, RD_x|TRAP,  0,      I32 },
00231 {"jrc",     "R",     0xe8a0, 0xffff, RD_31|TRAP, 0,      I32 },
00232 {"restore", "M",     0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP,   0,     I32 },
00233 {"save",    "m",     0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP,   0,     I32 },
00234 {"sdbbp",   "6",     0xe801, 0xf81f, TRAP,              0,     I32 },
00235 {"seb",           "x",      0xe891, 0xf8ff, WR_x|RD_x,  0,      I32 },
00236 {"seh",           "x",      0xe8b1, 0xf8ff, WR_x|RD_x,  0,      I32 },
00237 {"sew",           "x",      0xe8d1, 0xf8ff, WR_x|RD_x,  0,      I64 },
00238 {"zeb",           "x",      0xe811, 0xf8ff, WR_x|RD_x,  0,      I32 },
00239 {"zeh",           "x",      0xe831, 0xf8ff, WR_x|RD_x,  0,      I32 },
00240 {"zew",           "x",      0xe851, 0xf8ff, WR_x|RD_x,  0,      I64 },
00241 };
00242 
00243 const int bfd_mips16_num_opcodes =
00244   ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));