Back to index

cell-binutils  2.17cvs20070401
mips-opc.c
Go to the documentation of this file.
00001 /* mips-opc.c -- MIPS opcode list.
00002    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
00003    2003, 2004, 2005 Free Software Foundation, Inc.
00004    Contributed by Ralph Campbell and OSF
00005    Commented and modified by Ian Lance Taylor, Cygnus Support
00006    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
00007    MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom
00008    Corporation (SiByte).
00009 
00010 This file is part of GDB, GAS, and the GNU binutils.
00011 
00012 GDB, GAS, and the GNU binutils are free software; you can redistribute
00013 them and/or modify them under the terms of the GNU General Public
00014 License as published by the Free Software Foundation; either version
00015 1, or (at your option) any later version.
00016 
00017 GDB, GAS, and the GNU binutils are distributed in the hope that they
00018 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00019 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00020 the GNU General Public License for more details.
00021 
00022 You should have received a copy of the GNU General Public License
00023 along with this file; see the file COPYING.  If not, write to the Free
00024 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00025 
00026 #include <stdio.h>
00027 #include "sysdep.h"
00028 #include "opcode/mips.h"
00029 
00030 /* Short hand so the lines aren't too long.  */
00031 
00032 #define LDD     INSN_LOAD_MEMORY_DELAY
00033 #define LCD   INSN_LOAD_COPROC_DELAY
00034 #define UBD     INSN_UNCOND_BRANCH_DELAY
00035 #define CBD   INSN_COND_BRANCH_DELAY
00036 #define COD     INSN_COPROC_MOVE_DELAY
00037 #define CLD   INSN_COPROC_MEMORY_DELAY
00038 #define CBL   INSN_COND_BRANCH_LIKELY
00039 #define TRAP  INSN_TRAP
00040 #define SM    INSN_STORE_MEMORY
00041 
00042 #define WR_d    INSN_WRITE_GPR_D
00043 #define WR_t    INSN_WRITE_GPR_T
00044 #define WR_31   INSN_WRITE_GPR_31
00045 #define WR_D    INSN_WRITE_FPR_D
00046 #define WR_T  INSN_WRITE_FPR_T
00047 #define WR_S  INSN_WRITE_FPR_S
00048 #define RD_s    INSN_READ_GPR_S
00049 #define RD_b    INSN_READ_GPR_S
00050 #define RD_t    INSN_READ_GPR_T
00051 #define RD_S    INSN_READ_FPR_S
00052 #define RD_T    INSN_READ_FPR_T
00053 #define RD_R  INSN_READ_FPR_R
00054 #define WR_CC INSN_WRITE_COND_CODE
00055 #define RD_CC INSN_READ_COND_CODE
00056 #define RD_C0   INSN_COP
00057 #define RD_C1 INSN_COP
00058 #define RD_C2   INSN_COP
00059 #define RD_C3   INSN_COP
00060 #define WR_C0   INSN_COP
00061 #define WR_C1 INSN_COP
00062 #define WR_C2   INSN_COP
00063 #define WR_C3   INSN_COP
00064 
00065 #define WR_HI INSN_WRITE_HI
00066 #define RD_HI INSN_READ_HI
00067 #define MOD_HI  WR_HI|RD_HI
00068 
00069 #define WR_LO INSN_WRITE_LO
00070 #define RD_LO INSN_READ_LO
00071 #define MOD_LO  WR_LO|RD_LO
00072 
00073 #define WR_HILO WR_HI|WR_LO
00074 #define RD_HILO RD_HI|RD_LO
00075 #define MOD_HILO WR_HILO|RD_HILO
00076 
00077 #define IS_M    INSN_MULT
00078 
00079 #define WR_MACC INSN2_WRITE_MDMX_ACC
00080 #define RD_MACC INSN2_READ_MDMX_ACC
00081 
00082 #define I1    INSN_ISA1
00083 #define I2    INSN_ISA2
00084 #define I3    INSN_ISA3
00085 #define I4    INSN_ISA4
00086 #define I5    INSN_ISA5
00087 #define I32   INSN_ISA32
00088 #define I64     INSN_ISA64
00089 #define I33   INSN_ISA32R2
00090 #define I65   INSN_ISA64R2
00091 
00092 /* MIPS16 ASE support.  */
00093 #define I16     INSN_MIPS16
00094 
00095 /* MIPS64 MIPS-3D ASE support.  */
00096 #define M3D     INSN_MIPS3D
00097 
00098 /* MIPS32 SmartMIPS ASE support.  */
00099 #define SMT   INSN_SMARTMIPS
00100 
00101 /* MIPS64 MDMX ASE support.  */
00102 #define MX      INSN_MDMX
00103 
00104 #define P3    INSN_4650
00105 #define L1    INSN_4010
00106 #define V1    (INSN_4100 | INSN_4111 | INSN_4120)
00107 #define T3      INSN_3900
00108 #define M1    INSN_10000
00109 #define SB1     INSN_SB1
00110 #define N411  INSN_4111
00111 #define N412  INSN_4120
00112 #define N5    (INSN_5400 | INSN_5500)
00113 #define N54   INSN_5400
00114 #define N55   INSN_5500
00115 
00116 #define G1      (T3             \
00117                  )
00118 
00119 #define G2      (T3             \
00120                  )
00121 
00122 #define G3      (I4             \
00123                  )
00124 
00125 /* MIPS DSP ASE support.
00126    NOTE:
00127    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
00128    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
00129    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
00130    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
00131    (RD_HILO) attributes, such that HILO dependencies are maintained
00132    conservatively.
00133 
00134    2. For some mul. instructions that use integer registers as destinations
00135    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
00136 
00137    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
00138    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
00139    certain fields of the DSP control register.  For simplicity, we decide not
00140    to track dependencies of these fields.
00141    However, "bposge32" is a branch instruction that depends on the "pos"
00142    field.  In order to make sure that GAS does not reorder DSP instructions
00143    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
00144    attribute to those instructions that write the "pos" field.  */
00145 
00146 #define WR_a  WR_HILO       /* Write dsp accumulators (reuse WR_HILO)  */
00147 #define RD_a  RD_HILO       /* Read dsp accumulators (reuse RD_HILO)  */
00148 #define MOD_a WR_a|RD_a
00149 #define DSP_VOLA     INSN_TRAP
00150 #define D32   INSN_DSP
00151 #define D33   INSN_DSPR2
00152 #define D64   INSN_DSP64
00153 
00154 /* MIPS MT ASE support.  */
00155 #define MT32  INSN_MT
00156 
00157 /* The order of overloaded instructions matters.  Label arguments and
00158    register arguments look the same. Instructions that can have either
00159    for arguments must apear in the correct order in this table for the
00160    assembler to pick the right one. In other words, entries with
00161    immediate operands must apear after the same instruction with
00162    registers.
00163 
00164    Because of the lookup algorithm used, entries with the same opcode
00165    name must be contiguous.
00166  
00167    Many instructions are short hand for other instructions (i.e., The
00168    jal <register> instruction is short for jalr <register>).  */
00169 
00170 const struct mips_opcode mips_builtin_opcodes[] =
00171 {
00172 /* These instructions appear first so that the disassembler will find
00173    them first.  The assemblers uses a hash table based on the
00174    instruction name anyhow.  */
00175 /* name,    args,    match,     mask,     pinfo,               pinfo2,              membership */
00176 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                 0,            I4|I32|G3     },
00177 {"prefx",   "h,t(b)",       0x4c00000f, 0xfc0007ff, RD_b|RD_t,        0,            I4|I33 },
00178 {"nop",     "",         0x00000000, 0xffffffff, 0,                    INSN2_ALIAS,  I1      }, /* sll */
00179 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                    INSN2_ALIAS,  I32|N55       }, /* sll */
00180 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                    INSN2_ALIAS,  I33    }, /* sll */
00181 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                 INSN2_ALIAS,  I1     }, /* addiu */
00182 {"li",     "t,i",    0x34000000, 0xffe00000, WR_t,                    INSN2_ALIAS,  I1     }, /* ori */
00183 {"li",      "t,I",   0,    (int) M_LI,    INSN_MACRO,          0,            I1     },
00184 {"move",    "d,s",   0,    (int) M_MOVE,  INSN_MACRO,          0,            I1     },
00185 {"move",    "d,s",   0x0000002d, 0xfc1f07ff, WR_d|RD_s,        INSN2_ALIAS,  I3     },/* daddu */
00186 {"move",    "d,s",   0x00000021, 0xfc1f07ff, WR_d|RD_s,        INSN2_ALIAS,  I1     },/* addu */
00187 {"move",    "d,s",   0x00000025, 0xfc1f07ff,     WR_d|RD_s,           INSN2_ALIAS,  I1     },/* or */
00188 {"b",       "p",     0x10000000, 0xffff0000,     UBD,                 INSN2_ALIAS,  I1     },/* beq 0,0 */
00189 {"b",       "p",     0x04010000, 0xffff0000,     UBD,                 INSN2_ALIAS,  I1     },/* bgez 0 */
00190 {"bal",     "p",     0x04110000, 0xffff0000,     UBD|WR_31,           INSN2_ALIAS,  I1     },/* bgezal 0*/
00191 
00192 {"abs",     "d,v",   0,    (int) M_ABS,   INSN_MACRO,          0,            I1     },
00193 {"abs.s",   "D,V",   0x46000005, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I1     },
00194 {"abs.d",   "D,V",   0x46200005, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I1     },
00195 {"abs.ps",  "D,V",   0x46c00005, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I5|I33 },
00196 {"add",     "d,v,t", 0x00000020, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
00197 {"add",     "t,r,I", 0,    (int) M_ADD_I, INSN_MACRO,          0,            I1     },
00198 {"add.s",   "D,V,T", 0x46000000, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            I1     },
00199 {"add.d",   "D,V,T", 0x46200000, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I1     },
00200 {"add.ob",  "X,Y,Q", 0x7800000b, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00201 {"add.ob",  "D,S,T", 0x4ac0000b, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00202 {"add.ob",  "D,S,T[e]",     0x4800000b, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00203 {"add.ob",  "D,S,k", 0x4bc0000b, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00204 {"add.ps",  "D,V,T", 0x46c00000, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
00205 {"add.qh",  "X,Y,Q", 0x7820000b, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00206 {"adda.ob", "Y,Q",   0x78000037, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
00207 {"adda.qh", "Y,Q",   0x78200037, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
00208 {"addi",    "t,r,j", 0x20000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
00209 {"addiu",   "t,r,j", 0x24000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
00210 {"addl.ob", "Y,Q",   0x78000437, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
00211 {"addl.qh", "Y,Q",   0x78200437, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
00212 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            M3D    },
00213 {"addu",    "d,v,t", 0x00000021, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
00214 {"addu",    "t,r,I", 0,    (int) M_ADDU_I,       INSN_MACRO,          0,            I1     },
00215 {"alni.ob", "X,Y,Z,O",      0x78000018, 0xff00003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00216 {"alni.ob", "D,S,T,%",      0x48000018, 0xff00003f,     WR_D|RD_S|RD_T,      0,            N54    },
00217 {"alni.qh", "X,Y,Z,O",      0x7800001a, 0xff00003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00218 {"alnv.ps", "D,V,T,s",      0x4c00001e, 0xfc00003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
00219 {"alnv.ob", "X,Y,Z,s",      0x78000019, 0xfc00003f,     WR_D|RD_S|RD_T|RD_s|FP_D, 0,              MX|SB1 },
00220 {"alnv.qh", "X,Y,Z,s",      0x7800001b, 0xfc00003f,     WR_D|RD_S|RD_T|RD_s|FP_D, 0,              MX     },
00221 {"and",     "d,v,t", 0x00000024, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
00222 {"and",     "t,r,I", 0,    (int) M_AND_I, INSN_MACRO,          0,            I1     },
00223 {"and.ob",  "X,Y,Q", 0x7800000c, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00224 {"and.ob",  "D,S,T", 0x4ac0000c, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00225 {"and.ob",  "D,S,T[e]",     0x4800000c, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00226 {"and.ob",  "D,S,k", 0x4bc0000c, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00227 {"and.qh",  "X,Y,Q", 0x7820000c, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00228 {"andi",    "t,r,i", 0x30000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
00229 /* b is at the top of the table.  */
00230 /* bal is at the top of the table.  */
00231 /* bc0[tf]l? are at the bottom of the table.  */
00232 {"bc1any2f", "N,p",  0x45200000, 0xffe30000,     CBD|RD_CC|FP_S,             0,            M3D    },
00233 {"bc1any2t", "N,p",  0x45210000, 0xffe30000,     CBD|RD_CC|FP_S,             0,            M3D    },
00234 {"bc1any4f", "N,p",  0x45400000, 0xffe30000,     CBD|RD_CC|FP_S,             0,            M3D    },
00235 {"bc1any4t", "N,p",  0x45410000, 0xffe30000,     CBD|RD_CC|FP_S,             0,            M3D    },
00236 {"bc1f",    "p",     0x45000000, 0xffff0000,     CBD|RD_CC|FP_S,             0,            I1     },
00237 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,       0,            I4|I32 },
00238 {"bc1fl",   "p",     0x45020000, 0xffff0000,     CBL|RD_CC|FP_S,             0,            I2|T3  },
00239 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,       0,            I4|I32 },
00240 {"bc1t",    "p",     0x45010000, 0xffff0000,     CBD|RD_CC|FP_S,             0,            I1     },
00241 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,       0,            I4|I32 },
00242 {"bc1tl",   "p",     0x45030000, 0xffff0000,     CBL|RD_CC|FP_S,             0,            I2|T3  },
00243 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,       0,            I4|I32 },
00244 /* bc2* are at the bottom of the table.  */
00245 /* bc3* are at the bottom of the table.  */
00246 {"beqz",    "s,p",   0x10000000, 0xfc1f0000,     CBD|RD_s,            0,            I1     },
00247 {"beqzl",   "s,p",   0x50000000, 0xfc1f0000,     CBL|RD_s,            0,            I2|T3  },
00248 {"beq",     "s,t,p", 0x10000000, 0xfc000000,     CBD|RD_s|RD_t,              0,            I1     },
00249 {"beq",     "s,I,p", 0,    (int) M_BEQ_I, INSN_MACRO,          0,            I1     },
00250 {"beql",    "s,t,p", 0x50000000, 0xfc000000,     CBL|RD_s|RD_t,              0,            I2|T3  },
00251 {"beql",    "s,I,p", 0,    (int) M_BEQL_I,       INSN_MACRO,          0,            I2|T3  },
00252 {"bge",     "s,t,p", 0,    (int) M_BGE,   INSN_MACRO,          0,            I1     },
00253 {"bge",     "s,I,p", 0,    (int) M_BGE_I, INSN_MACRO,          0,            I1     },
00254 {"bgel",    "s,t,p", 0,    (int) M_BGEL,  INSN_MACRO,          0,            I2|T3  },
00255 {"bgel",    "s,I,p", 0,    (int) M_BGEL_I,       INSN_MACRO,          0,            I2|T3  },
00256 {"bgeu",    "s,t,p", 0,    (int) M_BGEU,  INSN_MACRO,          0,            I1     },
00257 {"bgeu",    "s,I,p", 0,    (int) M_BGEU_I,       INSN_MACRO,          0,            I1     },
00258 {"bgeul",   "s,t,p", 0,    (int) M_BGEUL, INSN_MACRO,          0,            I2|T3  },
00259 {"bgeul",   "s,I,p", 0,    (int) M_BGEUL_I,      INSN_MACRO,          0,            I2|T3  },
00260 {"bgez",    "s,p",   0x04010000, 0xfc1f0000,     CBD|RD_s,            0,            I1     },
00261 {"bgezl",   "s,p",   0x04030000, 0xfc1f0000,     CBL|RD_s,            0,            I2|T3  },
00262 {"bgezal",  "s,p",   0x04110000, 0xfc1f0000,     CBD|RD_s|WR_31,             0,            I1     },
00263 {"bgezall", "s,p",   0x04130000, 0xfc1f0000,     CBL|RD_s|WR_31,             0,            I2|T3  },
00264 {"bgt",     "s,t,p", 0,    (int) M_BGT,   INSN_MACRO,          0,            I1     },
00265 {"bgt",     "s,I,p", 0,    (int) M_BGT_I, INSN_MACRO,          0,            I1     },
00266 {"bgtl",    "s,t,p", 0,    (int) M_BGTL,  INSN_MACRO,          0,            I2|T3  },
00267 {"bgtl",    "s,I,p", 0,    (int) M_BGTL_I,       INSN_MACRO,          0,            I2|T3  },
00268 {"bgtu",    "s,t,p", 0,    (int) M_BGTU,  INSN_MACRO,          0,            I1     },
00269 {"bgtu",    "s,I,p", 0,    (int) M_BGTU_I,       INSN_MACRO,          0,            I1     },
00270 {"bgtul",   "s,t,p", 0,    (int) M_BGTUL, INSN_MACRO,          0,            I2|T3  },
00271 {"bgtul",   "s,I,p", 0,    (int) M_BGTUL_I,      INSN_MACRO,          0,            I2|T3  },
00272 {"bgtz",    "s,p",   0x1c000000, 0xfc1f0000,     CBD|RD_s,            0,            I1     },
00273 {"bgtzl",   "s,p",   0x5c000000, 0xfc1f0000,     CBL|RD_s,            0,            I2|T3  },
00274 {"ble",     "s,t,p", 0,    (int) M_BLE,   INSN_MACRO,          0,            I1     },
00275 {"ble",     "s,I,p", 0,    (int) M_BLE_I, INSN_MACRO,          0,            I1     },
00276 {"blel",    "s,t,p", 0,    (int) M_BLEL,  INSN_MACRO,          0,            I2|T3  },
00277 {"blel",    "s,I,p", 0,    (int) M_BLEL_I,       INSN_MACRO,          0,            I2|T3  },
00278 {"bleu",    "s,t,p", 0,    (int) M_BLEU,  INSN_MACRO,          0,            I1     },
00279 {"bleu",    "s,I,p", 0,    (int) M_BLEU_I,       INSN_MACRO,          0,            I1     },
00280 {"bleul",   "s,t,p", 0,    (int) M_BLEUL, INSN_MACRO,          0,            I2|T3  },
00281 {"bleul",   "s,I,p", 0,    (int) M_BLEUL_I,      INSN_MACRO,          0,            I2|T3  },
00282 {"blez",    "s,p",   0x18000000, 0xfc1f0000,     CBD|RD_s,            0,            I1     },
00283 {"blezl",   "s,p",   0x58000000, 0xfc1f0000,     CBL|RD_s,            0,            I2|T3  },
00284 {"blt",     "s,t,p", 0,    (int) M_BLT,   INSN_MACRO,          0,            I1     },
00285 {"blt",     "s,I,p", 0,    (int) M_BLT_I, INSN_MACRO,          0,            I1     },
00286 {"bltl",    "s,t,p", 0,    (int) M_BLTL,  INSN_MACRO,          0,            I2|T3  },
00287 {"bltl",    "s,I,p", 0,    (int) M_BLTL_I,       INSN_MACRO,          0,            I2|T3  },
00288 {"bltu",    "s,t,p", 0,    (int) M_BLTU,  INSN_MACRO,          0,            I1     },
00289 {"bltu",    "s,I,p", 0,    (int) M_BLTU_I,       INSN_MACRO,          0,            I1     },
00290 {"bltul",   "s,t,p", 0,    (int) M_BLTUL, INSN_MACRO,          0,            I2|T3  },
00291 {"bltul",   "s,I,p", 0,    (int) M_BLTUL_I,      INSN_MACRO,          0,            I2|T3  },
00292 {"bltz",    "s,p",   0x04000000, 0xfc1f0000,     CBD|RD_s,            0,            I1     },
00293 {"bltzl",   "s,p",   0x04020000, 0xfc1f0000,     CBL|RD_s,            0,            I2|T3  },
00294 {"bltzal",  "s,p",   0x04100000, 0xfc1f0000,     CBD|RD_s|WR_31,             0,            I1     },
00295 {"bltzall", "s,p",   0x04120000, 0xfc1f0000,     CBL|RD_s|WR_31,             0,            I2|T3  },
00296 {"bnez",    "s,p",   0x14000000, 0xfc1f0000,     CBD|RD_s,            0,            I1     },
00297 {"bnezl",   "s,p",   0x54000000, 0xfc1f0000,     CBL|RD_s,            0,            I2|T3  },
00298 {"bne",     "s,t,p", 0x14000000, 0xfc000000,     CBD|RD_s|RD_t,              0,            I1     },
00299 {"bne",     "s,I,p", 0,    (int) M_BNE_I, INSN_MACRO,          0,            I1     },
00300 {"bnel",    "s,t,p", 0x54000000, 0xfc000000,     CBL|RD_s|RD_t,              0,            I2|T3  },
00301 {"bnel",    "s,I,p", 0,    (int) M_BNEL_I,       INSN_MACRO,          0,            I2|T3  },
00302 {"break",   "",             0x0000000d, 0xffffffff,     TRAP,                0,            I1     },
00303 {"break",   "c",     0x0000000d, 0xfc00ffff,     TRAP,                0,            I1     },
00304 {"break",   "c,q",   0x0000000d, 0xfc00003f,     TRAP,                0,            I1     },
00305 {"c.f.d",   "S,T",   0x46200030, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00306 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00307 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00308 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00309 {"c.f.ps",  "S,T",   0x46c00030, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00310 {"c.f.ps",  "M,S,T", 0x46c00030, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00311 {"c.un.d",  "S,T",   0x46200031, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00312 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00313 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00314 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00315 {"c.un.ps", "S,T",   0x46c00031, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00316 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00317 {"c.eq.d",  "S,T",   0x46200032, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00318 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00319 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00320 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00321 {"c.eq.ob", "Y,Q",   0x78000001, 0xfc2007ff,     WR_CC|RD_S|RD_T|FP_D,       0,            MX|SB1 },
00322 {"c.eq.ob", "S,T",   0x4ac00001, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00323 {"c.eq.ob", "S,T[e]",       0x48000001, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00324 {"c.eq.ob", "S,k",   0x4bc00001, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00325 {"c.eq.ps", "S,T",   0x46c00032, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00326 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00327 {"c.eq.qh", "Y,Q",   0x78200001, 0xfc2007ff,     WR_CC|RD_S|RD_T|FP_D,       0,            MX     },
00328 {"c.ueq.d", "S,T",   0x46200033, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00329 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00330 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00331 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00332 {"c.ueq.ps","S,T",   0x46c00033, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00333 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00334 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,          I1      },
00335 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00336 {"c.olt.s", "S,T",   0x46000034, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_S,       0,            I1     },
00337 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00338 {"c.olt.ps","S,T",   0x46c00034, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00339 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00340 {"c.ult.d", "S,T",   0x46200035, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00341 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00342 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00343 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00344 {"c.ult.ps","S,T",   0x46c00035, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00345 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00346 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,          I1      },
00347 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00348 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00349 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00350 {"c.ole.ps","S,T",   0x46c00036, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00351 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00352 {"c.ule.d", "S,T",   0x46200037, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00353 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00354 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00355 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00356 {"c.ule.ps","S,T",   0x46c00037, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00357 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00358 {"c.sf.d",  "S,T",   0x46200038, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00359 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00360 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00361 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00362 {"c.sf.ps", "S,T",   0x46c00038, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00363 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00364 {"c.ngle.d","S,T",   0x46200039, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00365 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00366 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00367 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00368 {"c.ngle.ps","S,T",  0x46c00039, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00369 {"c.ngle.ps","M,S,T",       0x46c00039, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00370 {"c.seq.d", "S,T",   0x4620003a, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00371 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00372 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00373 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00374 {"c.seq.ps","S,T",   0x46c0003a, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00375 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00376 {"c.ngl.d", "S,T",   0x4620003b, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00377 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00378 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00379 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00380 {"c.ngl.ps","S,T",   0x46c0003b, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00381 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00382 {"c.lt.d",  "S,T",   0x4620003c, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00383 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00384 {"c.lt.s",  "S,T",   0x4600003c, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_S,       0,            I1     },
00385 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00386 {"c.lt.ob", "Y,Q",   0x78000004, 0xfc2007ff,     WR_CC|RD_S|RD_T|FP_D,       0,            MX|SB1 },
00387 {"c.lt.ob", "S,T",   0x4ac00004, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00388 {"c.lt.ob", "S,T[e]",       0x48000004, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00389 {"c.lt.ob", "S,k",   0x4bc00004, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00390 {"c.lt.ps", "S,T",   0x46c0003c, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00391 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00392 {"c.lt.qh", "Y,Q",   0x78200004, 0xfc2007ff,     WR_CC|RD_S|RD_T|FP_D,       0,            MX     },
00393 {"c.nge.d", "S,T",   0x4620003d, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00394 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00395 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00396 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00397 {"c.nge.ps","S,T",   0x46c0003d, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00398 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00399 {"c.le.d",  "S,T",   0x4620003e, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00400 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00401 {"c.le.s",  "S,T",   0x4600003e, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_S,       0,            I1     },
00402 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00403 {"c.le.ob", "Y,Q",   0x78000005, 0xfc2007ff,     WR_CC|RD_S|RD_T|FP_D,       0,            MX|SB1 },
00404 {"c.le.ob", "S,T",   0x4ac00005, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00405 {"c.le.ob", "S,T[e]",       0x48000005, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00406 {"c.le.ob", "S,k",   0x4bc00005, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00407 {"c.le.ps", "S,T",   0x46c0003e, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00408 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00409 {"c.le.qh", "Y,Q",   0x78200005, 0xfc2007ff,     WR_CC|RD_S|RD_T|FP_D,       0,            MX     },
00410 {"c.ngt.d", "S,T",   0x4620003f, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I1     },
00411 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,          I4|I32 },
00412 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,          I1      },
00413 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,          I4|I32 },
00414 {"c.ngt.ps","S,T",   0x46c0003f, 0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00415 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            I5|I33 },
00416 {"cabs.eq.d",  "M,S,T",     0x46200072, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00417 {"cabs.eq.ps", "M,S,T",     0x46c00072, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00418 {"cabs.eq.s",  "M,S,T",     0x46000072, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00419 {"cabs.f.d",   "M,S,T",     0x46200070, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00420 {"cabs.f.ps",  "M,S,T",     0x46c00070, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00421 {"cabs.f.s",   "M,S,T",     0x46000070, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00422 {"cabs.le.d",  "M,S,T",     0x4620007e, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00423 {"cabs.le.ps", "M,S,T",     0x46c0007e, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00424 {"cabs.le.s",  "M,S,T",     0x4600007e, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00425 {"cabs.lt.d",  "M,S,T",     0x4620007c, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00426 {"cabs.lt.ps", "M,S,T",     0x46c0007c, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00427 {"cabs.lt.s",  "M,S,T",     0x4600007c, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00428 {"cabs.nge.d", "M,S,T",     0x4620007d, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00429 {"cabs.nge.ps","M,S,T",     0x46c0007d, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00430 {"cabs.nge.s", "M,S,T",     0x4600007d, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00431 {"cabs.ngl.d", "M,S,T",     0x4620007b, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00432 {"cabs.ngl.ps","M,S,T",     0x46c0007b, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00433 {"cabs.ngl.s", "M,S,T",     0x4600007b, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00434 {"cabs.ngle.d","M,S,T",     0x46200079, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00435 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,  RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00436 {"cabs.ngle.s","M,S,T",     0x46000079, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00437 {"cabs.ngt.d", "M,S,T",     0x4620007f, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00438 {"cabs.ngt.ps","M,S,T",     0x46c0007f, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00439 {"cabs.ngt.s", "M,S,T",     0x4600007f, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00440 {"cabs.ole.d", "M,S,T",     0x46200076, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00441 {"cabs.ole.ps","M,S,T",     0x46c00076, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00442 {"cabs.ole.s", "M,S,T",     0x46000076, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00443 {"cabs.olt.d", "M,S,T",     0x46200074, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00444 {"cabs.olt.ps","M,S,T",     0x46c00074, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00445 {"cabs.olt.s", "M,S,T",     0x46000074, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00446 {"cabs.seq.d", "M,S,T",     0x4620007a, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00447 {"cabs.seq.ps","M,S,T",     0x46c0007a, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00448 {"cabs.seq.s", "M,S,T",     0x4600007a, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00449 {"cabs.sf.d",  "M,S,T",     0x46200078, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00450 {"cabs.sf.ps", "M,S,T",     0x46c00078, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00451 {"cabs.sf.s",  "M,S,T",     0x46000078, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00452 {"cabs.ueq.d", "M,S,T",     0x46200073, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00453 {"cabs.ueq.ps","M,S,T",     0x46c00073, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00454 {"cabs.ueq.s", "M,S,T",     0x46000073, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00455 {"cabs.ule.d", "M,S,T",     0x46200077, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00456 {"cabs.ule.ps","M,S,T",     0x46c00077, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00457 {"cabs.ule.s", "M,S,T",     0x46000077, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00458 {"cabs.ult.d", "M,S,T",     0x46200075, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00459 {"cabs.ult.ps","M,S,T",     0x46c00075, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00460 {"cabs.ult.s", "M,S,T",     0x46000075, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00461 {"cabs.un.d",  "M,S,T",     0x46200071, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00462 {"cabs.un.ps", "M,S,T",     0x46c00071, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_D,       0,            M3D    },
00463 {"cabs.un.s",  "M,S,T",     0x46000071, 0xffe000ff,     RD_S|RD_T|WR_CC|FP_S,       0,            M3D    },
00464 /* CW4010 instructions which are aliases for the cache instruction.  */
00465 {"flushi",  "",             0xbc010000, 0xffffffff, 0,                0,            L1     },
00466 {"flushd",  "",             0xbc020000, 0xffffffff, 0,                0,            L1     },
00467 {"flushid", "",             0xbc030000, 0xffffffff, 0,                0,            L1     },
00468 {"wb",            "o(b)",   0xbc040000, 0xfc1f0000, SM|RD_b,          0,            L1     },
00469 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                 0,            I3|I32|T3},
00470 {"cache",   "k,A(b)",       0,    (int) M_CACHE_AB, INSN_MACRO,              0,            I3|I32|T3},
00471 {"ceil.l.d", "D,S",  0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,          0,            I3|I33 },
00472 {"ceil.l.s", "D,S",  0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I3|I33 },
00473 {"ceil.w.d", "D,S",  0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I2     },
00474 {"ceil.w.s", "D,S",  0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,          0,            I2     },
00475 {"cfc0",    "t,G",   0x40400000, 0xffe007ff,     LCD|WR_t|RD_C0,             0,            I1     },
00476 {"cfc1",    "t,G",   0x44400000, 0xffe007ff,     LCD|WR_t|RD_C1|FP_S, 0,            I1     },
00477 {"cfc1",    "t,S",   0x44400000, 0xffe007ff,     LCD|WR_t|RD_C1|FP_S, 0,            I1     },
00478 /* cfc2 is at the bottom of the table.  */
00479 /* cfc3 is at the bottom of the table.  */
00480 {"cftc1",   "d,E",   0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,           MT32   },
00481 {"cftc1",   "d,T",   0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,           MT32   },
00482 {"cftc2",   "d,E",   0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,     0,            MT32   },
00483 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,       0,            I32|N55 },
00484 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,       0,            I32|N55 },
00485 {"ctc0",    "t,G",   0x40c00000, 0xffe007ff,     COD|RD_t|WR_CC,             0,            I1     },
00486 {"ctc1",    "t,G",   0x44c00000, 0xffe007ff,     COD|RD_t|WR_CC|FP_S, 0,            I1     },
00487 {"ctc1",    "t,S",   0x44c00000, 0xffe007ff,     COD|RD_t|WR_CC|FP_S, 0,            I1     },
00488 /* ctc2 is at the bottom of the table.  */
00489 /* ctc3 is at the bottom of the table.  */
00490 {"cttc1",   "t,g",   0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,           MT32   },
00491 {"cttc1",   "t,S",   0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,           MT32   },
00492 {"cttc2",   "t,g",   0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,     0,            MT32   },
00493 {"cvt.d.l", "D,S",   0x46a00021, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I3|I33 },
00494 {"cvt.d.s", "D,S",   0x46000021, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I1     },
00495 {"cvt.d.w", "D,S",   0x46800021, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I1     },
00496 {"cvt.l.d", "D,S",   0x46200025, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I3|I33 },
00497 {"cvt.l.s", "D,S",   0x46000025, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I3|I33 },
00498 {"cvt.s.l", "D,S",   0x46a00020, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I3|I33 },
00499 {"cvt.s.d", "D,S",   0x46200020, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I1     },
00500 {"cvt.s.w", "D,S",   0x46800020, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I1     },
00501 {"cvt.s.pl","D,S",   0x46c00028, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I5|I33 },
00502 {"cvt.s.pu","D,S",   0x46c00020, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I5|I33 },
00503 {"cvt.w.d", "D,S",   0x46200024, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I1     },
00504 {"cvt.w.s", "D,S",   0x46000024, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I1     },
00505 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            M3D    },
00506 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S|FP_D, 0,              I5|I33 },
00507 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            M3D    },
00508 {"dabs",    "d,v",   0,    (int) M_DABS,  INSN_MACRO,          0,            I3     },
00509 {"dadd",    "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            I3     },
00510 {"dadd",    "t,r,I", 0,    (int) M_DADD_I,       INSN_MACRO,          0,            I3     },
00511 {"daddi",   "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s,        0,            I3     },
00512 {"daddiu",  "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s,        0,            I3     },
00513 {"daddu",   "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            I3     },
00514 {"daddu",   "t,r,I", 0,    (int) M_DADDU_I,      INSN_MACRO,          0,            I3     },
00515 {"dbreak",  "",             0x7000003f, 0xffffffff,     0,                   0,            N5     },
00516 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,       0,            I64|N55 },
00517 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,       0,            I64|N55 },
00518 /* dctr and dctw are used on the r5000.  */
00519 {"dctr",    "o(b)",  0xbc050000, 0xfc1f0000, RD_b,                    0,            I3     },
00520 {"dctw",    "o(b)",  0xbc090000, 0xfc1f0000, RD_b,                    0,            I3     },
00521 {"deret",   "",         0x4200001f, 0xffffffff, 0,                    0,            I32|G2 },
00522 {"dext",    "t,r,I,+I",     0,    (int) M_DEXT,  INSN_MACRO,          0,            I65    },
00523 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,                  0,            I65    },
00524 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,                  0,            I65    },
00525 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,                  0,            I65    },
00526 /* For ddiv, see the comments about div.  */
00527 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I3      },
00528 {"ddiv",    "d,v,t", 0,    (int) M_DDIV_3,       INSN_MACRO,          0,            I3     },
00529 {"ddiv",    "d,v,I", 0,    (int) M_DDIV_3I,      INSN_MACRO,          0,            I3     },
00530 /* For ddivu, see the comments about div.  */
00531 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I3      },
00532 {"ddivu",   "d,v,t", 0,    (int) M_DDIVU_3,      INSN_MACRO,          0,            I3     },
00533 {"ddivu",   "d,v,I", 0,    (int) M_DDIVU_3I,     INSN_MACRO,          0,            I3     },
00534 {"di",      "",             0x41606000, 0xffffffff,     WR_t|WR_C0,          0,            I33    },
00535 {"di",      "t",     0x41606000, 0xffe0ffff,     WR_t|WR_C0,          0,            I33    },
00536 {"dins",    "t,r,I,+I",     0,    (int) M_DINS,  INSN_MACRO,          0,            I65    },
00537 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                  0,            I65    },
00538 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                  0,            I65    },
00539 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,                  0,            I65    },
00540 /* The MIPS assembler treats the div opcode with two operands as
00541    though the first operand appeared twice (the first operand is both
00542    a source and a destination).  To get the div machine instruction,
00543    you must use an explicit destination of $0.  */
00544 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I1      },
00545 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,          I1      },
00546 {"div",     "d,v,t", 0,    (int) M_DIV_3, INSN_MACRO,          0,            I1     },
00547 {"div",     "d,v,I", 0,    (int) M_DIV_3I,       INSN_MACRO,          0,            I1     },
00548 {"div.d",   "D,V,T", 0x46200003, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I1     },
00549 {"div.s",   "D,V,T", 0x46000003, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            I1     },
00550 {"div.ps",  "D,V,T", 0x46c00003, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            SB1    },
00551 /* For divu, see the comments about div.  */
00552 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I1      },
00553 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,          I1      },
00554 {"divu",    "d,v,t", 0,    (int) M_DIVU_3,       INSN_MACRO,          0,            I1     },
00555 {"divu",    "d,v,I", 0,    (int) M_DIVU_3I,      INSN_MACRO,          0,            I1     },
00556 {"dla",     "t,A(b)",       0,    (int) M_DLA_AB,       INSN_MACRO,          0,            I3     },
00557 {"dlca",    "t,A(b)",       0,    (int) M_DLCA_AB,      INSN_MACRO,          0,            I3     },
00558 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                 0,            I3     }, /* addiu */
00559 {"dli",           "t,i",    0x34000000, 0xffe00000, WR_t,                    0,            I3     }, /* ori */
00560 {"dli",     "t,I",   0,    (int) M_DLI,   INSN_MACRO,          0,            I3     },
00561 {"dmacc",   "d,s,t", 0x00000029, 0xfc0007ff,     RD_s|RD_t|WR_LO|WR_d,       0,            N412   },
00562 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,    0,            N412   },
00563 {"dmacchis", "d,s,t",       0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,    0,            N412   },
00564 {"dmacchiu", "d,s,t",       0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,    0,            N412   },
00565 {"dmacchius", "d,s,t",      0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,    0,            N412   },
00566 {"dmaccs",  "d,s,t", 0x00000429, 0xfc0007ff,     RD_s|RD_t|WR_LO|WR_d,       0,            N412   },
00567 {"dmaccu",  "d,s,t", 0x00000069, 0xfc0007ff,     RD_s|RD_t|WR_LO|WR_d,       0,            N412   },
00568 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff,     RD_s|RD_t|WR_LO|WR_d,       0,            N412   },
00569 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,          N411    },
00570 {"dmfc0",   "t,G",   0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,          0,            I3     },
00571 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,       0,            I64     },
00572 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,       0,            I64     },
00573 {"dmt",     "",             0x41600bc1, 0xffffffff, TRAP,                    0,            MT32   },
00574 {"dmt",     "t",     0x41600bc1, 0xffe0ffff, TRAP|WR_t,        0,            MT32   },
00575 {"dmtc0",   "t,G",   0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,    0,            I3     },
00576 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,          I64     },
00577 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,          I64     },
00578 {"dmfc1",   "t,S",   0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,      0,            I3     },
00579 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,          I3      },
00580 {"dmtc1",   "t,S",   0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,      0,            I3     },
00581 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,          I3      },
00582 /* dmfc2 is at the bottom of the table.  */
00583 /* dmtc2 is at the bottom of the table.  */
00584 /* dmfc3 is at the bottom of the table.  */
00585 /* dmtc3 is at the bottom of the table.  */
00586 {"dmul",    "d,v,t", 0,    (int) M_DMUL,  INSN_MACRO,          0,            I3     },
00587 {"dmul",    "d,v,I", 0,    (int) M_DMUL_I,       INSN_MACRO,          0,            I3     },
00588 {"dmulo",   "d,v,t", 0,    (int) M_DMULO, INSN_MACRO,          0,            I3     },
00589 {"dmulo",   "d,v,I", 0,    (int) M_DMULO_I,      INSN_MACRO,          0,            I3     },
00590 {"dmulou",  "d,v,t", 0,    (int) M_DMULOU,       INSN_MACRO,          0,            I3     },
00591 {"dmulou",  "d,v,I", 0,    (int) M_DMULOU_I,     INSN_MACRO,          0,            I3     },
00592 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I3     },
00593 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I3     },
00594 {"dneg",    "d,w",   0x0000002e, 0xffe007ff,     WR_d|RD_t,           0,            I3     }, /* dsub 0 */
00595 {"dnegu",   "d,w",   0x0000002f, 0xffe007ff,     WR_d|RD_t,           0,            I3     }, /* dsubu 0*/
00596 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I3      },
00597 {"drem",    "d,v,t", 3,    (int) M_DREM_3,       INSN_MACRO,          0,            I3     },
00598 {"drem",    "d,v,I", 3,    (int) M_DREM_3I,      INSN_MACRO,          0,            I3     },
00599 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I3      },
00600 {"dremu",   "d,v,t", 3,    (int) M_DREMU_3,      INSN_MACRO,          0,            I3     },
00601 {"dremu",   "d,v,I", 3,    (int) M_DREMU_3I,     INSN_MACRO,          0,            I3     },
00602 {"dret",    "",             0x7000003e, 0xffffffff,     0,                   0,            N5     },
00603 {"drol",    "d,v,t", 0,    (int) M_DROL,  INSN_MACRO,          0,            I3     },
00604 {"drol",    "d,v,I", 0,    (int) M_DROL_I,       INSN_MACRO,          0,            I3     },
00605 {"dror",    "d,v,t", 0,    (int) M_DROR,  INSN_MACRO,          0,            I3     },
00606 {"dror",    "d,v,I", 0,    (int) M_DROR_I,       INSN_MACRO,          0,            I3     },
00607 {"dror",    "d,w,<", 0x0020003a, 0xffe0003f,     WR_d|RD_t,           0,            N5|I65 },
00608 {"drorv",   "d,t,s", 0x00000056, 0xfc0007ff,     RD_t|RD_s|WR_d,             0,            N5|I65 },
00609 {"dror32",  "d,w,<", 0x0020003e, 0xffe0003f,     WR_d|RD_t,           0,            N5|I65 },
00610 {"drotl",   "d,v,t", 0,    (int) M_DROL,  INSN_MACRO,          0,            I65    },
00611 {"drotl",   "d,v,I", 0,    (int) M_DROL_I,       INSN_MACRO,          0,            I65    },
00612 {"drotr",   "d,v,t", 0,    (int) M_DROR,  INSN_MACRO,          0,            I65    },
00613 {"drotr",   "d,v,I", 0,    (int) M_DROR_I,       INSN_MACRO,          0,            I65    },
00614 {"drotrv",  "d,t,s", 0x00000056, 0xfc0007ff,     RD_t|RD_s|WR_d,             0,            I65    },
00615 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f,     WR_d|RD_t,           0,            I65    },
00616 {"dsbh",    "d,w",   0x7c0000a4, 0xffe007ff,     WR_d|RD_t,           0,            I65    },
00617 {"dshd",    "d,w",   0x7c000164, 0xffe007ff,     WR_d|RD_t,           0,            I65    },
00618 {"dsllv",   "d,t,s", 0x00000014, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I3     },
00619 {"dsll32",  "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t,        0,            I3     },
00620 {"dsll",    "d,w,s", 0x00000014, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I3     }, /* dsllv */
00621 {"dsll",    "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t,        0,            I3     }, /* dsll32 */
00622 {"dsll",    "d,w,<", 0x00000038, 0xffe0003f,     WR_d|RD_t,           0,            I3     },
00623 {"dsrav",   "d,t,s", 0x00000017, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I3     },
00624 {"dsra32",  "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t,        0,            I3     },
00625 {"dsra",    "d,w,s", 0x00000017, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I3     }, /* dsrav */
00626 {"dsra",    "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t,        0,            I3     }, /* dsra32 */
00627 {"dsra",    "d,w,<", 0x0000003b, 0xffe0003f,     WR_d|RD_t,           0,            I3     },
00628 {"dsrlv",   "d,t,s", 0x00000016, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I3     },
00629 {"dsrl32",  "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t,        0,            I3     },
00630 {"dsrl",    "d,w,s", 0x00000016, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I3     }, /* dsrlv */
00631 {"dsrl",    "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t,        0,            I3     }, /* dsrl32 */
00632 {"dsrl",    "d,w,<", 0x0000003a, 0xffe0003f,     WR_d|RD_t,           0,            I3     },
00633 {"dsub",    "d,v,t", 0x0000002e, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I3     },
00634 {"dsub",    "d,v,I", 0,    (int) M_DSUB_I,       INSN_MACRO,          0,            I3     },
00635 {"dsubu",   "d,v,t", 0x0000002f, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I3     },
00636 {"dsubu",   "d,v,I", 0,    (int) M_DSUBU_I,      INSN_MACRO,          0,            I3     },
00637 {"dvpe",    "",             0x41600001, 0xffffffff, TRAP,                    0,            MT32   },
00638 {"dvpe",    "t",     0x41600001, 0xffe0ffff, TRAP|WR_t,        0,            MT32   },
00639 {"ei",      "",             0x41606020, 0xffffffff,     WR_t|WR_C0,          0,            I33    },
00640 {"ei",      "t",     0x41606020, 0xffe0ffff,     WR_t|WR_C0,          0,            I33    },
00641 {"emt",     "",             0x41600be1, 0xffffffff, TRAP,                    0,            MT32   },
00642 {"emt",     "t",     0x41600be1, 0xffe0ffff, TRAP|WR_t,        0,            MT32   },
00643 {"eret",    "",         0x42000018, 0xffffffff, 0,                    0,            I3|I32 },
00644 {"evpe",    "",             0x41600021, 0xffffffff, TRAP,                    0,            MT32   },
00645 {"evpe",    "t",     0x41600021, 0xffe0ffff, TRAP|WR_t,        0,            MT32   },
00646 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,                  0,            I33    },
00647 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,          0,            I3|I33 },
00648 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I3|I33 },
00649 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I2     },
00650 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,          0,            I2     },
00651 {"hibernate","",        0x42000023, 0xffffffff,  0,                   0,            V1     },
00652 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,                  0,            I33    },
00653 {"jr",      "s",     0x00000008, 0xfc1fffff,     UBD|RD_s,            0,            I1     },
00654 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
00655    the same hazard barrier effect.  */
00656 {"jr.hb",   "s",     0x00000408, 0xfc1fffff,     UBD|RD_s,            0,            I32    },
00657 {"j",       "s",     0x00000008, 0xfc1fffff,     UBD|RD_s,            0,            I1     }, /* jr */
00658 /* SVR4 PIC code requires special handling for j, so it must be a
00659    macro.  */
00660 {"j",      "a",      0,     (int) M_J_A,  INSN_MACRO,          0,            I1     },
00661 /* This form of j is used by the disassembler and internally by the
00662    assembler, but will never match user input (because the line above
00663    will match first).  */
00664 {"j",       "a",     0x08000000, 0xfc000000,     UBD,                 0,            I1     },
00665 {"jalr",    "s",     0x0000f809, 0xfc1fffff,     UBD|RD_s|WR_d,              0,            I1     },
00666 {"jalr",    "d,s",   0x00000009, 0xfc1f07ff,     UBD|RD_s|WR_d,              0,            I1     },
00667 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
00668    with the same hazard barrier effect.  */
00669 {"jalr.hb", "s",     0x0000fc09, 0xfc1fffff,     UBD|RD_s|WR_d,              0,            I32    },
00670 {"jalr.hb", "d,s",   0x00000409, 0xfc1f07ff,     UBD|RD_s|WR_d,              0,            I32    },
00671 /* SVR4 PIC code requires special handling for jal, so it must be a
00672    macro.  */
00673 {"jal",     "d,s",   0,     (int) M_JAL_2,       INSN_MACRO,          0,            I1     },
00674 {"jal",     "s",     0,     (int) M_JAL_1,       INSN_MACRO,          0,            I1     },
00675 {"jal",     "a",     0,     (int) M_JAL_A,       INSN_MACRO,          0,            I1     },
00676 /* This form of jal is used by the disassembler and internally by the
00677    assembler, but will never match user input (because the line above
00678    will match first).  */
00679 {"jal",     "a",     0x0c000000, 0xfc000000,     UBD|WR_31,           0,            I1     },
00680 {"jalx",    "a",     0x74000000, 0xfc000000, UBD|WR_31,        0,            I16     },
00681 {"la",      "t,A(b)",       0,    (int) M_LA_AB, INSN_MACRO,          0,            I1     },
00682 {"lb",      "t,o(b)",       0x80000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00683 {"lb",      "t,A(b)",       0,    (int) M_LB_AB, INSN_MACRO,          0,            I1     },
00684 {"lbu",     "t,o(b)",       0x90000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00685 {"lbu",     "t,A(b)",       0,    (int) M_LBU_AB,       INSN_MACRO,          0,            I1     },
00686 {"lca",     "t,A(b)",       0,    (int) M_LCA_AB,       INSN_MACRO,          0,            I1     },
00687 {"ld",     "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,             0,            I3     },
00688 {"ld",      "t,o(b)",       0,    (int) M_LD_OB, INSN_MACRO,          0,            I1     },
00689 {"ld",      "t,A(b)",       0,    (int) M_LD_AB, INSN_MACRO,          0,            I1     },
00690 {"ldc1",    "T,o(b)",       0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,      0,            I2     },
00691 {"ldc1",    "E,o(b)",       0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,      0,            I2     },
00692 {"ldc1",    "T,A(b)",       0,    (int) M_LDC1_AB,      INSN_MACRO,          0,            I2     },
00693 {"ldc1",    "E,A(b)",       0,    (int) M_LDC1_AB,      INSN_MACRO,          0,            I2     },
00694 {"l.d",     "T,o(b)",       0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,      0,            I2     }, /* ldc1 */
00695 {"l.d",     "T,o(b)",       0,    (int) M_L_DOB, INSN_MACRO,          0,            I1     },
00696 {"l.d",     "T,A(b)",       0,    (int) M_L_DAB, INSN_MACRO,          0,            I1     },
00697 {"ldc2",    "E,o(b)",       0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,          0,            I2     },
00698 {"ldc2",    "E,A(b)",       0,    (int) M_LDC2_AB,      INSN_MACRO,          0,            I2     },
00699 {"ldc3",    "E,o(b)",       0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,          0,            I2     },
00700 {"ldc3",    "E,A(b)",       0,    (int) M_LDC3_AB,      INSN_MACRO,          0,            I2     },
00701 {"ldl",           "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b,           0,            I3     },
00702 {"ldl",           "t,A(b)", 0,    (int) M_LDL_AB,       INSN_MACRO,          0,            I3     },
00703 {"ldr",           "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b,           0,            I3     },
00704 {"ldr",     "t,A(b)",       0,    (int) M_LDR_AB,       INSN_MACRO,          0,            I3     },
00705 {"ldxc1",   "D,t(b)",       0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,            I4|I33 },
00706 {"lh",      "t,o(b)",       0x84000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00707 {"lh",      "t,A(b)",       0,    (int) M_LH_AB, INSN_MACRO,          0,            I1     },
00708 {"lhu",     "t,o(b)",       0x94000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00709 {"lhu",     "t,A(b)",       0,    (int) M_LHU_AB,       INSN_MACRO,          0,            I1     },
00710 /* li is at the start of the table.  */
00711 {"li.d",    "t,F",   0,    (int) M_LI_D,  INSN_MACRO,          0,            I1     },
00712 {"li.d",    "T,L",   0,    (int) M_LI_DD, INSN_MACRO,          0,            I1     },
00713 {"li.s",    "t,f",   0,    (int) M_LI_S,  INSN_MACRO,          0,            I1     },
00714 {"li.s",    "T,l",   0,    (int) M_LI_SS, INSN_MACRO,          0,            I1     },
00715 {"ll",     "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t,           0,            I2     },
00716 {"ll",     "t,A(b)", 0,    (int) M_LL_AB, INSN_MACRO,          0,            I2     },
00717 {"lld",           "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t,           0,            I3     },
00718 {"lld",     "t,A(b)",       0,    (int) M_LLD_AB,       INSN_MACRO,          0,            I3     },
00719 {"lui",     "t,u",   0x3c000000, 0xffe00000,     WR_t,                0,            I1     },
00720 {"luxc1",   "D,t(b)",       0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,            I5|I33|N55},
00721 {"lw",      "t,o(b)",       0x8c000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00722 {"lw",      "t,A(b)",       0,    (int) M_LW_AB, INSN_MACRO,          0,            I1     },
00723 {"lwc0",    "E,o(b)",       0xc0000000, 0xfc000000,     CLD|RD_b|WR_CC,             0,            I1     },
00724 {"lwc0",    "E,A(b)",       0,    (int) M_LWC0_AB,      INSN_MACRO,          0,            I1     },
00725 {"lwc1",    "T,o(b)",       0xc4000000, 0xfc000000,     CLD|RD_b|WR_T|FP_S,  0,            I1     },
00726 {"lwc1",    "E,o(b)",       0xc4000000, 0xfc000000,     CLD|RD_b|WR_T|FP_S,  0,            I1     },
00727 {"lwc1",    "T,A(b)",       0,    (int) M_LWC1_AB,      INSN_MACRO,          0,            I1     },
00728 {"lwc1",    "E,A(b)",       0,    (int) M_LWC1_AB,      INSN_MACRO,          0,            I1     },
00729 {"l.s",     "T,o(b)",       0xc4000000, 0xfc000000,     CLD|RD_b|WR_T|FP_S,  0,            I1     }, /* lwc1 */
00730 {"l.s",     "T,A(b)",       0,    (int) M_LWC1_AB,      INSN_MACRO,          0,            I1     },
00731 {"lwc2",    "E,o(b)",       0xc8000000, 0xfc000000,     CLD|RD_b|WR_CC,             0,            I1     },
00732 {"lwc2",    "E,A(b)",       0,    (int) M_LWC2_AB,      INSN_MACRO,          0,            I1     },
00733 {"lwc3",    "E,o(b)",       0xcc000000, 0xfc000000,     CLD|RD_b|WR_CC,             0,            I1     },
00734 {"lwc3",    "E,A(b)",       0,    (int) M_LWC3_AB,      INSN_MACRO,          0,            I1     },
00735 {"lwl",     "t,o(b)",       0x88000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00736 {"lwl",     "t,A(b)",       0,    (int) M_LWL_AB,       INSN_MACRO,          0,            I1     },
00737 {"lcache",  "t,o(b)",       0x88000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I2     }, /* same */
00738 {"lcache",  "t,A(b)",       0,    (int) M_LWL_AB,       INSN_MACRO,          0,            I2     }, /* as lwl */
00739 {"lwr",     "t,o(b)",       0x98000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I1     },
00740 {"lwr",     "t,A(b)",       0,    (int) M_LWR_AB,       INSN_MACRO,          0,            I1     },
00741 {"flush",   "t,o(b)",       0x98000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I2     }, /* same */
00742 {"flush",   "t,A(b)",       0,    (int) M_LWR_AB,       INSN_MACRO,          0,            I2     }, /* as lwr */
00743 {"fork",    "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,     0,            MT32   },
00744 {"lwu",     "t,o(b)",       0x9c000000, 0xfc000000,     LDD|RD_b|WR_t,              0,            I3     },
00745 {"lwu",     "t,A(b)",       0,    (int) M_LWU_AB,       INSN_MACRO,          0,            I3     },
00746 {"lwxc1",   "D,t(b)",       0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,            I4|I33 },
00747 {"lwxs",    "d,t(b)",       0x70000088, 0xfc0007ff,     LDD|RD_b|RD_t|WR_d,  0,            SMT    },
00748 {"macc",    "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,             N412    },
00749 {"macc",    "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,  0,            N5      },
00750 {"maccs",   "d,s,t", 0x00000428, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d, 0,         N412    },
00751 {"macchi",  "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,             N412    },
00752 {"macchi",  "d,s,t", 0x00000358, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5      },
00753 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d, 0,         N412    },
00754 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d, 0,         N412    },
00755 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,  0,            N5      },
00756 {"macchius","d,s,t", 0x00000668, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d, 0,         N412    },
00757 {"maccu",   "d,s,t", 0x00000068, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d, 0,         N412    },
00758 {"maccu",   "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,  0,            N5      },
00759 {"maccus",  "d,s,t", 0x00000468, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d, 0,         N412    },
00760 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,          P3      },
00761 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,          P3      },
00762 {"madd.d",  "D,R,S,T",      0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,        I4|I33 },
00763 {"madd.s",  "D,R,S,T",      0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,        I4|I33 },
00764 {"madd.ps", "D,R,S,T",      0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,        I5|I33 },
00765 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,            L1     },
00766 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,            I32|N55       },
00767 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,            G1     },
00768 {"madd",    "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33   },
00769 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,            G1     },
00770 {"maddp",   "s,t",      0x70000441, 0xfc00ffff,  RD_s|RD_t|MOD_HILO,       0,              SMT    },
00771 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,            L1     },
00772 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,            I32|N55       },
00773 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,            G1     },
00774 {"maddu",   "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33   },
00775 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,            G1     },
00776 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,   0,            N411    },
00777 {"max.ob",  "X,Y,Q", 0x78000007, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00778 {"max.ob",  "D,S,T", 0x4ac00007, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00779 {"max.ob",  "D,S,T[e]",     0x48000007, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00780 {"max.ob",  "D,S,k", 0x4bc00007, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00781 {"max.qh",  "X,Y,Q", 0x78200007, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00782 {"mfpc",    "t,P",   0x4000c801, 0xffe0ffc1,     LCD|WR_t|RD_C0,             0,            M1|N5  },
00783 {"mfps",    "t,P",   0x4000c800, 0xffe0ffc1,     LCD|WR_t|RD_C0,             0,            M1|N5  },
00784 {"mftacx",  "d",     0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,          0,            MT32   },
00785 {"mftacx",  "d,*",   0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,          0,            MT32   },
00786 {"mftc0",   "d,+t",  0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,     0,            MT32   },
00787 {"mftc0",   "d,+T",  0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,     0,            MT32   },
00788 {"mftc0",   "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,     0,            MT32   },
00789 {"mftc1",   "d,T",   0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,            MT32   },
00790 {"mftc1",   "d,E",   0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,            MT32   },
00791 {"mftc2",   "d,E",   0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,     0,            MT32   },
00792 {"mftdsp",  "d",     0x41100021, 0xffff07ff, TRAP|WR_d,        0,            MT32   },
00793 {"mftgpr",  "d,t",   0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,          0,            MT32   },
00794 {"mfthc1",  "d,T",   0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,            MT32   },
00795 {"mfthc1",  "d,E",   0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,            MT32   },
00796 {"mfthc2",  "d,E",   0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,     0,            MT32   },
00797 {"mfthi",   "d",     0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,          0,            MT32   },
00798 {"mfthi",   "d,*",   0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,          0,            MT32   },
00799 {"mftlo",   "d",     0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,          0,            MT32   },
00800 {"mftlo",   "d,*",   0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,          0,            MT32   },
00801 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,           0,            MT32   },
00802 {"mfc0",    "t,G",   0x40000000, 0xffe007ff,     LCD|WR_t|RD_C0,             0,            I1     },
00803 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,       0,            I32     },
00804 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,       0,            I32     },
00805 {"mfc1",    "t,S",   0x44000000, 0xffe007ff,     LCD|WR_t|RD_S|FP_S,  0,            I1     },
00806 {"mfc1",    "t,G",   0x44000000, 0xffe007ff,     LCD|WR_t|RD_S|FP_S,  0,            I1     },
00807 {"mfhc1",   "t,S",   0x44600000, 0xffe007ff,     LCD|WR_t|RD_S|FP_D,  0,            I33    },
00808 {"mfhc1",   "t,G",   0x44600000, 0xffe007ff,     LCD|WR_t|RD_S|FP_D,  0,            I33    },
00809 /* mfc2 is at the bottom of the table.  */
00810 /* mfhc2 is at the bottom of the table.  */
00811 /* mfc3 is at the bottom of the table.  */
00812 {"mfdr",    "t,G",   0x7000003d, 0xffe007ff,     LCD|WR_t|RD_C0,             0,            N5      },
00813 {"mfhi",    "d",     0x00000010, 0xffff07ff,     WR_d|RD_HI,          0,            I1     },
00814 {"mfhi",    "d,9",   0x00000010, 0xff9f07ff, WR_d|RD_HI,              0,            D32    },
00815 {"mflo",    "d",     0x00000012, 0xffff07ff,     WR_d|RD_LO,          0,            I1     },
00816 {"mflo",    "d,9",   0x00000012, 0xff9f07ff, WR_d|RD_LO,              0,            D32    },
00817 {"mflhxu",  "d",     0x00000052, 0xffff07ff,     WR_d|MOD_HILO,              0,            SMT    },
00818 {"min.ob",  "X,Y,Q", 0x78000006, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00819 {"min.ob",  "D,S,T", 0x4ac00006, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00820 {"min.ob",  "D,S,T[e]",     0x48000006, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00821 {"min.ob",  "D,S,k", 0x4bc00006, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00822 {"min.qh",  "X,Y,Q", 0x78200006, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00823 {"mov.d",   "D,S",   0x46200006, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I1     },
00824 {"mov.s",   "D,S",   0x46000006, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I1     },
00825 {"mov.ps",  "D,S",   0x46c00006, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I5|I33 },
00826 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,              I4|I32  },
00827 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,          I4|I32 },
00828 {"movf.l",  "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,    0,            MX|SB1 },
00829 {"movf.l",  "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,    0,            MX|SB1 },
00830 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,          I4|I32 },
00831 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,    0,            I5|I33 },
00832 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,       0,            I4|I32 },
00833 {"ffc",     "d,v",   0x0000000b, 0xfc1f07ff,     WR_d|RD_s,           0,            L1     },
00834 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          I4|I32 },
00835 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          MX|SB1 },
00836 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          MX|SB1 },
00837 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,          I4|I32 },
00838 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          I5|I33 },
00839 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,              I4|I32 },
00840 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,          I4|I32 },
00841 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,          MX|SB1 },
00842 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,          MX|SB1 },
00843 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,          I4|I32 },
00844 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,    0,            I5|I33 },
00845 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,       0,            I4|I32 },
00846 {"ffs",     "d,v",   0x0000000a, 0xfc1f07ff,     WR_d|RD_s,           0,            L1     },
00847 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          I4|I32 },
00848 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          MX|SB1 },
00849 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          MX|SB1 },
00850 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,          I4|I32 },
00851 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,          I5|I33 },
00852 {"msac",    "d,s,t", 0x000001d8, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00853 {"msacu",   "d,s,t", 0x000001d9, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00854 {"msachi",  "d,s,t", 0x000003d8, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00855 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00856 /* move is at the top of the table.  */
00857 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00858 {"msub.d",  "D,R,S,T",      0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,           I4|I33 },
00859 {"msub.s",  "D,R,S,T",      0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,           I4|I33 },
00860 {"msub.ps", "D,R,S,T",      0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,           I5|I33 },
00861 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,    0,            L1     },
00862 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,          I32|N55 },
00863 {"msub",    "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33   },
00864 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,    0,            L1     },
00865 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,          I32|N55       },
00866 {"msubu",   "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33   },
00867 {"mtpc",    "t,P",   0x4080c801, 0xffe0ffc1,     COD|RD_t|WR_C0,             0,            M1|N5  },
00868 {"mtps",    "t,P",   0x4080c800, 0xffe0ffc1,     COD|RD_t|WR_C0,             0,            M1|N5  },
00869 {"mtc0",    "t,G",   0x40800000, 0xffe007ff,     COD|RD_t|WR_C0|WR_CC,       0,            I1     },
00870 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,          I32     },
00871 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,          I32     },
00872 {"mtc1",    "t,S",   0x44800000, 0xffe007ff,     COD|RD_t|WR_S|FP_S,  0,            I1     },
00873 {"mtc1",    "t,G",   0x44800000, 0xffe007ff,     COD|RD_t|WR_S|FP_S,  0,            I1     },
00874 {"mthc1",   "t,S",   0x44e00000, 0xffe007ff,     COD|RD_t|WR_S|FP_D,  0,            I33    },
00875 {"mthc1",   "t,G",   0x44e00000, 0xffe007ff,     COD|RD_t|WR_S|FP_D,  0,            I33    },
00876 /* mtc2 is at the bottom of the table.  */
00877 /* mthc2 is at the bottom of the table.  */
00878 /* mtc3 is at the bottom of the table.  */
00879 {"mtdr",    "t,G",   0x7080003d, 0xffe007ff,     COD|RD_t|WR_C0,             0,            N5     },
00880 {"mthi",    "s",     0x00000011, 0xfc1fffff,     RD_s|WR_HI,          0,            I1     },
00881 {"mthi",    "s,7",   0x00000011, 0xfc1fe7ff, RD_s|WR_HI,              0,            D32    },
00882 {"mtlo",    "s",     0x00000013, 0xfc1fffff,     RD_s|WR_LO,          0,            I1     },
00883 {"mtlo",    "s,7",   0x00000013, 0xfc1fe7ff, RD_s|WR_LO,              0,            D32    },
00884 {"mtlhx",   "s",     0x00000053, 0xfc1fffff,     RD_s|MOD_HILO,              0,            SMT    },
00885 {"mttc0",   "t,G",   0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,          MT32   },
00886 {"mttc0",   "t,+D",  0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,          MT32   },
00887 {"mttc0",   "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,          MT32   },
00888 {"mttc1",   "t,S",   0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,            MT32   },
00889 {"mttc1",   "t,G",   0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,            MT32   },
00890 {"mttc2",   "t,g",   0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,          MT32   },
00891 {"mttacx",  "t",     0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,          0,            MT32   },
00892 {"mttacx",  "t,&",   0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,          0,            MT32   },
00893 {"mttdsp",  "t",     0x41808021, 0xffe0ffff, TRAP|RD_t,        0,            MT32   },
00894 {"mttgpr",  "t,d",   0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,          0,            MT32   },
00895 {"mtthc1",  "t,S",   0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,            MT32   },
00896 {"mtthc1",  "t,G",   0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,            MT32   },
00897 {"mtthc2",  "t,g",   0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,          MT32   },
00898 {"mtthi",   "t",     0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,          0,            MT32   },
00899 {"mtthi",   "t,&",   0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,          0,            MT32   },
00900 {"mttlo",   "t",     0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,          0,            MT32   },
00901 {"mttlo",   "t,&",   0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,          0,            MT32   },
00902 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,           0,            MT32   },
00903 {"mul.d",   "D,V,T", 0x46200002, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I1     },
00904 {"mul.s",   "D,V,T", 0x46000002, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            I1     },
00905 {"mul.ob",  "X,Y,Q", 0x78000030, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00906 {"mul.ob",  "D,S,T", 0x4ac00030, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00907 {"mul.ob",  "D,S,T[e]",     0x48000030, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00908 {"mul.ob",  "D,S,k", 0x4bc00030, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00909 {"mul.ps",  "D,V,T", 0x46c00002, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
00910 {"mul.qh",  "X,Y,Q", 0x78200030, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00911 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          I32|P3|N55},
00912 {"mul",     "d,s,t", 0x00000058, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N54    },
00913 {"mul",     "d,v,t", 0,    (int) M_MUL,   INSN_MACRO,          0,            I1     },
00914 {"mul",     "d,v,I", 0,    (int) M_MUL_I, INSN_MACRO,          0,            I1     },
00915 {"mula.ob", "Y,Q",   0x78000033, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
00916 {"mula.ob", "S,T",   0x4ac00033, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00917 {"mula.ob", "S,T[e]",       0x48000033, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00918 {"mula.ob", "S,k",   0x4bc00033, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00919 {"mula.qh", "Y,Q",   0x78200033, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
00920 {"mulhi",   "d,s,t", 0x00000258, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00921 {"mulhiu",  "d,s,t", 0x00000259, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00922 {"mull.ob", "Y,Q",   0x78000433, 0xfc2007ff,     RD_S|RD_T|FP_D,      WR_MACC,      MX|SB1 },
00923 {"mull.ob", "S,T",   0x4ac00433, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00924 {"mull.ob", "S,T[e]",       0x48000433, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00925 {"mull.ob", "S,k",   0x4bc00433, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00926 {"mull.qh", "Y,Q",   0x78200433, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
00927 {"mulo",    "d,v,t", 0,    (int) M_MULO,  INSN_MACRO,          0,            I1     },
00928 {"mulo",    "d,v,I", 0,    (int) M_MULO_I,       INSN_MACRO,          0,            I1     },
00929 {"mulou",   "d,v,t", 0,    (int) M_MULOU, INSN_MACRO,          0,            I1     },
00930 {"mulou",   "d,v,I", 0,    (int) M_MULOU_I,      INSN_MACRO,          0,            I1     },
00931 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            M3D    },
00932 {"muls",    "d,s,t", 0x000000d8, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00933 {"mulsu",   "d,s,t", 0x000000d9, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00934 {"mulshi",  "d,s,t", 0x000002d8, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00935 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00936 {"muls.ob", "Y,Q",   0x78000032, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
00937 {"muls.ob", "S,T",   0x4ac00032, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00938 {"muls.ob", "S,T[e]",       0x48000032, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00939 {"muls.ob", "S,k",   0x4bc00032, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00940 {"muls.qh", "Y,Q",   0x78200032, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
00941 {"mulsl.ob", "Y,Q",  0x78000432, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
00942 {"mulsl.ob", "S,T",  0x4ac00432, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00943 {"mulsl.ob", "S,T[e]",      0x48000432, 0xfe2007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00944 {"mulsl.ob", "S,k",  0x4bc00432, 0xffe007ff,     WR_CC|RD_S|RD_T,     0,            N54    },
00945 {"mulsl.qh", "Y,Q",  0x78200432, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
00946 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,          I1     },
00947 {"mult",    "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33   },
00948 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,            G1     },
00949 {"multp",   "s,t",   0x00000459, 0xfc00ffff,     RD_s|RD_t|MOD_HILO,  0,            SMT    },
00950 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,          I1     },
00951 {"multu",   "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33   },
00952 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,            G1     },
00953 {"mulu",    "d,s,t", 0x00000059, 0xfc0007ff,     RD_s|RD_t|WR_HILO|WR_d,     0,            N5     },
00954 {"neg",     "d,w",   0x00000022, 0xffe007ff,     WR_d|RD_t,           0,            I1     }, /* sub 0 */
00955 {"negu",    "d,w",   0x00000023, 0xffe007ff,     WR_d|RD_t,           0,            I1     }, /* subu 0 */
00956 {"neg.d",   "D,V",   0x46200007, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I1     },
00957 {"neg.s",   "D,V",   0x46000007, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I1     },
00958 {"neg.ps",  "D,V",   0x46c00007, 0xffff003f,     WR_D|RD_S|FP_D,             0,            I5|I33 },
00959 {"nmadd.d", "D,R,S,T",      0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,           I4|I33 },
00960 {"nmadd.s", "D,R,S,T",      0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,           I4|I33 },
00961 {"nmadd.ps","D,R,S,T",      0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,           I5|I33 },
00962 {"nmsub.d", "D,R,S,T",      0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,           I4|I33 },
00963 {"nmsub.s", "D,R,S,T",      0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,           I4|I33 },
00964 {"nmsub.ps","D,R,S,T",      0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,           I5|I33 },
00965 /* nop is at the start of the table.  */
00966 {"nor",     "d,v,t", 0x00000027, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
00967 {"nor",     "t,r,I", 0,    (int) M_NOR_I, INSN_MACRO,          0,            I1     },
00968 {"nor.ob",  "X,Y,Q", 0x7800000f, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00969 {"nor.ob",  "D,S,T", 0x4ac0000f, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00970 {"nor.ob",  "D,S,T[e]",     0x4800000f, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00971 {"nor.ob",  "D,S,k", 0x4bc0000f, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00972 {"nor.qh",  "X,Y,Q", 0x7820000f, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00973 {"not",     "d,v",   0x00000027, 0xfc1f07ff,     WR_d|RD_s|RD_t,             0,            I1     },/*nor d,s,0*/
00974 {"or",      "d,v,t", 0x00000025, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
00975 {"or",      "t,r,I", 0,    (int) M_OR_I,  INSN_MACRO,          0,            I1     },
00976 {"or.ob",   "X,Y,Q", 0x7800000e, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00977 {"or.ob",   "D,S,T", 0x4ac0000e, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00978 {"or.ob",   "D,S,T[e]",     0x4800000e, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
00979 {"or.ob",   "D,S,k", 0x4bc0000e, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00980 {"or.qh",   "X,Y,Q", 0x7820000e, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00981 {"ori",     "t,r,i", 0x34000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
00982 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f,  WR_D|RD_S|RD_T|FP_D, 0,            SB1    },
00983 {"pabsdiffc.ob", "Y,Q",     0x78000035, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      SB1    },
00984 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            SB1    },
00985 {"pickf.ob", "X,Y,Q",       0x78000002, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00986 {"pickf.ob", "D,S,T",       0x4ac00002, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00987 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,  WR_D|RD_S|RD_T,             0,            N54    },
00988 {"pickf.ob", "D,S,k",       0x4bc00002, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00989 {"pickf.qh", "X,Y,Q",       0x78200002, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00990 {"pickt.ob", "X,Y,Q",       0x78000003, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
00991 {"pickt.ob", "D,S,T",       0x4ac00003, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00992 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,  WR_D|RD_S|RD_T,             0,            N54    },
00993 {"pickt.ob", "D,S,k",       0x4bc00003, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
00994 {"pickt.qh", "X,Y,Q",       0x78200003, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
00995 {"pll.ps",  "D,V,T", 0x46c0002c, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
00996 {"plu.ps",  "D,V,T", 0x46c0002d, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
00997   /* pref and prefx are at the start of the table.  */
00998 {"pul.ps",  "D,V,T", 0x46c0002e, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
00999 {"puu.ps",  "D,V,T", 0x46c0002f, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
01000 {"pperm",   "s,t",   0x70000481, 0xfc00ffff,     MOD_HILO|RD_s|RD_t,  0,            SMT    },
01001 {"rach.ob", "X",     0x7a00003f, 0xfffff83f,     WR_D|FP_D,           RD_MACC,      MX|SB1 },
01002 {"rach.ob", "D",     0x4a00003f, 0xfffff83f,     WR_D,                0,            N54    },
01003 {"rach.qh", "X",     0x7a20003f, 0xfffff83f,     WR_D|FP_D,           RD_MACC,      MX     },
01004 {"racl.ob", "X",     0x7800003f, 0xfffff83f,     WR_D|FP_D,           RD_MACC,      MX|SB1 },
01005 {"racl.ob", "D",     0x4800003f, 0xfffff83f,     WR_D,                0,            N54    },
01006 {"racl.qh", "X",     0x7820003f, 0xfffff83f,     WR_D|FP_D,           RD_MACC,      MX     },
01007 {"racm.ob", "X",     0x7900003f, 0xfffff83f,     WR_D|FP_D,           RD_MACC,      MX|SB1 },
01008 {"racm.ob", "D",     0x4900003f, 0xfffff83f,     WR_D,                0,            N54    },
01009 {"racm.qh", "X",     0x7920003f, 0xfffff83f,     WR_D|FP_D,           RD_MACC,      MX     },
01010 {"recip.d", "D,S",   0x46200015, 0xffff003f, WR_D|RD_S|FP_D,          0,            I4|I33 },
01011 {"recip.ps","D,S",   0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,          0,            SB1    },
01012 {"recip.s", "D,S",   0x46000015, 0xffff003f, WR_D|RD_S|FP_S,          0,            I4|I33 },
01013 {"recip1.d",  "D,S", 0x4620001d, 0xffff003f,     WR_D|RD_S|FP_D,             0,            M3D    },
01014 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f,     WR_D|RD_S|FP_S,             0,            M3D    },
01015 {"recip1.s",  "D,S", 0x4600001d, 0xffff003f,     WR_D|RD_S|FP_S,             0,            M3D    },
01016 {"recip2.d",  "D,S,T",      0x4620001c, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            M3D    },
01017 {"recip2.ps", "D,S,T",      0x46c0001c, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            M3D    },
01018 {"recip2.s",  "D,S,T",      0x4600001c, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            M3D    },
01019 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I1     },
01020 {"rem",     "d,v,t", 0,    (int) M_REM_3, INSN_MACRO,          0,            I1     },
01021 {"rem",     "d,v,I", 0,    (int) M_REM_3I,       INSN_MACRO,          0,            I1     },
01022 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,          I1     },
01023 {"remu",    "d,v,t", 0,    (int) M_REMU_3,       INSN_MACRO,          0,            I1     },
01024 {"remu",    "d,v,I", 0,    (int) M_REMU_3I,      INSN_MACRO,          0,            I1     },
01025 {"rdhwr",   "t,K",   0x7c00003b, 0xffe007ff, WR_t,                    0,            I33    },
01026 {"rdpgpr",  "d,w",   0x41400000, 0xffe007ff, WR_d,                    0,            I33    },
01027 {"rfe",     "",             0x42000010, 0xffffffff,     0,                   0,            I1|T3  },
01028 {"rnas.qh", "X,Q",   0x78200025, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX     },
01029 {"rnau.ob", "X,Q",   0x78000021, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX|SB1 },
01030 {"rnau.qh", "X,Q",   0x78200021, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX     },
01031 {"rnes.qh", "X,Q",   0x78200026, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX     },
01032 {"rneu.ob", "X,Q",   0x78000022, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX|SB1 },
01033 {"rneu.qh", "X,Q",   0x78200022, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX     },
01034 {"rol",     "d,v,t", 0,    (int) M_ROL,   INSN_MACRO,          0,            I1     },
01035 {"rol",     "d,v,I", 0,    (int) M_ROL_I, INSN_MACRO,          0,            I1     },
01036 {"ror",     "d,v,t", 0,    (int) M_ROR,   INSN_MACRO,          0,            I1     },
01037 {"ror",     "d,v,I", 0,    (int) M_ROR_I, INSN_MACRO,          0,            I1     },
01038 {"ror",           "d,w,<",  0x00200002, 0xffe0003f,     WR_d|RD_t,           0,            N5|I33|SMT },
01039 {"rorv",    "d,t,s", 0x00000046, 0xfc0007ff,     RD_t|RD_s|WR_d,             0,            N5|I33|SMT },
01040 {"rotl",    "d,v,t", 0,    (int) M_ROL,   INSN_MACRO,          0,            I33|SMT       },
01041 {"rotl",    "d,v,I", 0,    (int) M_ROL_I, INSN_MACRO,          0,            I33|SMT       },
01042 {"rotr",    "d,v,t", 0,    (int) M_ROR,   INSN_MACRO,          0,            I33|SMT       },
01043 {"rotr",    "d,v,I", 0,    (int) M_ROR_I, INSN_MACRO,          0,            I33|SMT       },
01044 {"rotrv",   "d,t,s", 0x00000046, 0xfc0007ff,     RD_t|RD_s|WR_d,             0,            I33|SMT       },
01045 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D,          0,            I3|I33 },
01046 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I3|I33 },
01047 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I2     },
01048 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,          0,            I2     },
01049 {"rsqrt.d", "D,S",   0x46200016, 0xffff003f, WR_D|RD_S|FP_D,          0,            I4|I33 },
01050 {"rsqrt.ps","D,S",   0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,          0,            SB1    },
01051 {"rsqrt.s", "D,S",   0x46000016, 0xffff003f, WR_D|RD_S|FP_S,          0,            I4|I33 },
01052 {"rsqrt1.d",  "D,S", 0x4620001e, 0xffff003f,     WR_D|RD_S|FP_D,             0,            M3D    },
01053 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f,     WR_D|RD_S|FP_S,             0,            M3D    },
01054 {"rsqrt1.s",  "D,S", 0x4600001e, 0xffff003f,     WR_D|RD_S|FP_S,             0,            M3D    },
01055 {"rsqrt2.d",  "D,S,T",      0x4620001f, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            M3D    },
01056 {"rsqrt2.ps", "D,S,T",      0x46c0001f, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            M3D    },
01057 {"rsqrt2.s",  "D,S,T",      0x4600001f, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            M3D    },
01058 {"rzs.qh",  "X,Q",   0x78200024, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX     },
01059 {"rzu.ob",  "X,Q",   0x78000020, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX|SB1 },
01060 {"rzu.ob",  "D,k",   0x4bc00020, 0xffe0f83f,     WR_D|RD_S|RD_T,             0,            N54    },
01061 {"rzu.qh",  "X,Q",   0x78200020, 0xfc20f83f,     WR_D|RD_T|FP_D,             RD_MACC,      MX     },
01062 {"sb",      "t,o(b)",       0xa0000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I1     },
01063 {"sb",      "t,A(b)",       0,    (int) M_SB_AB, INSN_MACRO,          0,            I1     },
01064 {"sc",     "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,       0,            I2     },
01065 {"sc",     "t,A(b)", 0,    (int) M_SC_AB, INSN_MACRO,          0,            I2     },
01066 {"scd",           "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,       0,            I3     },
01067 {"scd",           "t,A(b)", 0,    (int) M_SCD_AB,       INSN_MACRO,          0,            I3     },
01068 {"sd",     "t,o(b)", 0xfc000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I3     },
01069 {"sd",      "t,o(b)",       0,    (int) M_SD_OB, INSN_MACRO,          0,            I1     },
01070 {"sd",      "t,A(b)",       0,    (int) M_SD_AB, INSN_MACRO,          0,            I1     },
01071 {"sdbbp",   "",             0x0000000e, 0xffffffff,     TRAP,                0,            G2     },
01072 {"sdbbp",   "c",     0x0000000e, 0xfc00ffff,     TRAP,                0,            G2     },
01073 {"sdbbp",   "c,q",   0x0000000e, 0xfc00003f,     TRAP,                0,            G2     },
01074 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                 0,            I32     },
01075 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                 0,            I32     },
01076 {"sdc1",    "T,o(b)",       0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,       0,            I2     },
01077 {"sdc1",    "E,o(b)",       0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,       0,            I2     },
01078 {"sdc1",    "T,A(b)",       0,    (int) M_SDC1_AB,      INSN_MACRO,          0,            I2     },
01079 {"sdc1",    "E,A(b)",       0,    (int) M_SDC1_AB,      INSN_MACRO,          0,            I2     },
01080 {"sdc2",    "E,o(b)",       0xf8000000, 0xfc000000, SM|RD_C2|RD_b,           0,            I2     },
01081 {"sdc2",    "E,A(b)",       0,    (int) M_SDC2_AB,      INSN_MACRO,          0,            I2     },
01082 {"sdc3",    "E,o(b)",       0xfc000000, 0xfc000000, SM|RD_C3|RD_b,           0,            I2     },
01083 {"sdc3",    "E,A(b)",       0,    (int) M_SDC3_AB,      INSN_MACRO,          0,            I2     },
01084 {"s.d",     "T,o(b)",       0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,       0,            I2     },
01085 {"s.d",     "T,o(b)",       0,    (int) M_S_DOB, INSN_MACRO,          0,            I1     },
01086 {"s.d",     "T,A(b)",       0,    (int) M_S_DAB, INSN_MACRO,          0,            I1     },
01087 {"sdl",     "t,o(b)",       0xb0000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I3     },
01088 {"sdl",     "t,A(b)",       0,    (int) M_SDL_AB,       INSN_MACRO,          0,            I3     },
01089 {"sdr",     "t,o(b)",       0xb4000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I3     },
01090 {"sdr",     "t,A(b)",       0,    (int) M_SDR_AB,       INSN_MACRO,          0,            I3     },
01091 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,      0,            I4|I33 },
01092 {"seb",     "d,w",   0x7c000420, 0xffe007ff,     WR_d|RD_t,           0,            I33    },
01093 {"seh",     "d,w",   0x7c000620, 0xffe007ff,     WR_d|RD_t,           0,            I33    },
01094 {"selsl",   "d,v,t", 0x00000005, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            L1     },
01095 {"selsr",   "d,v,t", 0x00000001, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            L1     },
01096 {"seq",     "d,v,t", 0,    (int) M_SEQ,   INSN_MACRO,          0,            I1     },
01097 {"seq",     "d,v,I", 0,    (int) M_SEQ_I, INSN_MACRO,          0,            I1     },
01098 {"sge",     "d,v,t", 0,    (int) M_SGE,   INSN_MACRO,          0,            I1     },
01099 {"sge",     "d,v,I", 0,    (int) M_SGE_I, INSN_MACRO,          0,            I1     },
01100 {"sgeu",    "d,v,t", 0,    (int) M_SGEU,  INSN_MACRO,          0,            I1     },
01101 {"sgeu",    "d,v,I", 0,    (int) M_SGEU_I,       INSN_MACRO,          0,            I1     },
01102 {"sgt",     "d,v,t", 0,    (int) M_SGT,   INSN_MACRO,          0,            I1     },
01103 {"sgt",     "d,v,I", 0,    (int) M_SGT_I, INSN_MACRO,          0,            I1     },
01104 {"sgtu",    "d,v,t", 0,    (int) M_SGTU,  INSN_MACRO,          0,            I1     },
01105 {"sgtu",    "d,v,I", 0,    (int) M_SGTU_I,       INSN_MACRO,          0,            I1     },
01106 {"sh",      "t,o(b)",       0xa4000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I1     },
01107 {"sh",      "t,A(b)",       0,    (int) M_SH_AB, INSN_MACRO,          0,            I1     },
01108 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX     },
01109 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX|SB1 },
01110 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,     0,            N54    },
01111 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX     },
01112 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX|SB1 },
01113 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,     0,            N54    },
01114 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX     },
01115 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX|SB1 },
01116 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,     0,            N54    },
01117 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX     },
01118 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,     0,            N54    },
01119 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX     },
01120 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX     },
01121 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,       0,            MX|SB1 },
01122 {"sle",     "d,v,t", 0,    (int) M_SLE,   INSN_MACRO,          0,            I1     },
01123 {"sle",     "d,v,I", 0,    (int) M_SLE_I, INSN_MACRO,          0,            I1     },
01124 {"sleu",    "d,v,t", 0,    (int) M_SLEU,  INSN_MACRO,          0,            I1     },
01125 {"sleu",    "d,v,I", 0,    (int) M_SLEU_I,       INSN_MACRO,          0,            I1     },
01126 {"sllv",    "d,t,s", 0x00000004, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I1     },
01127 {"sll",     "d,w,s", 0x00000004, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I1     }, /* sllv */
01128 {"sll",     "d,w,<", 0x00000000, 0xffe0003f,     WR_d|RD_t,           0,            I1     },
01129 {"sll.ob",  "X,Y,Q", 0x78000010, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
01130 {"sll.ob",  "D,S,T[e]",     0x48000010, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
01131 {"sll.ob",  "D,S,k", 0x4bc00010, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
01132 {"sll.qh",  "X,Y,Q", 0x78200010, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
01133 {"slt",     "d,v,t", 0x0000002a, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
01134 {"slt",     "d,v,I", 0,    (int) M_SLT_I, INSN_MACRO,          0,            I1     },
01135 {"slti",    "t,r,j", 0x28000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
01136 {"sltiu",   "t,r,j", 0x2c000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
01137 {"sltu",    "d,v,t", 0x0000002b, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
01138 {"sltu",    "d,v,I", 0,    (int) M_SLTU_I,       INSN_MACRO,          0,            I1     },
01139 {"sne",     "d,v,t", 0,    (int) M_SNE,   INSN_MACRO,          0,            I1     },
01140 {"sne",     "d,v,I", 0,    (int) M_SNE_I, INSN_MACRO,          0,            I1     },
01141 {"sqrt.d",  "D,S",   0x46200004, 0xffff003f, WR_D|RD_S|FP_D,          0,            I2     },
01142 {"sqrt.s",  "D,S",   0x46000004, 0xffff003f, WR_D|RD_S|FP_S,          0,            I2     },
01143 {"sqrt.ps", "D,S",   0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,          0,            SB1    },
01144 {"srav",    "d,t,s", 0x00000007, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I1     },
01145 {"sra",     "d,w,s", 0x00000007, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I1     }, /* srav */
01146 {"sra",     "d,w,<", 0x00000003, 0xffe0003f,     WR_d|RD_t,           0,            I1     },
01147 {"sra.qh",  "X,Y,Q", 0x78200013, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
01148 {"srlv",    "d,t,s", 0x00000006, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I1     },
01149 {"srl",     "d,w,s", 0x00000006, 0xfc0007ff,     WR_d|RD_t|RD_s,             0,            I1     }, /* srlv */
01150 {"srl",     "d,w,<", 0x00000002, 0xffe0003f,     WR_d|RD_t,           0,            I1     },
01151 {"srl.ob",  "X,Y,Q", 0x78000012, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
01152 {"srl.ob",  "D,S,T[e]",     0x48000012, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
01153 {"srl.ob",  "D,S,k", 0x4bc00012, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
01154 {"srl.qh",  "X,Y,Q", 0x78200012, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
01155 /* ssnop is at the start of the table.  */
01156 {"standby", "",         0x42000021, 0xffffffff,  0,                   0,            V1     },
01157 {"sub",     "d,v,t", 0x00000022, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
01158 {"sub",     "d,v,I", 0,    (int) M_SUB_I, INSN_MACRO,          0,            I1     },
01159 {"sub.d",   "D,V,T", 0x46200001, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I1     },
01160 {"sub.s",   "D,V,T", 0x46000001, 0xffe0003f,     WR_D|RD_S|RD_T|FP_S, 0,            I1     },
01161 {"sub.ob",  "X,Y,Q", 0x7800000a, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
01162 {"sub.ob",  "D,S,T", 0x4ac0000a, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
01163 {"sub.ob",  "D,S,T[e]",     0x4800000a, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
01164 {"sub.ob",  "D,S,k", 0x4bc0000a, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
01165 {"sub.ps",  "D,V,T", 0x46c00001, 0xffe0003f,     WR_D|RD_S|RD_T|FP_D, 0,            I5|I33 },
01166 {"sub.qh",  "X,Y,Q", 0x7820000a, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
01167 {"suba.ob", "Y,Q",   0x78000036, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
01168 {"suba.qh", "Y,Q",   0x78200036, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
01169 {"subl.ob", "Y,Q",   0x78000436, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
01170 {"subl.qh", "Y,Q",   0x78200436, 0xfc2007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
01171 {"subu",    "d,v,t", 0x00000023, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
01172 {"subu",    "d,v,I", 0,    (int) M_SUBU_I,       INSN_MACRO,          0,            I1     },
01173 {"suspend", "",         0x42000022, 0xffffffff,  0,                   0,            V1     },
01174 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,    0,            I5|I33|N55},
01175 {"sw",      "t,o(b)",       0xac000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I1     },
01176 {"sw",      "t,A(b)",       0,    (int) M_SW_AB, INSN_MACRO,          0,            I1     },
01177 {"swc0",    "E,o(b)",       0xe0000000, 0xfc000000,     SM|RD_C0|RD_b,              0,            I1     },
01178 {"swc0",    "E,A(b)",       0,    (int) M_SWC0_AB,      INSN_MACRO,          0,            I1     },
01179 {"swc1",    "T,o(b)",       0xe4000000, 0xfc000000,     SM|RD_T|RD_b|FP_S,   0,            I1     },
01180 {"swc1",    "E,o(b)",       0xe4000000, 0xfc000000,     SM|RD_T|RD_b|FP_S,   0,            I1     },
01181 {"swc1",    "T,A(b)",       0,    (int) M_SWC1_AB,      INSN_MACRO,          0,            I1     },
01182 {"swc1",    "E,A(b)",       0,    (int) M_SWC1_AB,      INSN_MACRO,          0,            I1     },
01183 {"s.s",     "T,o(b)",       0xe4000000, 0xfc000000,     SM|RD_T|RD_b|FP_S,   0,            I1     }, /* swc1 */
01184 {"s.s",     "T,A(b)",       0,    (int) M_SWC1_AB,      INSN_MACRO,          0,            I1     },
01185 {"swc2",    "E,o(b)",       0xe8000000, 0xfc000000,     SM|RD_C2|RD_b,              0,            I1     },
01186 {"swc2",    "E,A(b)",       0,    (int) M_SWC2_AB,      INSN_MACRO,          0,            I1     },
01187 {"swc3",    "E,o(b)",       0xec000000, 0xfc000000,     SM|RD_C3|RD_b,              0,            I1     },
01188 {"swc3",    "E,A(b)",       0,    (int) M_SWC3_AB,      INSN_MACRO,          0,            I1     },
01189 {"swl",     "t,o(b)",       0xa8000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I1     },
01190 {"swl",     "t,A(b)",       0,    (int) M_SWL_AB,       INSN_MACRO,          0,            I1     },
01191 {"scache",  "t,o(b)",       0xa8000000, 0xfc000000,     RD_t|RD_b,           0,            I2     }, /* same */
01192 {"scache",  "t,A(b)",       0,    (int) M_SWL_AB,       INSN_MACRO,          0,            I2     }, /* as swl */
01193 {"swr",     "t,o(b)",       0xb8000000, 0xfc000000,     SM|RD_t|RD_b,        0,            I1     },
01194 {"swr",     "t,A(b)",       0,    (int) M_SWR_AB,       INSN_MACRO,          0,            I1     },
01195 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,  RD_t|RD_b,           0,            I2     }, /* same */
01196 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,    INSN_MACRO,          0,            I2     }, /* as swr */
01197 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,      0,            I4|I33 },
01198 {"sync",    "",             0x0000000f, 0xffffffff,     INSN_SYNC,           0,            I2|G1  },
01199 {"sync.p",  "",             0x0000040f, 0xffffffff,     INSN_SYNC,           0,            I2     },
01200 {"sync.l",  "",             0x0000000f, 0xffffffff,     INSN_SYNC,           0,            I2     },
01201 {"synci",   "o(b)",  0x041f0000, 0xfc1f0000,     SM|RD_b,             0,            I33    },
01202 {"syscall", "",             0x0000000c, 0xffffffff,     TRAP,                0,            I1     },
01203 {"syscall", "B",     0x0000000c, 0xfc00003f,     TRAP,                0,            I1     },
01204 {"teqi",    "s,j",   0x040c0000, 0xfc1f0000, RD_s|TRAP,        0,            I2     },
01205 {"teq",           "s,t",    0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,          0,            I2     },
01206 {"teq",           "s,t,q",  0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,          0,            I2     },
01207 {"teq",     "s,j",   0x040c0000, 0xfc1f0000, RD_s|TRAP,        0,            I2     }, /* teqi */
01208 {"teq",     "s,I",   0,    (int) M_TEQ_I, INSN_MACRO,          0,            I2     },
01209 {"tgei",    "s,j",   0x04080000, 0xfc1f0000, RD_s|TRAP,        0,            I2     },
01210 {"tge",           "s,t",    0x00000030, 0xfc00ffff,     RD_s|RD_t|TRAP,             0,            I2     },
01211 {"tge",           "s,t,q",  0x00000030, 0xfc00003f,     RD_s|RD_t|TRAP,             0,            I2     },
01212 {"tge",     "s,j",   0x04080000, 0xfc1f0000, RD_s|TRAP,        0,            I2     }, /* tgei */
01213 {"tge",           "s,I",    0,    (int) M_TGE_I,    INSN_MACRO,              0,            I2     },
01214 {"tgeiu",   "s,j",   0x04090000, 0xfc1f0000, RD_s|TRAP,        0,            I2     },
01215 {"tgeu",    "s,t",   0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,          0,            I2     },
01216 {"tgeu",    "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,          0,            I2     },
01217 {"tgeu",    "s,j",   0x04090000, 0xfc1f0000, RD_s|TRAP,        0,            I2     }, /* tgeiu */
01218 {"tgeu",    "s,I",   0,    (int) M_TGEU_I,       INSN_MACRO,          0,            I2     },
01219 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,             0,            I1     },
01220 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,             0,            I1     },
01221 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,             0,            I1     },
01222 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,             0,            I1     },
01223 {"tlti",    "s,j",   0x040a0000, 0xfc1f0000,     RD_s|TRAP,           0,            I2     },
01224 {"tlt",     "s,t",   0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,          0,            I2     },
01225 {"tlt",     "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,          0,            I2     },
01226 {"tlt",     "s,j",   0x040a0000, 0xfc1f0000,     RD_s|TRAP,           0,            I2     }, /* tlti */
01227 {"tlt",     "s,I",   0,    (int) M_TLT_I, INSN_MACRO,          0,            I2     },
01228 {"tltiu",   "s,j",   0x040b0000, 0xfc1f0000, RD_s|TRAP,        0,            I2     },
01229 {"tltu",    "s,t",   0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,          0,            I2     },
01230 {"tltu",    "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,          0,            I2     },
01231 {"tltu",    "s,j",   0x040b0000, 0xfc1f0000, RD_s|TRAP,        0,            I2     }, /* tltiu */
01232 {"tltu",    "s,I",   0,    (int) M_TLTU_I,       INSN_MACRO,          0,            I2     },
01233 {"tnei",    "s,j",   0x040e0000, 0xfc1f0000, RD_s|TRAP,        0,            I2     },
01234 {"tne",     "s,t",   0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,          0,            I2     },
01235 {"tne",     "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,          0,            I2     },
01236 {"tne",     "s,j",   0x040e0000, 0xfc1f0000, RD_s|TRAP,        0,            I2     }, /* tnei */
01237 {"tne",     "s,I",   0,    (int) M_TNE_I, INSN_MACRO,          0,            I2     },
01238 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D,          0,            I3|I33 },
01239 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f,     WR_D|RD_S|FP_S|FP_D, 0,            I3|I33 },
01240 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I2     },
01241 {"trunc.w.d", "D,S,x",      0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,     0,            I2     },
01242 {"trunc.w.d", "D,S,t",      0,    (int) M_TRUNCWD,      INSN_MACRO,          0,            I1     },
01243 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I2     },
01244 {"trunc.w.s", "D,S,x",      0x4600000d, 0xffff003f,     WR_D|RD_S|FP_S,             0,            I2     },
01245 {"trunc.w.s", "D,S,t",      0,    (int) M_TRUNCWS,      INSN_MACRO,          0,            I1     },
01246 {"uld",     "t,o(b)",       0,    (int) M_ULD,   INSN_MACRO,          0,            I3     },
01247 {"uld",     "t,A(b)",       0,    (int) M_ULD_A, INSN_MACRO,          0,            I3     },
01248 {"ulh",     "t,o(b)",       0,    (int) M_ULH,   INSN_MACRO,          0,            I1     },
01249 {"ulh",     "t,A(b)",       0,    (int) M_ULH_A, INSN_MACRO,          0,            I1     },
01250 {"ulhu",    "t,o(b)",       0,    (int) M_ULHU,  INSN_MACRO,          0,            I1     },
01251 {"ulhu",    "t,A(b)",       0,    (int) M_ULHU_A,       INSN_MACRO,          0,            I1     },
01252 {"ulw",     "t,o(b)",       0,    (int) M_ULW,   INSN_MACRO,          0,            I1     },
01253 {"ulw",     "t,A(b)",       0,    (int) M_ULW_A, INSN_MACRO,          0,            I1     },
01254 {"usd",     "t,o(b)",       0,    (int) M_USD,   INSN_MACRO,          0,            I3     },
01255 {"usd",     "t,A(b)",       0,    (int) M_USD_A, INSN_MACRO,          0,            I3     },
01256 {"ush",     "t,o(b)",       0,    (int) M_USH,   INSN_MACRO,          0,            I1     },
01257 {"ush",     "t,A(b)",       0,    (int) M_USH_A, INSN_MACRO,          0,            I1     },
01258 {"usw",     "t,o(b)",       0,    (int) M_USW,   INSN_MACRO,          0,            I1     },
01259 {"usw",     "t,A(b)",       0,    (int) M_USW_A, INSN_MACRO,          0,            I1     },
01260 {"wach.ob", "Y",     0x7a00003e, 0xffff07ff,     RD_S|FP_D,           WR_MACC,      MX|SB1 },
01261 {"wach.ob", "S",     0x4a00003e, 0xffff07ff,     RD_S,                0,            N54    },
01262 {"wach.qh", "Y",     0x7a20003e, 0xffff07ff,     RD_S|FP_D,           WR_MACC,      MX     },
01263 {"wacl.ob", "Y,Z",   0x7800003e, 0xffe007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX|SB1 },
01264 {"wacl.ob", "S,T",   0x4800003e, 0xffe007ff,     RD_S|RD_T,           0,            N54    },
01265 {"wacl.qh", "Y,Z",   0x7820003e, 0xffe007ff,     RD_S|RD_T|FP_D,             WR_MACC,      MX     },
01266 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                 0,            I3|I32 },
01267 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                 0,            I32|N55       },
01268 {"waiti",   "",             0x42000020, 0xffffffff,     TRAP,                0,            L1     },
01269 {"wrpgpr",  "d,w",   0x41c00000, 0xffe007ff, RD_t,                    0,            I33    },
01270 {"wsbh",    "d,w",   0x7c0000a0, 0xffe007ff,     WR_d|RD_t,           0,            I33    },
01271 {"xor",     "d,v,t", 0x00000026, 0xfc0007ff,     WR_d|RD_s|RD_t,             0,            I1     },
01272 {"xor",     "t,r,I", 0,    (int) M_XOR_I, INSN_MACRO,          0,            I1     },
01273 {"xor.ob",  "X,Y,Q", 0x7800000d, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX|SB1 },
01274 {"xor.ob",  "D,S,T", 0x4ac0000d, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
01275 {"xor.ob",  "D,S,T[e]",     0x4800000d, 0xfe20003f,     WR_D|RD_S|RD_T,             0,            N54    },
01276 {"xor.ob",  "D,S,k", 0x4bc0000d, 0xffe0003f,     WR_D|RD_S|RD_T,             0,            N54    },
01277 {"xor.qh",  "X,Y,Q", 0x7820000d, 0xfc20003f,     WR_D|RD_S|RD_T|FP_D, 0,            MX     },
01278 {"xori",    "t,r,i", 0x38000000, 0xfc000000,     WR_t|RD_s,           0,            I1     },
01279 {"yield",   "s",     0x7c000009, 0xfc1fffff, TRAP|RD_s,        0,            MT32   },
01280 {"yield",   "d,s",   0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,          0,            MT32   },
01281 
01282 /* User Defined Instruction.  */
01283 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01284 {"udi0",     "s,t,+2",      0x70000010, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01285 {"udi0",     "s,+3", 0x70000010, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01286 {"udi0",     "+4",   0x70000010, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01287 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01288 {"udi1",     "s,t,+2",      0x70000011, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01289 {"udi1",     "s,+3", 0x70000011, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01290 {"udi1",     "+4",   0x70000011, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01291 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01292 {"udi2",     "s,t,+2",      0x70000012, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01293 {"udi2",     "s,+3", 0x70000012, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01294 {"udi2",     "+4",   0x70000012, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01295 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01296 {"udi3",     "s,t,+2",      0x70000013, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01297 {"udi3",     "s,+3", 0x70000013, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01298 {"udi3",     "+4",   0x70000013, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01299 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01300 {"udi4",     "s,t,+2",      0x70000014, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01301 {"udi4",     "s,+3", 0x70000014, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01302 {"udi4",     "+4",   0x70000014, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01303 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01304 {"udi5",     "s,t,+2",      0x70000015, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01305 {"udi5",     "s,+3", 0x70000015, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01306 {"udi5",     "+4",   0x70000015, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01307 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01308 {"udi6",     "s,t,+2",      0x70000016, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01309 {"udi6",     "s,+3", 0x70000016, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01310 {"udi6",     "+4",   0x70000016, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01311 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01312 {"udi7",     "s,t,+2",      0x70000017, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01313 {"udi7",     "s,+3", 0x70000017, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01314 {"udi7",     "+4",   0x70000017, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01315 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01316 {"udi8",     "s,t,+2",      0x70000018, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01317 {"udi8",     "s,+3", 0x70000018, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01318 {"udi8",     "+4",   0x70000018, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01319 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01320 {"udi9",      "s,t,+2",     0x70000019, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01321 {"udi9",     "s,+3", 0x70000019, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01322 {"udi9",     "+4",   0x70000019, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01323 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01324 {"udi10",    "s,t,+2",      0x7000001a, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01325 {"udi10",    "s,+3", 0x7000001a, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01326 {"udi10",    "+4",   0x7000001a, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01327 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01328 {"udi11",    "s,t,+2",      0x7000001b, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01329 {"udi11",    "s,+3", 0x7000001b, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01330 {"udi11",    "+4",   0x7000001b, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01331 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01332 {"udi12",    "s,t,+2",      0x7000001c, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01333 {"udi12",    "s,+3", 0x7000001c, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01334 {"udi12",    "+4",   0x7000001c, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01335 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01336 {"udi13",    "s,t,+2",      0x7000001d, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01337 {"udi13",    "s,+3", 0x7000001d, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01338 {"udi13",    "+4",   0x7000001d, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01339 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01340 {"udi14",    "s,t,+2",      0x7000001e, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01341 {"udi14",    "s,+3", 0x7000001e, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01342 {"udi14",    "+4",   0x7000001e, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01343 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f,  WR_d|RD_s|RD_t,             0,            I33    },
01344 {"udi15",    "s,t,+2",      0x7000001f, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01345 {"udi15",    "s,+3", 0x7000001f, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01346 {"udi15",    "+4",   0x7000001f, 0xfc00003f,     WR_d|RD_s|RD_t,             0,            I33    },
01347 
01348 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
01349    instructions so they are here for the latters to take precedence.  */
01350 {"bc2f",    "p",     0x49000000, 0xffff0000,     CBD|RD_CC,           0,            I1     },
01351 {"bc2f",    "N,p",   0x49000000, 0xffe30000,     CBD|RD_CC,           0,            I32    },
01352 {"bc2fl",   "p",     0x49020000, 0xffff0000,     CBL|RD_CC,           0,            I2|T3  },
01353 {"bc2fl",   "N,p",   0x49020000, 0xffe30000,     CBL|RD_CC,           0,            I32    },
01354 {"bc2t",    "p",     0x49010000, 0xffff0000,     CBD|RD_CC,           0,            I1     },
01355 {"bc2t",    "N,p",   0x49010000, 0xffe30000,     CBD|RD_CC,           0,            I32    },
01356 {"bc2tl",   "p",     0x49030000, 0xffff0000,     CBL|RD_CC,           0,            I2|T3  },
01357 {"bc2tl",   "N,p",   0x49030000, 0xffe30000,     CBL|RD_CC,           0,            I32    },
01358 {"cfc2",    "t,G",   0x48400000, 0xffe007ff,     LCD|WR_t|RD_C2,             0,            I1     },
01359 {"ctc2",    "t,G",   0x48c00000, 0xffe007ff,     COD|RD_t|WR_CC,             0,            I1     },
01360 {"dmfc2",   "t,G",   0x48200000, 0xffe007ff,     LCD|WR_t|RD_C2,             0,            I3     },
01361 {"dmfc2",   "t,G,H", 0x48200000, 0xffe007f8,     LCD|WR_t|RD_C2,             0,            I64    },
01362 {"dmtc2",   "t,G",   0x48a00000, 0xffe007ff,     COD|RD_t|WR_C2|WR_CC,       0,            I3     },
01363 {"dmtc2",   "t,G,H", 0x48a00000, 0xffe007f8,     COD|RD_t|WR_C2|WR_CC,       0,            I64    },
01364 {"mfc2",    "t,G",   0x48000000, 0xffe007ff,     LCD|WR_t|RD_C2,             0,            I1     },
01365 {"mfc2",    "t,G,H", 0x48000000, 0xffe007f8,     LCD|WR_t|RD_C2,             0,            I32    },
01366 {"mfhc2",   "t,G",   0x48600000, 0xffe007ff,     LCD|WR_t|RD_C2,             0,            I33    },
01367 {"mfhc2",   "t,G,H", 0x48600000, 0xffe007f8,     LCD|WR_t|RD_C2,             0,            I33    },
01368 {"mfhc2",   "t,i",   0x48600000, 0xffe00000,     LCD|WR_t|RD_C2,             0,            I33    },
01369 {"mtc2",    "t,G",   0x48800000, 0xffe007ff,     COD|RD_t|WR_C2|WR_CC,       0,            I1     },
01370 {"mtc2",    "t,G,H", 0x48800000, 0xffe007f8,     COD|RD_t|WR_C2|WR_CC,       0,            I32    },
01371 {"mthc2",   "t,G",   0x48e00000, 0xffe007ff,     COD|RD_t|WR_C2|WR_CC,       0,            I33    },
01372 {"mthc2",   "t,G,H", 0x48e00000, 0xffe007f8,     COD|RD_t|WR_C2|WR_CC,       0,            I33    },
01373 {"mthc2",   "t,i",   0x48e00000, 0xffe00000,     COD|RD_t|WR_C2|WR_CC,       0,            I33    },
01374 
01375 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
01376    instructions, so they are here for the latters to take precedence.  */
01377 {"bc3f",    "p",     0x4d000000, 0xffff0000,     CBD|RD_CC,           0,            I1     },
01378 {"bc3fl",   "p",     0x4d020000, 0xffff0000,     CBL|RD_CC,           0,            I2|T3  },
01379 {"bc3t",    "p",     0x4d010000, 0xffff0000,     CBD|RD_CC,           0,            I1     },
01380 {"bc3tl",   "p",     0x4d030000, 0xffff0000,     CBL|RD_CC,           0,            I2|T3  },
01381 {"cfc3",    "t,G",   0x4c400000, 0xffe007ff,     LCD|WR_t|RD_C3,             0,            I1     },
01382 {"ctc3",    "t,G",   0x4cc00000, 0xffe007ff,     COD|RD_t|WR_CC,             0,            I1     },
01383 {"dmfc3",   "t,G",   0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,   0,            I3     },
01384 {"dmtc3",   "t,G",   0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,    0,            I3     },
01385 {"mfc3",    "t,G",   0x4c000000, 0xffe007ff,     LCD|WR_t|RD_C3,             0,            I1     },
01386 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,       0,            I32     },
01387 {"mtc3",    "t,G",   0x4c800000, 0xffe007ff,     COD|RD_t|WR_C3|WR_CC,       0,            I1     },
01388 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,          I32     },
01389 
01390 /* No hazard protection on coprocessor instructions--they shouldn't
01391    change the state of the processor and if they do it's up to the
01392    user to put in nops as necessary.  These are at the end so that the
01393    disassembler recognizes more specific versions first.  */
01394 {"c0",      "C",     0x42000000, 0xfe000000,     0,                   0,            I1     },
01395 {"c1",      "C",     0x46000000, 0xfe000000,     0,                   0,            I1     },
01396 {"c2",      "C",     0x4a000000, 0xfe000000,     0,                   0,            I1     },
01397 {"c3",      "C",     0x4e000000, 0xfe000000,     0,                   0,            I1     },
01398 {"cop0",     "C",    0,    (int) M_COP0,  INSN_MACRO,          0,            I1     },
01399 {"cop1",     "C",    0,    (int) M_COP1,  INSN_MACRO,          0,            I1     },
01400 {"cop2",     "C",    0,    (int) M_COP2,  INSN_MACRO,          0,            I1     },
01401 {"cop3",     "C",    0,    (int) M_COP3,  INSN_MACRO,          0,            I1     },
01402   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
01403      4010 any more, so move this insn out of the way.  If the object
01404      format gave us more info, we could do this right.  */
01405 {"addciu",  "t,r,j", 0x70000000, 0xfc000000,     WR_t|RD_s,           0,            L1     },
01406 /* MIPS DSP ASE */
01407 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01408 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t,        0,            D64    },
01409 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t,        0,            D64    },
01410 {"absq_s.w", "d,t",  0x7c000452, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01411 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01412 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01413 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01414 {"addq_s.ph", "d,s,t",      0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01415 {"addq_s.pw", "d,s,t",      0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01416 {"addq_s.qh", "d,s,t",      0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01417 {"addq_s.w", "d,s,t",       0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01418 {"addsc",   "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01419 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01420 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01421 {"addu_s.ob", "d,s,t",      0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01422 {"addu_s.qb", "d,s,t",      0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01423 {"addwc",   "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01424 {"bitrev",  "d,t",   0x7c0006d2, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01425 {"bposge32", "p",    0x041c0000, 0xffff0000, CBD,                     0,            D32    },
01426 {"bposge64", "p",    0x041d0000, 0xffff0000, CBD,                     0,            D64    },
01427 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t,        0,            D32    },
01428 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01429 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01430 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D64    },
01431 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D32    },
01432 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D64    },
01433 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D32    },
01434 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D64    },
01435 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D32    },
01436 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t,        0,            D32    },
01437 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01438 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01439 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t,        0,            D32    },
01440 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01441 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01442 {"cmpu.eq.ob", "s,t",       0x7c000015, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01443 {"cmpu.eq.qb", "s,t",       0x7c000011, 0xfc00ffff, RD_s|RD_t,        0,            D32    },
01444 {"cmpu.le.ob", "s,t",       0x7c000095, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01445 {"cmpu.le.qb", "s,t",       0x7c000091, 0xfc00ffff, RD_s|RD_t,        0,            D32    },
01446 {"cmpu.lt.ob", "s,t",       0x7c000055, 0xfc00ffff, RD_s|RD_t,        0,            D64    },
01447 {"cmpu.lt.qb", "s,t",       0x7c000051, 0xfc00ffff, RD_s|RD_t,        0,            D32    },
01448 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,      0,            D64    },
01449 {"dextpdpv", "t,7,s",       0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,            D64    },
01450 {"dextp",   "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01451 {"dextpv",  "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D64    },
01452 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01453 {"dextr_r.l", "t,7,6",      0x7c00053c, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01454 {"dextr_rs.l", "t,7,6",     0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01455 {"dextr_rs.w", "t,7,6",     0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01456 {"dextr_r.w", "t,7,6",      0x7c00013c, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01457 {"dextr_s.h", "t,7,6",      0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01458 {"dextrv.l", "t,7,s",       0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D64    },
01459 {"dextrv_r.l", "t,7,s",     0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D64    },
01460 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,      0,            D64    },
01461 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,      0,            D64    },
01462 {"dextrv_r.w", "t,7,s",     0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D64    },
01463 {"dextrv_s.h", "t,7,s",     0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D64    },
01464 {"dextrv.w", "t,7,s",       0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D64    },
01465 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a,        0,            D64    },
01466 {"dinsv",   "t,s",   0x7c00000d, 0xfc00ffff, WR_t|RD_s,        0,            D64    },
01467 {"dmadd",   "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01468 {"dmaddu",  "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01469 {"dmsub",   "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01470 {"dmsubu",  "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01471 {"dmthlip", "s,7",   0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,     0,            D64    },
01472 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D64    },
01473 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D32    },
01474 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D32    },
01475 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D64    },
01476 {"dpau.h.obl", "7,s,t",     0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01477 {"dpau.h.obr", "7,s,t",     0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01478 {"dpau.h.qbl", "7,s,t",     0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D32    },
01479 {"dpau.h.qbr", "7,s,t",     0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D32    },
01480 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D64    },
01481 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D32    },
01482 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D32    },
01483 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D64    },
01484 {"dpsu.h.obl", "7,s,t",     0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01485 {"dpsu.h.obr", "7,s,t",     0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D64    },
01486 {"dpsu.h.qbl", "7,s,t",     0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D32    },
01487 {"dpsu.h.qbr", "7,s,t",     0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,            D32    },
01488 {"dshilo",  "7,:",   0x7c0006bc, 0xfc07e7ff, MOD_a,                   0,            D64    },
01489 {"dshilov", "7,s",   0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,              0,            D64    },
01490 {"extpdp",  "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,      0,            D32    },
01491 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,            D32    },
01492 {"extp",    "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,        0,            D32    },
01493 {"extpv",   "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D32    },
01494 {"extr_rs.w", "t,7,6",      0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,        0,            D32    },
01495 {"extr_r.w", "t,7,6",       0x7c000138, 0xfc00e7ff, WR_t|RD_a,        0,            D32    },
01496 {"extr_s.h", "t,7,6",       0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,        0,            D32    },
01497 {"extrv_rs.w", "t,7,s",     0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D32    },
01498 {"extrv_r.w", "t,7,s",      0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D32    },
01499 {"extrv_s.h", "t,7,s",      0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D32    },
01500 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,          0,            D32    },
01501 {"extr.w",  "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a,        0,            D32    },
01502 {"insv",    "t,s",   0x7c00000c, 0xfc00ffff, WR_t|RD_s,        0,            D32    },
01503 {"lbux",    "d,t(b)",       0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,      0,            D32    },
01504 {"ldx",     "d,t(b)",       0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,      0,            D64    },
01505 {"lhx",     "d,t(b)",       0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,      0,            D32    },
01506 {"lwx",     "d,t(b)",       0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,      0,            D32    },
01507 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D32    },
01508 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D32    },
01509 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D64    },
01510 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D64    },
01511 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D64    },
01512 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D64    },
01513 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D64    },
01514 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D64    },
01515 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D32    },
01516 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,            D32    },
01517 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D64    },
01518 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D64    },
01519 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D64    },
01520 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,            D64    },
01521 {"modsub",  "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01522 {"mthlip",  "s,7",   0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,     0,            D32    },
01523 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             D64    },
01524 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             D64    },
01525 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32    },
01526 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32    },
01527 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             D32    },
01528 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             D32    },
01529 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             D64    },
01530 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             D64    },
01531 {"mulq_rs.ph", "d,s,t",     0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,  0,            D32    },
01532 {"mulq_rs.qh", "d,s,t",     0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,  0,            D64    },
01533 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D64    },
01534 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D32    },
01535 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,            D64    },
01536 {"packrl.ph", "d,s,t",      0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01537 {"packrl.pw", "d,s,t",      0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01538 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01539 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01540 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01541 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01542 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01543 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01544 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,           0,            D64    },
01545 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01546 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,           0,            D64    },
01547 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01548 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01549 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,         0,            D32    },
01550 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,          0,            D32    },
01551 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,         0,            D32    },
01552 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,          0,            D32    },
01553 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,         0,            D64    },
01554 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01555 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,         0,            D64    },
01556 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01557 {"preceq.w.phl", "d,t",     0x7c000312, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01558 {"preceq.w.phr", "d,t",     0x7c000352, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01559 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,          0,            D32    },
01560 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,           0,            D32    },
01561 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,          0,            D32    },
01562 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,           0,            D32    },
01563 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01564 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,           0,            D64    },
01565 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,          0,            D64    },
01566 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,           0,            D64    },
01567 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,     0,            D64    },
01568 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D32    },
01569 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,      0,            D64    },
01570 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,     0,            D32    },
01571 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,     0,            D64    },
01572 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,   0,            D32    },
01573 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,  0,            D64    },
01574 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,  0,            D64    },
01575 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,  0,            D32    },
01576 {"raddu.l.ob", "d,s",       0x7c000514, 0xfc1f07ff, WR_d|RD_s,        0,            D64    },
01577 {"raddu.w.qb", "d,s",       0x7c000510, 0xfc1f07ff, WR_d|RD_s,        0,            D32    },
01578 {"rddsp",   "d",     0x7fff04b8, 0xffff07ff, WR_d,                    0,            D32    },
01579 {"rddsp",   "d,'",   0x7c0004b8, 0xffc007ff, WR_d,                    0,            D32    },
01580 {"repl.ob", "d,5",   0x7c000096, 0xff0007ff, WR_d,                    0,            D64    },
01581 {"repl.ph", "d,@",   0x7c000292, 0xfc0007ff, WR_d,                    0,            D32    },
01582 {"repl.pw", "d,@",   0x7c000496, 0xfc0007ff, WR_d,                    0,            D64    },
01583 {"repl.qb", "d,5",   0x7c000092, 0xff0007ff, WR_d,                    0,            D32    },
01584 {"repl.qh", "d,@",   0x7c000296, 0xfc0007ff, WR_d,                    0,            D64    },
01585 {"replv.ob", "d,t",  0x7c0000d6, 0xffe007ff, WR_d|RD_t,        0,            D64    },
01586 {"replv.ph", "d,t",  0x7c0002d2, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01587 {"replv.pw", "d,t",  0x7c0004d6, 0xffe007ff, WR_d|RD_t,        0,            D64    },
01588 {"replv.qb", "d,t",  0x7c0000d2, 0xffe007ff, WR_d|RD_t,        0,            D32    },
01589 {"replv.qh", "d,t",  0x7c0002d6, 0xffe007ff, WR_d|RD_t,        0,            D64    },
01590 {"shilo",   "7,0",   0x7c0006b8, 0xfc0fe7ff, MOD_a,                   0,            D32    },
01591 {"shilov",  "7,s",   0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,              0,            D32    },
01592 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t,        0,            D64    },
01593 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t,        0,            D32    },
01594 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t,        0,            D64    },
01595 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t,        0,            D32    },
01596 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t,        0,            D64    },
01597 {"shll_s.ph", "d,t,4",      0x7c000313, 0xfe0007ff, WR_d|RD_t,        0,            D32    },
01598 {"shll_s.pw", "d,t,6",      0x7c000517, 0xfc0007ff, WR_d|RD_t,        0,            D64    },
01599 {"shll_s.qh", "d,t,4",      0x7c000317, 0xfe0007ff, WR_d|RD_t,        0,            D64    },
01600 {"shll_s.w", "d,t,6",       0x7c000513, 0xfc0007ff, WR_d|RD_t,        0,            D32    },
01601 {"shllv.ob", "d,t,s",       0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01602 {"shllv.ph", "d,t,s",       0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01603 {"shllv.pw", "d,t,s",       0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01604 {"shllv.qb", "d,t,s",       0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01605 {"shllv.qh", "d,t,s",       0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01606 {"shllv_s.ph", "d,t,s",     0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01607 {"shllv_s.pw", "d,t,s",     0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01608 {"shllv_s.qh", "d,t,s",     0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01609 {"shllv_s.w", "d,t,s",      0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01610 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t,        0,            D32    },
01611 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t,        0,            D64    },
01612 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t,        0,            D64    },
01613 {"shra_r.ph", "d,t,4",      0x7c000353, 0xfe0007ff, WR_d|RD_t,        0,            D32    },
01614 {"shra_r.pw", "d,t,6",      0x7c000557, 0xfc0007ff, WR_d|RD_t,        0,            D64    },
01615 {"shra_r.qh", "d,t,4",      0x7c000357, 0xfe0007ff, WR_d|RD_t,        0,            D64    },
01616 {"shra_r.w", "d,t,6",       0x7c000553, 0xfc0007ff, WR_d|RD_t,        0,            D32    },
01617 {"shrav.ph", "d,t,s",       0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01618 {"shrav.pw", "d,t,s",       0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01619 {"shrav.qh", "d,t,s",       0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01620 {"shrav_r.ph", "d,t,s",     0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01621 {"shrav_r.pw", "d,t,s",     0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01622 {"shrav_r.qh", "d,t,s",     0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01623 {"shrav_r.w", "d,t,s",      0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01624 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t,        0,            D64    },
01625 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t,        0,            D32    },
01626 {"shrlv.ob", "d,t,s",       0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01627 {"shrlv.qb", "d,t,s",       0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01628 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01629 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01630 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01631 {"subq_s.ph", "d,s,t",      0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01632 {"subq_s.pw", "d,s,t",      0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01633 {"subq_s.qh", "d,s,t",      0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01634 {"subq_s.w", "d,s,t",       0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01635 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01636 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01637 {"subu_s.ob", "d,s,t",      0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D64    },
01638 {"subu_s.qb", "d,s,t",      0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,          0,            D32    },
01639 {"wrdsp",   "s",     0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,           0,            D32    },
01640 {"wrdsp",   "s,8",   0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,           0,            D32    },
01641 /* MIPS DSP ASE Rev2 */
01642 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33   },
01643 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01644 {"addu_s.ph", "d,s,t",      0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01645 {"adduh.qb", "d,s,t",       0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01646 {"adduh_r.qb", "d,s,t",     0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01647 {"append",  "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33   },
01648 {"balign",  "t,s,I", 0,    (int) M_BALIGN,       INSN_MACRO,             0,              D33      },
01649 {"balign",  "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33   },
01650 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33       },
01651 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33       },
01652 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33       },
01653 {"dpa.w.ph", "7,s,t",       0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33   },
01654 {"dps.w.ph", "7,s,t",       0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33   },
01655 {"mul.ph",  "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33   },
01656 {"mul_s.ph", "d,s,t",       0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33   },
01657 {"mulq_rs.w", "d,s,t",      0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33   },
01658 {"mulq_s.ph", "d,s,t",      0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33   },
01659 {"mulq_s.w", "d,s,t",       0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33   },
01660 {"mulsa.w.ph", "7,s,t",     0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33   },
01661 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33       },
01662 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33       },
01663 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33       },
01664 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33   },
01665 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33   },
01666 {"shra_r.qb", "d,t,3",      0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33   },
01667 {"shrav.qb", "d,t,s",       0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01668 {"shrav_r.qb", "d,t,s",     0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01669 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33   },
01670 {"shrlv.ph", "d,t,s",       0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01671 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01672 {"subu_s.ph", "d,s,t",      0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01673 {"subuh.qb", "d,s,t",       0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01674 {"subuh_r.qb", "d,s,t",     0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33   },
01675 {"addqh.ph", "d,s,t",       0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01676 {"addqh_r.ph", "d,s,t",     0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01677 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01678 {"addqh_r.w", "d,s,t",      0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01679 {"subqh.ph", "d,s,t",       0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01680 {"subqh_r.ph", "d,s,t",     0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01681 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01682 {"subqh_r.w", "d,s,t",      0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,          0,              D33  },
01683 {"dpax.w.ph", "7,s,t",      0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,              D33  },
01684 {"dpsx.w.ph", "7,s,t",      0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,  0,              D33  },
01685 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D33  },
01686 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,              D33  },
01687 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D33  },
01688 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,   0,              D33  },
01689 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
01690 {"bc0f",    "p",     0x41000000, 0xffff0000,     CBD|RD_CC,           0,            I1     },
01691 {"bc0fl",   "p",     0x41020000, 0xffff0000,     CBL|RD_CC,           0,            I2|T3  },
01692 {"bc0t",    "p",     0x41010000, 0xffff0000,     CBD|RD_CC,           0,            I1     },
01693 {"bc0tl",   "p",     0x41030000, 0xffff0000,     CBL|RD_CC,           0,            I2|T3  },
01694 };
01695 
01696 #define MIPS_NUM_OPCODES \
01697        ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
01698 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
01699 
01700 /* const removed from the following to allow for dynamic extensions to the
01701  * built-in instruction set. */
01702 struct mips_opcode *mips_opcodes =
01703   (struct mips_opcode *) mips_builtin_opcodes;
01704 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
01705 #undef MIPS_NUM_OPCODES