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cell-binutils  2.17cvs20070401
mep-desc.h
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00001 /* CPU data header for mep.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef MEP_CPU_H
00026 #define MEP_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH mep
00031 
00032 /* Given symbol S, return mep_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) mep##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) mep_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_MEPF
00042 
00043 #define CGEN_INSN_LSB0_P 0
00044 
00045 /* Minimum size of any insn (in bytes).  */
00046 #define CGEN_MIN_INSN_SIZE 2
00047 
00048 /* Maximum size of any insn (in bytes).  */
00049 #define CGEN_MAX_INSN_SIZE 4
00050 
00051 #define CGEN_INT_INSN_P 1
00052 
00053 /* Maximum number of syntax elements in an instruction.  */
00054 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17
00055 
00056 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00057    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00058    we can't hash on everything up to the space.  */
00059 #define CGEN_MNEMONIC_OPERANDS
00060 
00061 /* Maximum number of fields in an instruction.  */
00062 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11
00063 
00064 /* Enums.  */
00065 
00066 /* Enum declaration for major opcodes.  */
00067 typedef enum major {
00068   MAJ_0, MAJ_1, MAJ_2, MAJ_3
00069  , MAJ_4, MAJ_5, MAJ_6, MAJ_7
00070  , MAJ_8, MAJ_9, MAJ_10, MAJ_11
00071  , MAJ_12, MAJ_13, MAJ_14, MAJ_15
00072 } MAJOR;
00073 
00074 /* Enum declaration for condition opcode enum.  */
00075 typedef enum fmax_cond {
00076   FMAX_F, FMAX_U, FMAX_E, FMAX_UE
00077  , FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE
00078  , FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI
00079  , FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI
00080 } FMAX_COND;
00081 
00082 /* Attributes.  */
00083 
00084 /* Enum declaration for machine type selection.  */
00085 typedef enum mach_attr {
00086   MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX
00087 } MACH_ATTR;
00088 
00089 /* Enum declaration for instruction set selection.  */
00090 typedef enum isa_attr {
00091   ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16
00092  , ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX
00093 } ISA_ATTR;
00094 
00095 /* Enum declaration for datatype to use for C intrinsics mapping.  */
00096 typedef enum cdata_attr {
00097   CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT
00098  , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT
00099  , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
00100 } CDATA_ATTR;
00101 
00102 /* Enum declaration for .  */
00103 typedef enum config_attr {
00104   CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX
00105 } CONFIG_ATTR;
00106 
00107 /* Number of architecture variants.  */
00108 #define MAX_ISAS  ((int) ISA_MAX)
00109 #define MAX_MACHS ((int) MACH_MAX)
00110 
00111 /* Ifield support.  */
00112 
00113 /* Ifield attribute indices.  */
00114 
00115 /* Enum declaration for cgen_ifld attrs.  */
00116 typedef enum cgen_ifld_attr {
00117   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00118  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00119  , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
00120 } CGEN_IFLD_ATTR;
00121 
00122 /* Number of non-boolean elements in cgen_ifld_attr.  */
00123 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00124 
00125 /* cgen_ifld attribute accessor macros.  */
00126 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00127 #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
00128 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00129 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00130 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00131 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00132 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00133 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00134 
00135 /* Enum declaration for mep ifield types.  */
00136 typedef enum ifield_type {
00137   MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN
00138  , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2
00139  , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN
00140  , MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI
00141  , MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1
00142  , MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5
00143  , MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9
00144  , MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13
00145  , MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17
00146  , MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21
00147  , MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25
00148  , MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29
00149  , MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2
00150  , MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N
00151  , MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6
00152  , MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16
00153  , MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8
00154  , MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16
00155  , MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2
00156  , MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
00157  , MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
00158  , MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
00159  , MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4
00160  , MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4
00161  , MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1
00162  , MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN
00163  , MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX
00164 } IFIELD_TYPE;
00165 
00166 #define MAX_IFLD ((int) MEP_F_MAX)
00167 
00168 /* Hardware attribute indices.  */
00169 
00170 /* Enum declaration for cgen_hw attrs.  */
00171 typedef enum cgen_hw_attr {
00172   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00173  , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH
00174  , CGEN_HW_ISA, CGEN_HW_END_NBOOLS
00175 } CGEN_HW_ATTR;
00176 
00177 /* Number of non-boolean elements in cgen_hw_attr.  */
00178 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00179 
00180 /* cgen_hw attribute accessor macros.  */
00181 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00182 #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
00183 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00184 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00185 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00186 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00187 #define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0)
00188 
00189 /* Enum declaration for mep hardware types.  */
00190 typedef enum cgen_hw_type {
00191   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00192  , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
00193  , HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX
00194  , HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX
00195 } CGEN_HW_TYPE;
00196 
00197 #define MAX_HW ((int) HW_MAX)
00198 
00199 /* Operand attribute indices.  */
00200 
00201 /* Enum declaration for cgen_operand attrs.  */
00202 typedef enum cgen_operand_attr {
00203   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00204  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00205  , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
00206  , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS
00207 } CGEN_OPERAND_ATTR;
00208 
00209 /* Number of non-boolean elements in cgen_operand_attr.  */
00210 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00211 
00212 /* cgen_operand attribute accessor macros.  */
00213 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00214 #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
00215 #define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00216 #define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00217 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00218 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00219 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00220 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00221 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00222 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00223 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00224 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00225 #define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0)
00226 
00227 /* Enum declaration for mep operand types.  */
00228 typedef enum cgen_operand_type {
00229   MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM
00230  , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC
00231  , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL
00232  , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S
00233  , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP
00234  , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0
00235  , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW
00236  , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG
00237  , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP
00238  , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN
00239  , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64
00240  , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2
00241  , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2
00242  , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16
00243  , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8
00244  , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3
00245  , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
00246  , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
00247  , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
00248  , MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD
00249  , MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT
00250  , MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR
00251  , MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX
00252 } CGEN_OPERAND_TYPE;
00253 
00254 /* Number of operands types.  */
00255 #define MAX_OPERANDS 90
00256 
00257 /* Maximum number of operands referenced by any insn.  */
00258 #define MAX_OPERAND_INSTANCES 8
00259 
00260 /* Insn attribute indices.  */
00261 
00262 /* Enum declaration for cgen_insn attrs.  */
00263 typedef enum cgen_insn_attr {
00264   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00265  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00266  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN
00267  , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN
00268  , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN
00269  , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN
00270  , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
00271  , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
00272  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
00273  , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS
00274 } CGEN_INSN_ATTR;
00275 
00276 /* Number of non-boolean elements in cgen_insn_attr.  */
00277 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00278 
00279 /* cgen_insn attribute accessor macros.  */
00280 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00281 #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
00282 #define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
00283 #define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
00284 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00285 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00286 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00287 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00288 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00289 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00290 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00291 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00292 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00293 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00294 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0)
00295 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0)
00296 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0)
00297 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0)
00298 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0)
00299 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0)
00300 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0)
00301 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0)
00302 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0)
00303 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0)
00304 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0)
00305 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0)
00306 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0)
00307 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0)
00308 #define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0)
00309 #define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0)
00310 #define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0)
00311 #define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0)
00312 #define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0)
00313 #define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0)
00314 #define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0)
00315 #define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0)
00316 
00317 /* cgen.h uses things we just defined.  */
00318 #include "opcode/cgen.h"
00319 
00320 extern const struct cgen_ifld mep_cgen_ifld_table[];
00321 
00322 /* Attributes.  */
00323 extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[];
00324 extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[];
00325 extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[];
00326 extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[];
00327 
00328 /* Hardware decls.  */
00329 
00330 extern CGEN_KEYWORD mep_cgen_opval_h_gpr;
00331 extern CGEN_KEYWORD mep_cgen_opval_h_csr;
00332 extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
00333 extern CGEN_KEYWORD mep_cgen_opval_h_cr;
00334 extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
00335 extern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax;
00336 extern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax;
00337 
00338 extern const CGEN_HW_ENTRY mep_cgen_hw_table[];
00339 
00340 
00341 
00342 #endif /* MEP_CPU_H */