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cell-binutils  2.17cvs20070401
mep-desc.c
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00001 /* CPU data for mep.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "mep-desc.h"
00032 #include "mep-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "mep", MACH_MEP },
00050   { "h1", MACH_H1 },
00051   { "max", MACH_MAX },
00052   { 0, 0 }
00053 };
00054 
00055 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00056 {
00057   { "mep", ISA_MEP },
00058   { "ext_core1", ISA_EXT_CORE1 },
00059   { "ext_core2", ISA_EXT_CORE2 },
00060   { "ext_cop2_16", ISA_EXT_COP2_16 },
00061   { "ext_cop2_32", ISA_EXT_COP2_32 },
00062   { "ext_cop2_48", ISA_EXT_COP2_48 },
00063   { "ext_cop2_64", ISA_EXT_COP2_64 },
00064   { "max", ISA_MAX },
00065   { 0, 0 }
00066 };
00067 
00068 static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
00069 {
00070   { "LABEL", CDATA_LABEL },
00071   { "REGNUM", CDATA_REGNUM },
00072   { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
00073   { "FMAX_INT", CDATA_FMAX_INT },
00074   { "POINTER", CDATA_POINTER },
00075   { "LONG", CDATA_LONG },
00076   { "ULONG", CDATA_ULONG },
00077   { "SHORT", CDATA_SHORT },
00078   { "USHORT", CDATA_USHORT },
00079   { "CHAR", CDATA_CHAR },
00080   { "UCHAR", CDATA_UCHAR },
00081   { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
00082   { 0, 0 }
00083 };
00084 
00085 static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED = 
00086 {
00087   {"integer", 1},
00088   { 0, 0 }
00089 };
00090 
00091 static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED = 
00092 {
00093   {"integer", 0},
00094   { 0, 0 }
00095 };
00096 
00097 static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
00098 {
00099   { "NONE", CONFIG_NONE },
00100   { "simple", CONFIG_SIMPLE },
00101   { "fmax", CONFIG_FMAX },
00102   { 0, 0 }
00103 };
00104 
00105 const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
00106 {
00107   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00108   { "ISA", & ISA_attr[0], & ISA_attr[0] },
00109   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00110   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00111   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00112   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00113   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00114   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00115   { 0, 0, 0 }
00116 };
00117 
00118 const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
00119 {
00120   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00121   { "ISA", & ISA_attr[0], & ISA_attr[0] },
00122   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00123   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00124   { "PC", &bool_attr[0], &bool_attr[0] },
00125   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00126   { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
00127   { 0, 0, 0 }
00128 };
00129 
00130 const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
00131 {
00132   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00133   { "ISA", & ISA_attr[0], & ISA_attr[0] },
00134   { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
00135   { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
00136   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00137   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00138   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00139   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00140   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00141   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00142   { "RELAX", &bool_attr[0], &bool_attr[0] },
00143   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00144   { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
00145   { 0, 0, 0 }
00146 };
00147 
00148 const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
00149 {
00150   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00151   { "ISA", & ISA_attr[0], & ISA_attr[0] },
00152   { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
00153   { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
00154   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00155   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00156   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00157   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00158   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00159   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00160   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00161   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00162   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00163   { "PBB", &bool_attr[0], &bool_attr[0] },
00164   { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
00165   { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
00166   { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
00167   { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
00168   { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
00169   { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
00170   { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
00171   { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
00172   { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
00173   { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
00174   { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
00175   { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
00176   { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
00177   { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
00178   { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
00179   { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
00180   { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
00181   { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
00182   { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
00183   { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
00184   { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
00185   { "VOLATILE", &bool_attr[0], &bool_attr[0] },
00186   { 0, 0, 0 }
00187 };
00188 
00189 /* Instruction set variants.  */
00190 
00191 static const CGEN_ISA mep_cgen_isa_table[] = {
00192   { "mep", 32, 32, 16, 32 },
00193   { "ext_core1", 32, 32, 16, 32 },
00194   { "ext_core2", 32, 32, 16, 32 },
00195   { "ext_cop2_16", 32, 32, 65535, 0 },
00196   { "ext_cop2_32", 32, 32, 65535, 0 },
00197   { "ext_cop2_48", 32, 32, 65535, 0 },
00198   { "ext_cop2_64", 32, 32, 65535, 0 },
00199   { 0, 0, 0, 0, 0 }
00200 };
00201 
00202 /* Machine variants.  */
00203 
00204 static const CGEN_MACH mep_cgen_mach_table[] = {
00205   { "mep", "mep", MACH_MEP, 16 },
00206   { "h1", "h1", MACH_H1, 16 },
00207   { 0, 0, 0, 0 }
00208 };
00209 
00210 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
00211 {
00212   { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
00213   { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
00214   { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
00215   { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
00216   { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
00217   { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
00218   { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
00219   { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
00220   { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
00221   { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
00222   { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
00223   { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
00224   { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
00225   { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
00226   { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
00227   { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
00228   { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
00229   { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
00230   { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
00231   { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
00232 };
00233 
00234 CGEN_KEYWORD mep_cgen_opval_h_gpr =
00235 {
00236   & mep_cgen_opval_h_gpr_entries[0],
00237   20,
00238   0, 0, 0, 0, ""
00239 };
00240 
00241 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
00242 {
00243   { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
00244   { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
00245   { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
00246   { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
00247   { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
00248   { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
00249   { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
00250   { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
00251   { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
00252   { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
00253   { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
00254   { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
00255   { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
00256   { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
00257   { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
00258   { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
00259   { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
00260   { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
00261   { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
00262   { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
00263   { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
00264   { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
00265   { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
00266   { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 }
00267 };
00268 
00269 CGEN_KEYWORD mep_cgen_opval_h_csr =
00270 {
00271   & mep_cgen_opval_h_csr_entries[0],
00272   24,
00273   0, 0, 0, 0, ""
00274 };
00275 
00276 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
00277 {
00278   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
00279   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
00280   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
00281   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
00282   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
00283   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
00284   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
00285   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
00286   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
00287   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
00288   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
00289   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
00290   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
00291   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
00292   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
00293   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
00294   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
00295   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
00296   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
00297   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
00298   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
00299   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
00300   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
00301   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
00302   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
00303   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
00304   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
00305   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
00306   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
00307   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
00308   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
00309   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
00310 };
00311 
00312 CGEN_KEYWORD mep_cgen_opval_h_cr64 =
00313 {
00314   & mep_cgen_opval_h_cr64_entries[0],
00315   32,
00316   0, 0, 0, 0, ""
00317 };
00318 
00319 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
00320 {
00321   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
00322   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
00323   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
00324   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
00325   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
00326   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
00327   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
00328   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
00329   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
00330   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
00331   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
00332   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
00333   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
00334   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
00335   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
00336   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
00337   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
00338   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
00339   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
00340   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
00341   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
00342   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
00343   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
00344   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
00345   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
00346   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
00347   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
00348   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
00349   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
00350   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
00351   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
00352   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
00353 };
00354 
00355 CGEN_KEYWORD mep_cgen_opval_h_cr =
00356 {
00357   & mep_cgen_opval_h_cr_entries[0],
00358   32,
00359   0, 0, 0, 0, ""
00360 };
00361 
00362 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
00363 {
00364   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
00365   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
00366   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
00367   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
00368   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
00369   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
00370   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
00371   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
00372   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
00373   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
00374   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
00375   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
00376   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
00377   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
00378   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
00379   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
00380   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
00381   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
00382   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
00383   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
00384   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
00385   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
00386   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
00387   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
00388   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
00389   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
00390   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
00391   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
00392   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
00393   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
00394   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
00395   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
00396   { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
00397   { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
00398   { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
00399   { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
00400   { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
00401   { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
00402   { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
00403   { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
00404   { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
00405   { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
00406   { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
00407   { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
00408   { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
00409   { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
00410   { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
00411   { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
00412   { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
00413   { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
00414   { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
00415   { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
00416   { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
00417   { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
00418   { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
00419   { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
00420   { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
00421   { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
00422   { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
00423   { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
00424   { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
00425   { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
00426   { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
00427   { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
00428 };
00429 
00430 CGEN_KEYWORD mep_cgen_opval_h_ccr =
00431 {
00432   & mep_cgen_opval_h_ccr_entries[0],
00433   64,
00434   0, 0, 0, 0, ""
00435 };
00436 
00437 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_fmax_entries[] =
00438 {
00439   { "$fr0", 0, {0, {{{0, 0}}}}, 0, 0 },
00440   { "$fr1", 1, {0, {{{0, 0}}}}, 0, 0 },
00441   { "$fr2", 2, {0, {{{0, 0}}}}, 0, 0 },
00442   { "$fr3", 3, {0, {{{0, 0}}}}, 0, 0 },
00443   { "$fr4", 4, {0, {{{0, 0}}}}, 0, 0 },
00444   { "$fr5", 5, {0, {{{0, 0}}}}, 0, 0 },
00445   { "$fr6", 6, {0, {{{0, 0}}}}, 0, 0 },
00446   { "$fr7", 7, {0, {{{0, 0}}}}, 0, 0 },
00447   { "$fr8", 8, {0, {{{0, 0}}}}, 0, 0 },
00448   { "$fr9", 9, {0, {{{0, 0}}}}, 0, 0 },
00449   { "$fr10", 10, {0, {{{0, 0}}}}, 0, 0 },
00450   { "$fr11", 11, {0, {{{0, 0}}}}, 0, 0 },
00451   { "$fr12", 12, {0, {{{0, 0}}}}, 0, 0 },
00452   { "$fr13", 13, {0, {{{0, 0}}}}, 0, 0 },
00453   { "$fr14", 14, {0, {{{0, 0}}}}, 0, 0 },
00454   { "$fr15", 15, {0, {{{0, 0}}}}, 0, 0 },
00455   { "$fr16", 16, {0, {{{0, 0}}}}, 0, 0 },
00456   { "$fr17", 17, {0, {{{0, 0}}}}, 0, 0 },
00457   { "$fr18", 18, {0, {{{0, 0}}}}, 0, 0 },
00458   { "$fr19", 19, {0, {{{0, 0}}}}, 0, 0 },
00459   { "$fr20", 20, {0, {{{0, 0}}}}, 0, 0 },
00460   { "$fr21", 21, {0, {{{0, 0}}}}, 0, 0 },
00461   { "$fr22", 22, {0, {{{0, 0}}}}, 0, 0 },
00462   { "$fr23", 23, {0, {{{0, 0}}}}, 0, 0 },
00463   { "$fr24", 24, {0, {{{0, 0}}}}, 0, 0 },
00464   { "$fr25", 25, {0, {{{0, 0}}}}, 0, 0 },
00465   { "$fr26", 26, {0, {{{0, 0}}}}, 0, 0 },
00466   { "$fr27", 27, {0, {{{0, 0}}}}, 0, 0 },
00467   { "$fr28", 28, {0, {{{0, 0}}}}, 0, 0 },
00468   { "$fr29", 29, {0, {{{0, 0}}}}, 0, 0 },
00469   { "$fr30", 30, {0, {{{0, 0}}}}, 0, 0 },
00470   { "$fr31", 31, {0, {{{0, 0}}}}, 0, 0 },
00471   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
00472   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
00473   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
00474   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
00475   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
00476   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
00477   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
00478   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
00479   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
00480   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
00481   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
00482   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
00483   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
00484   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
00485   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
00486   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
00487   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
00488   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
00489   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
00490   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
00491   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
00492   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
00493   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
00494   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
00495   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
00496   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
00497   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
00498   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
00499   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
00500   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
00501   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
00502   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
00503 };
00504 
00505 CGEN_KEYWORD mep_cgen_opval_h_cr_fmax =
00506 {
00507   & mep_cgen_opval_h_cr_fmax_entries[0],
00508   64,
00509   0, 0, 0, 0, ""
00510 };
00511 
00512 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_fmax_entries[] =
00513 {
00514   { "$cirr", 0, {0, {{{0, 0}}}}, 0, 0 },
00515   { "$fcr0", 0, {0, {{{0, 0}}}}, 0, 0 },
00516   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
00517   { "$cbcr", 1, {0, {{{0, 0}}}}, 0, 0 },
00518   { "$fcr1", 1, {0, {{{0, 0}}}}, 0, 0 },
00519   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
00520   { "$cerr", 15, {0, {{{0, 0}}}}, 0, 0 },
00521   { "$fcr15", 15, {0, {{{0, 0}}}}, 0, 0 },
00522   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 }
00523 };
00524 
00525 CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax =
00526 {
00527   & mep_cgen_opval_h_ccr_fmax_entries[0],
00528   9,
00529   0, 0, 0, 0, ""
00530 };
00531 
00532 
00533 /* The hardware table.  */
00534 
00535 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00536 #define A(a) (1 << CGEN_HW_##a)
00537 #else
00538 #define A(a) (1 << CGEN_HW_a)
00539 #endif
00540 
00541 const CGEN_HW_ENTRY mep_cgen_hw_table[] =
00542 {
00543   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00544   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00545   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00546   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00547   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00548   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00549   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00550   { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00551   { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00552   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00553   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } },
00554   { "h-cr-fmax", HW_H_CR_FMAX, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_fmax, { 0|A(IS_FLOAT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
00555   { "h-ccr-fmax", HW_H_CCR_FMAX, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_fmax, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
00556   { "h-fmax-compare-i-p", HW_H_FMAX_COMPARE_I_P, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } },
00557   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
00558 };
00559 
00560 #undef A
00561 
00562 
00563 /* The instruction field table.  */
00564 
00565 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00566 #define A(a) (1 << CGEN_IFLD_##a)
00567 #else
00568 #define A(a) (1 << CGEN_IFLD_a)
00569 #endif
00570 
00571 const CGEN_IFLD mep_cgen_ifld_table[] =
00572 {
00573   { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
00574   { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
00575   { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00576   { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00577   { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00578   { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00579   { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00580   { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00581   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00582   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00583   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00584   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00585   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00586   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00587   { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00588   { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00589   { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00590   { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00591   { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00592   { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00593   { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00594   { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00595   { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00596   { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00597   { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00598   { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00599   { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00600   { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00601   { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00602   { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00603   { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00604   { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00605   { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00606   { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00607   { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00608   { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00609   { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00610   { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00611   { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00612   { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00613   { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00614   { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00615   { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00616   { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00617   { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00618   { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00619   { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00620   { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00621   { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00622   { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } }  },
00623   { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00624   { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00625   { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00626   { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00627   { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00628   { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00629   { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00630   { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00631   { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00632   { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00633   { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00634   { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00635   { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00636   { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00637   { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00638   { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00639   { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00640   { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00641   { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00642   { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00643   { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00644   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00645   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00646   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00647   { MEP_F_8S24, "f-8s24", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00648   { MEP_F_8S24A2, "f-8s24a2", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00649   { MEP_F_8S24A4, "f-8s24a4", 0, 32, 24, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00650   { MEP_F_8S24A8, "f-8s24a8", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00651   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00652   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00653   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00654   { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00655   { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00656   { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00657   { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00658   { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00659   { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00660   { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00661   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00662   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00663   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } }  },
00664   { MEP_F_FMAX_0_4, "f-fmax-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00665   { MEP_F_FMAX_4_4, "f-fmax-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00666   { MEP_F_FMAX_8_4, "f-fmax-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00667   { MEP_F_FMAX_12_4, "f-fmax-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00668   { MEP_F_FMAX_16_4, "f-fmax-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00669   { MEP_F_FMAX_20_4, "f-fmax-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00670   { MEP_F_FMAX_24_4, "f-fmax-24-4", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00671   { MEP_F_FMAX_28_1, "f-fmax-28-1", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00672   { MEP_F_FMAX_29_1, "f-fmax-29-1", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00673   { MEP_F_FMAX_30_1, "f-fmax-30-1", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00674   { MEP_F_FMAX_31_1, "f-fmax-31-1", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00675   { MEP_F_FMAX_FRD, "f-fmax-frd", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00676   { MEP_F_FMAX_FRN, "f-fmax-frn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00677   { MEP_F_FMAX_FRM, "f-fmax-frm", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00678   { MEP_F_FMAX_RM, "f-fmax-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }  },
00679   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
00680 };
00681 
00682 #undef A
00683 
00684 
00685 
00686 /* multi ifield declarations */
00687 
00688 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
00689 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
00690 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
00691 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
00692 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
00693 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
00694 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
00695 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
00696 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
00697 const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRD_MULTI_IFIELD [];
00698 const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRN_MULTI_IFIELD [];
00699 const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRM_MULTI_IFIELD [];
00700 
00701 
00702 /* multi ifield definitions */
00703 
00704 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
00705 {
00706     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
00707     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
00708     { 0, { (const PTR) 0 } }
00709 };
00710 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
00711 {
00712     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
00713     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
00714     { 0, { (const PTR) 0 } }
00715 };
00716 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
00717 {
00718     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
00719     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
00720     { 0, { (const PTR) 0 } }
00721 };
00722 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
00723 {
00724     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
00725     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
00726     { 0, { (const PTR) 0 } }
00727 };
00728 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
00729 {
00730     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
00731     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
00732     { 0, { (const PTR) 0 } }
00733 };
00734 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
00735 {
00736     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
00737     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
00738     { 0, { (const PTR) 0 } }
00739 };
00740 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
00741 {
00742     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
00743     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
00744     { 0, { (const PTR) 0 } }
00745 };
00746 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
00747 {
00748     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
00749     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
00750     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
00751     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
00752     { 0, { (const PTR) 0 } }
00753 };
00754 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
00755 {
00756     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
00757     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
00758     { 0, { (const PTR) 0 } }
00759 };
00760 const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRD_MULTI_IFIELD [] =
00761 {
00762     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_28_1] } },
00763     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_4_4] } },
00764     { 0, { (const PTR) 0 } }
00765 };
00766 const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRN_MULTI_IFIELD [] =
00767 {
00768     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_29_1] } },
00769     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_20_4] } },
00770     { 0, { (const PTR) 0 } }
00771 };
00772 const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRM_MULTI_IFIELD [] =
00773 {
00774     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_30_1] } },
00775     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_24_4] } },
00776     { 0, { (const PTR) 0 } }
00777 };
00778 
00779 /* The operand table.  */
00780 
00781 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00782 #define A(a) (1 << CGEN_OPERAND_##a)
00783 #else
00784 #define A(a) (1 << CGEN_OPERAND_a)
00785 #endif
00786 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00787 #define OPERAND(op) MEP_OPERAND_##op
00788 #else
00789 #define OPERAND(op) MEP_OPERAND_op
00790 #endif
00791 
00792 const CGEN_OPERAND mep_cgen_operand_table[] =
00793 {
00794 /* pc: program counter */
00795   { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
00796     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } }, 
00797     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00798 /* r0: register 0 */
00799   { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
00800     { 0, { (const PTR) 0 } }, 
00801     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00802 /* rn: register Rn */
00803   { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
00804     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00805     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00806 /* rm: register Rm */
00807   { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
00808     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } }, 
00809     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00810 /* rl: register Rl */
00811   { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
00812     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } }, 
00813     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00814 /* rn3: register 0-7 */
00815   { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
00816     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00817     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00818 /* rma: register Rm holding pointer */
00819   { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
00820     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } }, 
00821     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } }  },
00822 /* rnc: register Rn holding char */
00823   { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
00824     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00825     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CHAR, 0 } }, { { 1, 0 } } } }  },
00826 /* rnuc: register Rn holding unsigned char */
00827   { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
00828     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00829     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_UCHAR, 0 } }, { { 1, 0 } } } }  },
00830 /* rns: register Rn holding short */
00831   { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
00832     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00833     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_SHORT, 0 } }, { { 1, 0 } } } }  },
00834 /* rnus: register Rn holding unsigned short */
00835   { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
00836     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00837     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_USHORT, 0 } }, { { 1, 0 } } } }  },
00838 /* rnl: register Rn holding long */
00839   { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
00840     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00841     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00842 /* rnul: register Rn holding unsigned  long */
00843   { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
00844     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
00845     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
00846 /* rn3c: register 0-7 holding unsigned char */
00847   { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
00848     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00849     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CHAR, 0 } }, { { 1, 0 } } } }  },
00850 /* rn3uc: register 0-7 holding byte */
00851   { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
00852     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00853     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_UCHAR, 0 } }, { { 1, 0 } } } }  },
00854 /* rn3s: register 0-7 holding unsigned short */
00855   { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
00856     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00857     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_SHORT, 0 } }, { { 1, 0 } } } }  },
00858 /* rn3us: register 0-7 holding short */
00859   { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
00860     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00861     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_USHORT, 0 } }, { { 1, 0 } } } }  },
00862 /* rn3l: register 0-7 holding unsigned long */
00863   { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
00864     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00865     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00866 /* rn3ul: register 0-7 holding long */
00867   { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
00868     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, 
00869     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
00870 /* lp: link pointer */
00871   { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
00872     { 0, { (const PTR) 0 } }, 
00873     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00874 /* sar: shift amount register */
00875   { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
00876     { 0, { (const PTR) 0 } }, 
00877     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00878 /* hi: high result */
00879   { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
00880     { 0, { (const PTR) 0 } }, 
00881     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00882 /* lo: low result */
00883   { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
00884     { 0, { (const PTR) 0 } }, 
00885     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00886 /* mb0: modulo begin register 0 */
00887   { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
00888     { 0, { (const PTR) 0 } }, 
00889     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00890 /* me0: modulo end register 0 */
00891   { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
00892     { 0, { (const PTR) 0 } }, 
00893     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00894 /* mb1: modulo begin register 1 */
00895   { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
00896     { 0, { (const PTR) 0 } }, 
00897     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00898 /* me1: modulo end register 1 */
00899   { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
00900     { 0, { (const PTR) 0 } }, 
00901     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00902 /* psw: program status word */
00903   { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
00904     { 0, { (const PTR) 0 } }, 
00905     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00906 /* epc: exception prog counter */
00907   { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
00908     { 0, { (const PTR) 0 } }, 
00909     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00910 /* exc: exception cause */
00911   { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
00912     { 0, { (const PTR) 0 } }, 
00913     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00914 /* npc: nmi program counter */
00915   { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
00916     { 0, { (const PTR) 0 } }, 
00917     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00918 /* dbg: debug register */
00919   { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
00920     { 0, { (const PTR) 0 } }, 
00921     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00922 /* depc: debug exception pc */
00923   { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
00924     { 0, { (const PTR) 0 } }, 
00925     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00926 /* opt: option register */
00927   { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
00928     { 0, { (const PTR) 0 } }, 
00929     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00930 /* r1: register 1 */
00931   { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
00932     { 0, { (const PTR) 0 } }, 
00933     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00934 /* tp: tiny data area pointer */
00935   { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
00936     { 0, { (const PTR) 0 } }, 
00937     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00938 /* sp: stack pointer */
00939   { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
00940     { 0, { (const PTR) 0 } }, 
00941     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00942 /* tpr: comment */
00943   { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
00944     { 0, { (const PTR) 0 } }, 
00945     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00946 /* spr: comment */
00947   { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
00948     { 0, { (const PTR) 0 } }, 
00949     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00950 /* csrn: control/special register */
00951   { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
00952     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } }, 
00953     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
00954 /* csrn-idx: control/special reg idx */
00955   { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
00956     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } }, 
00957     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00958 /* crn64: copro Rn (64-bit) */
00959   { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
00960     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } }, 
00961     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
00962 /* crn: copro Rn (32-bit) */
00963   { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
00964     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } }, 
00965     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
00966 /* crnx64: copro Rn (0-31, 64-bit) */
00967   { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
00968     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } }, 
00969     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
00970 /* crnx: copro Rn (0-31, 32-bit) */
00971   { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
00972     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } }, 
00973     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
00974 /* ccrn: copro control reg CCRn */
00975   { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
00976     { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } }, 
00977     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
00978 /* cccc: copro flags */
00979   { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
00980     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } }, 
00981     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
00982 /* pcrel8a2: comment */
00983   { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
00984     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } }, 
00985     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
00986 /* pcrel12a2: comment */
00987   { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
00988     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } }, 
00989     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
00990 /* pcrel17a2: comment */
00991   { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
00992     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } }, 
00993     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
00994 /* pcrel24a2: comment */
00995   { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
00996     { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } }, 
00997     { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
00998 /* pcabs24a2: comment */
00999   { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
01000     { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } }, 
01001     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
01002 /* sdisp16: comment */
01003   { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
01004     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } }, 
01005     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01006 /* simm16: comment */
01007   { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
01008     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } }, 
01009     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01010 /* uimm16: comment */
01011   { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
01012     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } }, 
01013     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01014 /* code16: uci/dsp code (16 bits) */
01015   { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
01016     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } }, 
01017     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01018 /* udisp2: SSARB addend (2 bits) */
01019   { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
01020     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } }, 
01021     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01022 /* uimm2: interrupt (2 bits) */
01023   { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
01024     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } }, 
01025     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01026 /* simm6: add const (6 bits) */
01027   { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
01028     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } }, 
01029     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01030 /* simm8: mov const (8 bits) */
01031   { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
01032     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } }, 
01033     { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01034 /* addr24a4: comment */
01035   { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
01036     { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } }, 
01037     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
01038 /* code24: coprocessor code */
01039   { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
01040     { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } }, 
01041     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01042 /* callnum: system call number */
01043   { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
01044     { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } }, 
01045     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01046 /* uimm3: bit immediate (3 bits) */
01047   { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
01048     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } }, 
01049     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01050 /* uimm4: bCC const (4 bits) */
01051   { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
01052     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } }, 
01053     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01054 /* uimm5: bit/shift val (5 bits) */
01055   { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
01056     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } }, 
01057     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01058 /* udisp7: comment */
01059   { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
01060     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } }, 
01061     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01062 /* udisp7a2: comment */
01063   { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
01064     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } }, 
01065     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
01066 /* udisp7a4: comment */
01067   { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
01068     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } }, 
01069     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
01070 /* uimm7a4: comment */
01071   { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
01072     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } }, 
01073     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
01074 /* uimm24: immediate (24 bits) */
01075   { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
01076     { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } }, 
01077     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01078 /* cimm4: cache immed'te (4 bits) */
01079   { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
01080     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, 
01081     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01082 /* cimm5: clip immediate (5 bits) */
01083   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
01084     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } }, 
01085     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01086 /* cdisp8: copro addend (8 bits) */
01087   { "cdisp8", MEP_OPERAND_CDISP8, HW_H_SINT, 24, 8,
01088     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24] } }, 
01089     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01090 /* cdisp8a2: comment */
01091   { "cdisp8a2", MEP_OPERAND_CDISP8A2, HW_H_SINT, 24, 7,
01092     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A2] } }, 
01093     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
01094 /* cdisp8a4: comment */
01095   { "cdisp8a4", MEP_OPERAND_CDISP8A4, HW_H_SINT, 24, 6,
01096     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A4] } }, 
01097     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
01098 /* cdisp8a8: comment */
01099   { "cdisp8a8", MEP_OPERAND_CDISP8A8, HW_H_SINT, 24, 5,
01100     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A8] } }, 
01101     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 8, 0 } } } }  },
01102 /* zero: Zero operand */
01103   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
01104     { 0, { (const PTR) 0 } }, 
01105     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01106 /* cp_flag: branch condition register */
01107   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
01108     { 0, { (const PTR) 0 } }, 
01109     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01110 /* fmax-FRd: FRd */
01111   { "fmax-FRd", MEP_OPERAND_FMAX_FRD, HW_H_CR, 4, 5,
01112     { 2, { (const PTR) &MEP_F_FMAX_FRD_MULTI_IFIELD[0] } }, 
01113     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } }  },
01114 /* fmax-FRn: FRn */
01115   { "fmax-FRn", MEP_OPERAND_FMAX_FRN, HW_H_CR, 20, 5,
01116     { 2, { (const PTR) &MEP_F_FMAX_FRN_MULTI_IFIELD[0] } }, 
01117     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } }  },
01118 /* fmax-FRm: FRm */
01119   { "fmax-FRm", MEP_OPERAND_FMAX_FRM, HW_H_CR, 24, 5,
01120     { 2, { (const PTR) &MEP_F_FMAX_FRM_MULTI_IFIELD[0] } }, 
01121     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } }  },
01122 /* fmax-FRd-int: FRd as an integer */
01123   { "fmax-FRd-int", MEP_OPERAND_FMAX_FRD_INT, HW_H_CR, 4, 5,
01124     { 2, { (const PTR) &MEP_F_FMAX_FRD_MULTI_IFIELD[0] } }, 
01125     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_INT, 0 } }, { { 1, 0 } } } }  },
01126 /* fmax-FRn-int: FRn as an integer */
01127   { "fmax-FRn-int", MEP_OPERAND_FMAX_FRN_INT, HW_H_CR, 20, 5,
01128     { 2, { (const PTR) &MEP_F_FMAX_FRN_MULTI_IFIELD[0] } }, 
01129     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_INT, 0 } }, { { 1, 0 } } } }  },
01130 /* fmax-CCRn: CCRn */
01131   { "fmax-CCRn", MEP_OPERAND_FMAX_CCRN, HW_H_CCR, 4, 4,
01132     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_4_4] } }, 
01133     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
01134 /* fmax-CIRR: CIRR */
01135   { "fmax-CIRR", MEP_OPERAND_FMAX_CIRR, HW_H_CCR, 0, 0,
01136     { 0, { (const PTR) 0 } }, 
01137     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01138 /* fmax-CBCR: CBCR */
01139   { "fmax-CBCR", MEP_OPERAND_FMAX_CBCR, HW_H_CCR, 0, 0,
01140     { 0, { (const PTR) 0 } }, 
01141     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01142 /* fmax-CERR: CERR */
01143   { "fmax-CERR", MEP_OPERAND_FMAX_CERR, HW_H_CCR, 0, 0,
01144     { 0, { (const PTR) 0 } }, 
01145     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01146 /* fmax-Rm: Rm */
01147   { "fmax-Rm", MEP_OPERAND_FMAX_RM, HW_H_GPR, 8, 4,
01148     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_RM] } }, 
01149     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01150 /* fmax-Compare-i-p: flag */
01151   { "fmax-Compare-i-p", MEP_OPERAND_FMAX_COMPARE_I_P, HW_H_FMAX_COMPARE_I_P, 0, 0,
01152     { 0, { (const PTR) 0 } }, 
01153     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
01154 /* sentinel */
01155   { 0, 0, 0, 0, 0,
01156     { 0, { (const PTR) 0 } },
01157     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
01158 };
01159 
01160 #undef A
01161 
01162 
01163 /* The instruction table.  */
01164 
01165 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
01166 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01167 #define A(a) (1 << CGEN_INSN_##a)
01168 #else
01169 #define A(a) (1 << CGEN_INSN_a)
01170 #endif
01171 
01172 static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
01173 {
01174   /* Special null first entry.
01175      A `num' value of zero is thus invalid.
01176      Also, the special `invalid' insn resides here.  */
01177   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } },
01178 /* sb $rnc,($rma) */
01179   {
01180     MEP_INSN_SB, "sb", "sb", 16,
01181     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01182   },
01183 /* sh $rns,($rma) */
01184   {
01185     MEP_INSN_SH, "sh", "sh", 16,
01186     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01187   },
01188 /* sw $rnl,($rma) */
01189   {
01190     MEP_INSN_SW, "sw", "sw", 16,
01191     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01192   },
01193 /* lb $rnc,($rma) */
01194   {
01195     MEP_INSN_LB, "lb", "lb", 16,
01196     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01197   },
01198 /* lh $rns,($rma) */
01199   {
01200     MEP_INSN_LH, "lh", "lh", 16,
01201     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01202   },
01203 /* lw $rnl,($rma) */
01204   {
01205     MEP_INSN_LW, "lw", "lw", 16,
01206     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01207   },
01208 /* lbu $rnuc,($rma) */
01209   {
01210     MEP_INSN_LBU, "lbu", "lbu", 16,
01211     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01212   },
01213 /* lhu $rnus,($rma) */
01214   {
01215     MEP_INSN_LHU, "lhu", "lhu", 16,
01216     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01217   },
01218 /* sw $rnl,$udisp7a4($spr) */
01219   {
01220     MEP_INSN_SW_SP, "sw-sp", "sw", 16,
01221     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01222   },
01223 /* lw $rnl,$udisp7a4($spr) */
01224   {
01225     MEP_INSN_LW_SP, "lw-sp", "lw", 16,
01226     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01227   },
01228 /* sb $rn3c,$udisp7($tpr) */
01229   {
01230     MEP_INSN_SB_TP, "sb-tp", "sb", 16,
01231     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01232   },
01233 /* sh $rn3s,$udisp7a2($tpr) */
01234   {
01235     MEP_INSN_SH_TP, "sh-tp", "sh", 16,
01236     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01237   },
01238 /* sw $rn3l,$udisp7a4($tpr) */
01239   {
01240     MEP_INSN_SW_TP, "sw-tp", "sw", 16,
01241     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01242   },
01243 /* lb $rn3c,$udisp7($tpr) */
01244   {
01245     MEP_INSN_LB_TP, "lb-tp", "lb", 16,
01246     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01247   },
01248 /* lh $rn3s,$udisp7a2($tpr) */
01249   {
01250     MEP_INSN_LH_TP, "lh-tp", "lh", 16,
01251     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01252   },
01253 /* lw $rn3l,$udisp7a4($tpr) */
01254   {
01255     MEP_INSN_LW_TP, "lw-tp", "lw", 16,
01256     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01257   },
01258 /* lbu $rn3uc,$udisp7($tpr) */
01259   {
01260     MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
01261     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01262   },
01263 /* lhu $rn3us,$udisp7a2($tpr) */
01264   {
01265     MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
01266     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01267   },
01268 /* sb $rnc,$sdisp16($rma) */
01269   {
01270     MEP_INSN_SB16, "sb16", "sb", 32,
01271     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01272   },
01273 /* sh $rns,$sdisp16($rma) */
01274   {
01275     MEP_INSN_SH16, "sh16", "sh", 32,
01276     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01277   },
01278 /* sw $rnl,$sdisp16($rma) */
01279   {
01280     MEP_INSN_SW16, "sw16", "sw", 32,
01281     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01282   },
01283 /* lb $rnc,$sdisp16($rma) */
01284   {
01285     MEP_INSN_LB16, "lb16", "lb", 32,
01286     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01287   },
01288 /* lh $rns,$sdisp16($rma) */
01289   {
01290     MEP_INSN_LH16, "lh16", "lh", 32,
01291     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01292   },
01293 /* lw $rnl,$sdisp16($rma) */
01294   {
01295     MEP_INSN_LW16, "lw16", "lw", 32,
01296     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01297   },
01298 /* lbu $rnuc,$sdisp16($rma) */
01299   {
01300     MEP_INSN_LBU16, "lbu16", "lbu", 32,
01301     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01302   },
01303 /* lhu $rnus,$sdisp16($rma) */
01304   {
01305     MEP_INSN_LHU16, "lhu16", "lhu", 32,
01306     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01307   },
01308 /* sw $rnl,($addr24a4) */
01309   {
01310     MEP_INSN_SW24, "sw24", "sw", 32,
01311     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01312   },
01313 /* lw $rnl,($addr24a4) */
01314   {
01315     MEP_INSN_LW24, "lw24", "lw", 32,
01316     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01317   },
01318 /* extb $rn */
01319   {
01320     MEP_INSN_EXTB, "extb", "extb", 16,
01321     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01322   },
01323 /* exth $rn */
01324   {
01325     MEP_INSN_EXTH, "exth", "exth", 16,
01326     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01327   },
01328 /* extub $rn */
01329   {
01330     MEP_INSN_EXTUB, "extub", "extub", 16,
01331     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01332   },
01333 /* extuh $rn */
01334   {
01335     MEP_INSN_EXTUH, "extuh", "extuh", 16,
01336     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01337   },
01338 /* ssarb $udisp2($rm) */
01339   {
01340     MEP_INSN_SSARB, "ssarb", "ssarb", 16,
01341     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01342   },
01343 /* mov $rn,$rm */
01344   {
01345     MEP_INSN_MOV, "mov", "mov", 16,
01346     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01347   },
01348 /* mov $rn,$simm8 */
01349   {
01350     MEP_INSN_MOVI8, "movi8", "mov", 16,
01351     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01352   },
01353 /* mov $rn,$simm16 */
01354   {
01355     MEP_INSN_MOVI16, "movi16", "mov", 32,
01356     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01357   },
01358 /* movu $rn3,$uimm24 */
01359   {
01360     MEP_INSN_MOVU24, "movu24", "movu", 32,
01361     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01362   },
01363 /* movu $rn,$uimm16 */
01364   {
01365     MEP_INSN_MOVU16, "movu16", "movu", 32,
01366     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01367   },
01368 /* movh $rn,$uimm16 */
01369   {
01370     MEP_INSN_MOVH, "movh", "movh", 32,
01371     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01372   },
01373 /* add3 $rl,$rn,$rm */
01374   {
01375     MEP_INSN_ADD3, "add3", "add3", 16,
01376     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01377   },
01378 /* add $rn,$simm6 */
01379   {
01380     MEP_INSN_ADD, "add", "add", 16,
01381     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01382   },
01383 /* add3 $rn,$spr,$uimm7a4 */
01384   {
01385     MEP_INSN_ADD3I, "add3i", "add3", 16,
01386     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01387   },
01388 /* advck3 \$0,$rn,$rm */
01389   {
01390     MEP_INSN_ADVCK3, "advck3", "advck3", 16,
01391     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01392   },
01393 /* sub $rn,$rm */
01394   {
01395     MEP_INSN_SUB, "sub", "sub", 16,
01396     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01397   },
01398 /* sbvck3 \$0,$rn,$rm */
01399   {
01400     MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
01401     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01402   },
01403 /* neg $rn,$rm */
01404   {
01405     MEP_INSN_NEG, "neg", "neg", 16,
01406     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01407   },
01408 /* slt3 \$0,$rn,$rm */
01409   {
01410     MEP_INSN_SLT3, "slt3", "slt3", 16,
01411     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01412   },
01413 /* sltu3 \$0,$rn,$rm */
01414   {
01415     MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
01416     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01417   },
01418 /* slt3 \$0,$rn,$uimm5 */
01419   {
01420     MEP_INSN_SLT3I, "slt3i", "slt3", 16,
01421     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01422   },
01423 /* sltu3 \$0,$rn,$uimm5 */
01424   {
01425     MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
01426     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01427   },
01428 /* sl1ad3 \$0,$rn,$rm */
01429   {
01430     MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
01431     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01432   },
01433 /* sl2ad3 \$0,$rn,$rm */
01434   {
01435     MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
01436     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01437   },
01438 /* add3 $rn,$rm,$simm16 */
01439   {
01440     MEP_INSN_ADD3X, "add3x", "add3", 32,
01441     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01442   },
01443 /* slt3 $rn,$rm,$simm16 */
01444   {
01445     MEP_INSN_SLT3X, "slt3x", "slt3", 32,
01446     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01447   },
01448 /* sltu3 $rn,$rm,$uimm16 */
01449   {
01450     MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
01451     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01452   },
01453 /* or $rn,$rm */
01454   {
01455     MEP_INSN_OR, "or", "or", 16,
01456     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01457   },
01458 /* and $rn,$rm */
01459   {
01460     MEP_INSN_AND, "and", "and", 16,
01461     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01462   },
01463 /* xor $rn,$rm */
01464   {
01465     MEP_INSN_XOR, "xor", "xor", 16,
01466     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01467   },
01468 /* nor $rn,$rm */
01469   {
01470     MEP_INSN_NOR, "nor", "nor", 16,
01471     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01472   },
01473 /* or3 $rn,$rm,$uimm16 */
01474   {
01475     MEP_INSN_OR3, "or3", "or3", 32,
01476     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01477   },
01478 /* and3 $rn,$rm,$uimm16 */
01479   {
01480     MEP_INSN_AND3, "and3", "and3", 32,
01481     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01482   },
01483 /* xor3 $rn,$rm,$uimm16 */
01484   {
01485     MEP_INSN_XOR3, "xor3", "xor3", 32,
01486     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01487   },
01488 /* sra $rn,$rm */
01489   {
01490     MEP_INSN_SRA, "sra", "sra", 16,
01491     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01492   },
01493 /* srl $rn,$rm */
01494   {
01495     MEP_INSN_SRL, "srl", "srl", 16,
01496     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01497   },
01498 /* sll $rn,$rm */
01499   {
01500     MEP_INSN_SLL, "sll", "sll", 16,
01501     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01502   },
01503 /* sra $rn,$uimm5 */
01504   {
01505     MEP_INSN_SRAI, "srai", "sra", 16,
01506     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01507   },
01508 /* srl $rn,$uimm5 */
01509   {
01510     MEP_INSN_SRLI, "srli", "srl", 16,
01511     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01512   },
01513 /* sll $rn,$uimm5 */
01514   {
01515     MEP_INSN_SLLI, "slli", "sll", 16,
01516     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01517   },
01518 /* sll3 \$0,$rn,$uimm5 */
01519   {
01520     MEP_INSN_SLL3, "sll3", "sll3", 16,
01521     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01522   },
01523 /* fsft $rn,$rm */
01524   {
01525     MEP_INSN_FSFT, "fsft", "fsft", 16,
01526     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01527   },
01528 /* bra $pcrel12a2 */
01529   {
01530     MEP_INSN_BRA, "bra", "bra", 16,
01531     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01532   },
01533 /* beqz $rn,$pcrel8a2 */
01534   {
01535     MEP_INSN_BEQZ, "beqz", "beqz", 16,
01536     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01537   },
01538 /* bnez $rn,$pcrel8a2 */
01539   {
01540     MEP_INSN_BNEZ, "bnez", "bnez", 16,
01541     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01542   },
01543 /* beqi $rn,$uimm4,$pcrel17a2 */
01544   {
01545     MEP_INSN_BEQI, "beqi", "beqi", 32,
01546     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01547   },
01548 /* bnei $rn,$uimm4,$pcrel17a2 */
01549   {
01550     MEP_INSN_BNEI, "bnei", "bnei", 32,
01551     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01552   },
01553 /* blti $rn,$uimm4,$pcrel17a2 */
01554   {
01555     MEP_INSN_BLTI, "blti", "blti", 32,
01556     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01557   },
01558 /* bgei $rn,$uimm4,$pcrel17a2 */
01559   {
01560     MEP_INSN_BGEI, "bgei", "bgei", 32,
01561     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01562   },
01563 /* beq $rn,$rm,$pcrel17a2 */
01564   {
01565     MEP_INSN_BEQ, "beq", "beq", 32,
01566     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01567   },
01568 /* bne $rn,$rm,$pcrel17a2 */
01569   {
01570     MEP_INSN_BNE, "bne", "bne", 32,
01571     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01572   },
01573 /* bsr $pcrel12a2 */
01574   {
01575     MEP_INSN_BSR12, "bsr12", "bsr", 16,
01576     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01577   },
01578 /* bsr $pcrel24a2 */
01579   {
01580     MEP_INSN_BSR24, "bsr24", "bsr", 32,
01581     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01582   },
01583 /* jmp $rm */
01584   {
01585     MEP_INSN_JMP, "jmp", "jmp", 16,
01586     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01587   },
01588 /* jmp $pcabs24a2 */
01589   {
01590     MEP_INSN_JMP24, "jmp24", "jmp", 32,
01591     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01592   },
01593 /* jsr $rm */
01594   {
01595     MEP_INSN_JSR, "jsr", "jsr", 16,
01596     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01597   },
01598 /* ret */
01599   {
01600     MEP_INSN_RET, "ret", "ret", 16,
01601     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01602   },
01603 /* repeat $rn,$pcrel17a2 */
01604   {
01605     MEP_INSN_REPEAT, "repeat", "repeat", 32,
01606     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01607   },
01608 /* erepeat $pcrel17a2 */
01609   {
01610     MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
01611     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01612   },
01613 /* stc $rn,\$lp */
01614   {
01615     MEP_INSN_STC_LP, "stc_lp", "stc", 16,
01616     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01617   },
01618 /* stc $rn,\$hi */
01619   {
01620     MEP_INSN_STC_HI, "stc_hi", "stc", 16,
01621     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01622   },
01623 /* stc $rn,\$lo */
01624   {
01625     MEP_INSN_STC_LO, "stc_lo", "stc", 16,
01626     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01627   },
01628 /* stc $rn,$csrn */
01629   {
01630     MEP_INSN_STC, "stc", "stc", 16,
01631     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01632   },
01633 /* ldc $rn,\$lp */
01634   {
01635     MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
01636     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01637   },
01638 /* ldc $rn,\$hi */
01639   {
01640     MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
01641     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01642   },
01643 /* ldc $rn,\$lo */
01644   {
01645     MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
01646     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01647   },
01648 /* ldc $rn,$csrn */
01649   {
01650     MEP_INSN_LDC, "ldc", "ldc", 16,
01651     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } }
01652   },
01653 /* di */
01654   {
01655     MEP_INSN_DI, "di", "di", 16,
01656     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01657   },
01658 /* ei */
01659   {
01660     MEP_INSN_EI, "ei", "ei", 16,
01661     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01662   },
01663 /* reti */
01664   {
01665     MEP_INSN_RETI, "reti", "reti", 16,
01666     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01667   },
01668 /* halt */
01669   {
01670     MEP_INSN_HALT, "halt", "halt", 16,
01671     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01672   },
01673 /* sleep */
01674   {
01675     MEP_INSN_SLEEP, "sleep", "sleep", 16,
01676     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01677   },
01678 /* swi $uimm2 */
01679   {
01680     MEP_INSN_SWI, "swi", "swi", 16,
01681     { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01682   },
01683 /* break */
01684   {
01685     MEP_INSN_BREAK, "break", "break", 16,
01686     { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01687   },
01688 /* syncm */
01689   {
01690     MEP_INSN_SYNCM, "syncm", "syncm", 16,
01691     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01692   },
01693 /* stcb $rn,$uimm16 */
01694   {
01695     MEP_INSN_STCB, "stcb", "stcb", 32,
01696     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01697   },
01698 /* ldcb $rn,$uimm16 */
01699   {
01700     MEP_INSN_LDCB, "ldcb", "ldcb", 32,
01701     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
01702   },
01703 /* bsetm ($rma),$uimm3 */
01704   {
01705     MEP_INSN_BSETM, "bsetm", "bsetm", 16,
01706     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01707   },
01708 /* bclrm ($rma),$uimm3 */
01709   {
01710     MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
01711     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01712   },
01713 /* bnotm ($rma),$uimm3 */
01714   {
01715     MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
01716     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01717   },
01718 /* btstm \$0,($rma),$uimm3 */
01719   {
01720     MEP_INSN_BTSTM, "btstm", "btstm", 16,
01721     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01722   },
01723 /* tas $rn,($rma) */
01724   {
01725     MEP_INSN_TAS, "tas", "tas", 16,
01726     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01727   },
01728 /* cache $cimm4,($rma) */
01729   {
01730     MEP_INSN_CACHE, "cache", "cache", 16,
01731     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01732   },
01733 /* mul $rn,$rm */
01734   {
01735     MEP_INSN_MUL, "mul", "mul", 16,
01736     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01737   },
01738 /* mulu $rn,$rm */
01739   {
01740     MEP_INSN_MULU, "mulu", "mulu", 16,
01741     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01742   },
01743 /* mulr $rn,$rm */
01744   {
01745     MEP_INSN_MULR, "mulr", "mulr", 16,
01746     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
01747   },
01748 /* mulru $rn,$rm */
01749   {
01750     MEP_INSN_MULRU, "mulru", "mulru", 16,
01751     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
01752   },
01753 /* madd $rn,$rm */
01754   {
01755     MEP_INSN_MADD, "madd", "madd", 32,
01756     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01757   },
01758 /* maddu $rn,$rm */
01759   {
01760     MEP_INSN_MADDU, "maddu", "maddu", 32,
01761     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01762   },
01763 /* maddr $rn,$rm */
01764   {
01765     MEP_INSN_MADDR, "maddr", "maddr", 32,
01766     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
01767   },
01768 /* maddru $rn,$rm */
01769   {
01770     MEP_INSN_MADDRU, "maddru", "maddru", 32,
01771     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } }
01772   },
01773 /* div $rn,$rm */
01774   {
01775     MEP_INSN_DIV, "div", "div", 16,
01776     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
01777   },
01778 /* divu $rn,$rm */
01779   {
01780     MEP_INSN_DIVU, "divu", "divu", 16,
01781     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } }
01782   },
01783 /* dret */
01784   {
01785     MEP_INSN_DRET, "dret", "dret", 16,
01786     { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01787   },
01788 /* dbreak */
01789   {
01790     MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
01791     { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01792   },
01793 /* ldz $rn,$rm */
01794   {
01795     MEP_INSN_LDZ, "ldz", "ldz", 32,
01796     { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01797   },
01798 /* abs $rn,$rm */
01799   {
01800     MEP_INSN_ABS, "abs", "abs", 32,
01801     { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01802   },
01803 /* ave $rn,$rm */
01804   {
01805     MEP_INSN_AVE, "ave", "ave", 32,
01806     { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01807   },
01808 /* min $rn,$rm */
01809   {
01810     MEP_INSN_MIN, "min", "min", 32,
01811     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01812   },
01813 /* max $rn,$rm */
01814   {
01815     MEP_INSN_MAX, "max", "max", 32,
01816     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01817   },
01818 /* minu $rn,$rm */
01819   {
01820     MEP_INSN_MINU, "minu", "minu", 32,
01821     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01822   },
01823 /* maxu $rn,$rm */
01824   {
01825     MEP_INSN_MAXU, "maxu", "maxu", 32,
01826     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01827   },
01828 /* clip $rn,$cimm5 */
01829   {
01830     MEP_INSN_CLIP, "clip", "clip", 32,
01831     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01832   },
01833 /* clipu $rn,$cimm5 */
01834   {
01835     MEP_INSN_CLIPU, "clipu", "clipu", 32,
01836     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01837   },
01838 /* sadd $rn,$rm */
01839   {
01840     MEP_INSN_SADD, "sadd", "sadd", 32,
01841     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01842   },
01843 /* ssub $rn,$rm */
01844   {
01845     MEP_INSN_SSUB, "ssub", "ssub", 32,
01846     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01847   },
01848 /* saddu $rn,$rm */
01849   {
01850     MEP_INSN_SADDU, "saddu", "saddu", 32,
01851     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01852   },
01853 /* ssubu $rn,$rm */
01854   {
01855     MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
01856     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01857   },
01858 /* swcp $crn,($rma) */
01859   {
01860     MEP_INSN_SWCP, "swcp", "swcp", 16,
01861     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01862   },
01863 /* lwcp $crn,($rma) */
01864   {
01865     MEP_INSN_LWCP, "lwcp", "lwcp", 16,
01866     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01867   },
01868 /* smcp $crn64,($rma) */
01869   {
01870     MEP_INSN_SMCP, "smcp", "smcp", 16,
01871     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01872   },
01873 /* lmcp $crn64,($rma) */
01874   {
01875     MEP_INSN_LMCP, "lmcp", "lmcp", 16,
01876     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01877   },
01878 /* swcpi $crn,($rma+) */
01879   {
01880     MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
01881     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01882   },
01883 /* lwcpi $crn,($rma+) */
01884   {
01885     MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
01886     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01887   },
01888 /* smcpi $crn64,($rma+) */
01889   {
01890     MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
01891     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01892   },
01893 /* lmcpi $crn64,($rma+) */
01894   {
01895     MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
01896     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01897   },
01898 /* swcp $crn,$sdisp16($rma) */
01899   {
01900     MEP_INSN_SWCP16, "swcp16", "swcp", 32,
01901     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01902   },
01903 /* lwcp $crn,$sdisp16($rma) */
01904   {
01905     MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
01906     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01907   },
01908 /* smcp $crn64,$sdisp16($rma) */
01909   {
01910     MEP_INSN_SMCP16, "smcp16", "smcp", 32,
01911     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01912   },
01913 /* lmcp $crn64,$sdisp16($rma) */
01914   {
01915     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
01916     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01917   },
01918 /* sbcpa $crn,($rma+),$cdisp8 */
01919   {
01920     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
01921     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01922   },
01923 /* lbcpa $crn,($rma+),$cdisp8 */
01924   {
01925     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
01926     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01927   },
01928 /* shcpa $crn,($rma+),$cdisp8a2 */
01929   {
01930     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
01931     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01932   },
01933 /* lhcpa $crn,($rma+),$cdisp8a2 */
01934   {
01935     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
01936     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01937   },
01938 /* swcpa $crn,($rma+),$cdisp8a4 */
01939   {
01940     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
01941     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01942   },
01943 /* lwcpa $crn,($rma+),$cdisp8a4 */
01944   {
01945     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
01946     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01947   },
01948 /* smcpa $crn64,($rma+),$cdisp8a8 */
01949   {
01950     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
01951     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01952   },
01953 /* lmcpa $crn64,($rma+),$cdisp8a8 */
01954   {
01955     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
01956     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01957   },
01958 /* sbcpm0 $crn,($rma+),$cdisp8 */
01959   {
01960     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
01961     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01962   },
01963 /* lbcpm0 $crn,($rma+),$cdisp8 */
01964   {
01965     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
01966     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01967   },
01968 /* shcpm0 $crn,($rma+),$cdisp8a2 */
01969   {
01970     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
01971     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01972   },
01973 /* lhcpm0 $crn,($rma+),$cdisp8a2 */
01974   {
01975     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
01976     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01977   },
01978 /* swcpm0 $crn,($rma+),$cdisp8a4 */
01979   {
01980     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
01981     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01982   },
01983 /* lwcpm0 $crn,($rma+),$cdisp8a4 */
01984   {
01985     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
01986     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01987   },
01988 /* smcpm0 $crn64,($rma+),$cdisp8a8 */
01989   {
01990     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
01991     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01992   },
01993 /* lmcpm0 $crn64,($rma+),$cdisp8a8 */
01994   {
01995     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
01996     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
01997   },
01998 /* sbcpm1 $crn,($rma+),$cdisp8 */
01999   {
02000     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
02001     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02002   },
02003 /* lbcpm1 $crn,($rma+),$cdisp8 */
02004   {
02005     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
02006     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02007   },
02008 /* shcpm1 $crn,($rma+),$cdisp8a2 */
02009   {
02010     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
02011     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02012   },
02013 /* lhcpm1 $crn,($rma+),$cdisp8a2 */
02014   {
02015     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
02016     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02017   },
02018 /* swcpm1 $crn,($rma+),$cdisp8a4 */
02019   {
02020     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
02021     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02022   },
02023 /* lwcpm1 $crn,($rma+),$cdisp8a4 */
02024   {
02025     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
02026     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02027   },
02028 /* smcpm1 $crn64,($rma+),$cdisp8a8 */
02029   {
02030     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
02031     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02032   },
02033 /* lmcpm1 $crn64,($rma+),$cdisp8a8 */
02034   {
02035     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
02036     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02037   },
02038 /* bcpeq $cccc,$pcrel17a2 */
02039   {
02040     MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
02041     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02042   },
02043 /* bcpne $cccc,$pcrel17a2 */
02044   {
02045     MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
02046     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02047   },
02048 /* bcpat $cccc,$pcrel17a2 */
02049   {
02050     MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
02051     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02052   },
02053 /* bcpaf $cccc,$pcrel17a2 */
02054   {
02055     MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
02056     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02057   },
02058 /* synccp */
02059   {
02060     MEP_INSN_SYNCCP, "synccp", "synccp", 16,
02061     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02062   },
02063 /* jsrv $rm */
02064   {
02065     MEP_INSN_JSRV, "jsrv", "jsrv", 16,
02066     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02067   },
02068 /* bsrv $pcrel24a2 */
02069   {
02070     MEP_INSN_BSRV, "bsrv", "bsrv", 32,
02071     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02072   },
02073 /* --unused-- */
02074   {
02075     MEP_INSN_SIM_SYSCALL, "sim-syscall", "--unused--", 16,
02076     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02077   },
02078 /* --reserved-- */
02079   {
02080     MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
02081     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02082   },
02083 /* --reserved-- */
02084   {
02085     MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
02086     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02087   },
02088 /* --reserved-- */
02089   {
02090     MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
02091     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02092   },
02093 /* --reserved-- */
02094   {
02095     MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
02096     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02097   },
02098 /* --reserved-- */
02099   {
02100     MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
02101     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02102   },
02103 /* --reserved-- */
02104   {
02105     MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
02106     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02107   },
02108 /* --reserved-- */
02109   {
02110     MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
02111     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02112   },
02113 /* --reserved-- */
02114   {
02115     MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
02116     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02117   },
02118 /* --reserved-- */
02119   {
02120     MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
02121     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02122   },
02123 /* --reserved-- */
02124   {
02125     MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
02126     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02127   },
02128 /* --reserved-- */
02129   {
02130     MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
02131     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02132   },
02133 /* --reserved-- */
02134   {
02135     MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
02136     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02137   },
02138 /* --reserved-- */
02139   {
02140     MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
02141     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02142   },
02143 /* --reserved-- */
02144   {
02145     MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
02146     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02147   },
02148 /* --reserved-- */
02149   {
02150     MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
02151     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02152   },
02153 /* --reserved-- */
02154   {
02155     MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
02156     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02157   },
02158 /* --reserved-- */
02159   {
02160     MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
02161     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02162   },
02163 /* --reserved-- */
02164   {
02165     MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
02166     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02167   },
02168 /* --reserved-- */
02169   {
02170     MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
02171     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02172   },
02173 /* --reserved-- */
02174   {
02175     MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
02176     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02177   },
02178 /* --reserved-- */
02179   {
02180     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
02181     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02182   },
02183 /* --reserved-- */
02184   {
02185     MEP_INSN_RI_24, "ri-24", "--reserved--", 16,
02186     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02187   },
02188 /* --reserved-- */
02189   {
02190     MEP_INSN_RI_25, "ri-25", "--reserved--", 16,
02191     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02192   },
02193 /* --reserved-- */
02194   {
02195     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
02196     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02197   },
02198 /* --reserved-- */
02199   {
02200     MEP_INSN_RI_16, "ri-16", "--reserved--", 16,
02201     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02202   },
02203 /* --reserved-- */
02204   {
02205     MEP_INSN_RI_18, "ri-18", "--reserved--", 16,
02206     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02207   },
02208 /* --reserved-- */
02209   {
02210     MEP_INSN_RI_19, "ri-19", "--reserved--", 16,
02211     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02212   },
02213 /* fadds ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
02214   {
02215     MEP_INSN_FADDS, "fadds", "fadds", 32,
02216     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02217   },
02218 /* fsubs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
02219   {
02220     MEP_INSN_FSUBS, "fsubs", "fsubs", 32,
02221     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02222   },
02223 /* fmuls ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
02224   {
02225     MEP_INSN_FMULS, "fmuls", "fmuls", 32,
02226     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02227   },
02228 /* fdivs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
02229   {
02230     MEP_INSN_FDIVS, "fdivs", "fdivs", 32,
02231     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02232   },
02233 /* fsqrts ${fmax-FRd},${fmax-FRn} */
02234   {
02235     MEP_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
02236     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02237   },
02238 /* fabss ${fmax-FRd},${fmax-FRn} */
02239   {
02240     MEP_INSN_FABSS, "fabss", "fabss", 32,
02241     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02242   },
02243 /* fnegs ${fmax-FRd},${fmax-FRn} */
02244   {
02245     MEP_INSN_FNEGS, "fnegs", "fnegs", 32,
02246     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02247   },
02248 /* fmovs ${fmax-FRd},${fmax-FRn} */
02249   {
02250     MEP_INSN_FMOVS, "fmovs", "fmovs", 32,
02251     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02252   },
02253 /* froundws ${fmax-FRd-int},${fmax-FRn} */
02254   {
02255     MEP_INSN_FROUNDWS, "froundws", "froundws", 32,
02256     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02257   },
02258 /* ftruncws ${fmax-FRd-int},${fmax-FRn} */
02259   {
02260     MEP_INSN_FTRUNCWS, "ftruncws", "ftruncws", 32,
02261     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02262   },
02263 /* fceilws ${fmax-FRd-int},${fmax-FRn} */
02264   {
02265     MEP_INSN_FCEILWS, "fceilws", "fceilws", 32,
02266     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02267   },
02268 /* ffloorws ${fmax-FRd-int},${fmax-FRn} */
02269   {
02270     MEP_INSN_FFLOORWS, "ffloorws", "ffloorws", 32,
02271     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02272   },
02273 /* fcvtws ${fmax-FRd-int},${fmax-FRn} */
02274   {
02275     MEP_INSN_FCVTWS, "fcvtws", "fcvtws", 32,
02276     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02277   },
02278 /* fcvtsw ${fmax-FRd},${fmax-FRn-int} */
02279   {
02280     MEP_INSN_FCVTSW, "fcvtsw", "fcvtsw", 32,
02281     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02282   },
02283 /* fcmpfs ${fmax-FRn},${fmax-FRm} */
02284   {
02285     MEP_INSN_FCMPFS, "fcmpfs", "fcmpfs", 32,
02286     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02287   },
02288 /* fcmpus ${fmax-FRn},${fmax-FRm} */
02289   {
02290     MEP_INSN_FCMPUS, "fcmpus", "fcmpus", 32,
02291     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02292   },
02293 /* fcmpes ${fmax-FRn},${fmax-FRm} */
02294   {
02295     MEP_INSN_FCMPES, "fcmpes", "fcmpes", 32,
02296     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02297   },
02298 /* fcmpues ${fmax-FRn},${fmax-FRm} */
02299   {
02300     MEP_INSN_FCMPUES, "fcmpues", "fcmpues", 32,
02301     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02302   },
02303 /* fcmpls ${fmax-FRn},${fmax-FRm} */
02304   {
02305     MEP_INSN_FCMPLS, "fcmpls", "fcmpls", 32,
02306     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02307   },
02308 /* fcmpuls ${fmax-FRn},${fmax-FRm} */
02309   {
02310     MEP_INSN_FCMPULS, "fcmpuls", "fcmpuls", 32,
02311     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02312   },
02313 /* fcmples ${fmax-FRn},${fmax-FRm} */
02314   {
02315     MEP_INSN_FCMPLES, "fcmples", "fcmples", 32,
02316     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02317   },
02318 /* fcmpules ${fmax-FRn},${fmax-FRm} */
02319   {
02320     MEP_INSN_FCMPULES, "fcmpules", "fcmpules", 32,
02321     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02322   },
02323 /* fcmpfis ${fmax-FRn},${fmax-FRm} */
02324   {
02325     MEP_INSN_FCMPFIS, "fcmpfis", "fcmpfis", 32,
02326     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02327   },
02328 /* fcmpuis ${fmax-FRn},${fmax-FRm} */
02329   {
02330     MEP_INSN_FCMPUIS, "fcmpuis", "fcmpuis", 32,
02331     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02332   },
02333 /* fcmpeis ${fmax-FRn},${fmax-FRm} */
02334   {
02335     MEP_INSN_FCMPEIS, "fcmpeis", "fcmpeis", 32,
02336     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02337   },
02338 /* fcmpueis ${fmax-FRn},${fmax-FRm} */
02339   {
02340     MEP_INSN_FCMPUEIS, "fcmpueis", "fcmpueis", 32,
02341     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02342   },
02343 /* fcmplis ${fmax-FRn},${fmax-FRm} */
02344   {
02345     MEP_INSN_FCMPLIS, "fcmplis", "fcmplis", 32,
02346     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02347   },
02348 /* fcmpulis ${fmax-FRn},${fmax-FRm} */
02349   {
02350     MEP_INSN_FCMPULIS, "fcmpulis", "fcmpulis", 32,
02351     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02352   },
02353 /* fcmpleis ${fmax-FRn},${fmax-FRm} */
02354   {
02355     MEP_INSN_FCMPLEIS, "fcmpleis", "fcmpleis", 32,
02356     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02357   },
02358 /* fcmpuleis ${fmax-FRn},${fmax-FRm} */
02359   {
02360     MEP_INSN_FCMPULEIS, "fcmpuleis", "fcmpuleis", 32,
02361     { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02362   },
02363 /* cmov ${fmax-FRd-int},${fmax-Rm} */
02364   {
02365     MEP_INSN_CMOV_FRN_RM, "cmov-frn-rm", "cmov", 32,
02366     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02367   },
02368 /* cmov ${fmax-Rm},${fmax-FRd-int} */
02369   {
02370     MEP_INSN_CMOV_RM_FRN, "cmov-rm-frn", "cmov", 32,
02371     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02372   },
02373 /* cmovc ${fmax-CCRn},${fmax-Rm} */
02374   {
02375     MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
02376     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02377   },
02378 /* cmovc ${fmax-Rm},${fmax-CCRn} */
02379   {
02380     MEP_INSN_CMOVC_RM_CCRN, "cmovc-rm-ccrn", "cmovc", 32,
02381     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
02382   },
02383 };
02384 
02385 #undef OP
02386 #undef A
02387 
02388 /* Initialize anything needed to be done once, before any cpu_open call.  */
02389 
02390 static void
02391 init_tables (void)
02392 {
02393 }
02394 
02395 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
02396 static void build_hw_table      (CGEN_CPU_TABLE *);
02397 static void build_ifield_table  (CGEN_CPU_TABLE *);
02398 static void build_operand_table (CGEN_CPU_TABLE *);
02399 static void build_insn_table    (CGEN_CPU_TABLE *);
02400 static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
02401 
02402 /* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name.  */
02403 
02404 static const CGEN_MACH *
02405 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
02406 {
02407   while (table->name)
02408     {
02409       if (strcmp (name, table->bfd_name) == 0)
02410        return table;
02411       ++table;
02412     }
02413   abort ();
02414 }
02415 
02416 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
02417 
02418 static void
02419 build_hw_table (CGEN_CPU_TABLE *cd)
02420 {
02421   int i;
02422   int machs = cd->machs;
02423   const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
02424   /* MAX_HW is only an upper bound on the number of selected entries.
02425      However each entry is indexed by it's enum so there can be holes in
02426      the table.  */
02427   const CGEN_HW_ENTRY **selected =
02428     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
02429 
02430   cd->hw_table.init_entries = init;
02431   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
02432   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
02433   /* ??? For now we just use machs to determine which ones we want.  */
02434   for (i = 0; init[i].name != NULL; ++i)
02435     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
02436        & machs)
02437       selected[init[i].type] = &init[i];
02438   cd->hw_table.entries = selected;
02439   cd->hw_table.num_entries = MAX_HW;
02440 }
02441 
02442 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
02443 
02444 static void
02445 build_ifield_table (CGEN_CPU_TABLE *cd)
02446 {
02447   cd->ifld_table = & mep_cgen_ifld_table[0];
02448 }
02449 
02450 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
02451 
02452 static void
02453 build_operand_table (CGEN_CPU_TABLE *cd)
02454 {
02455   int i;
02456   int machs = cd->machs;
02457   const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
02458   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
02459      However each entry is indexed by it's enum so there can be holes in
02460      the table.  */
02461   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
02462 
02463   cd->operand_table.init_entries = init;
02464   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
02465   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
02466   /* ??? For now we just use mach to determine which ones we want.  */
02467   for (i = 0; init[i].name != NULL; ++i)
02468     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
02469        & machs)
02470       selected[init[i].type] = &init[i];
02471   cd->operand_table.entries = selected;
02472   cd->operand_table.num_entries = MAX_OPERANDS;
02473 }
02474 
02475 /* Subroutine of mep_cgen_cpu_open to build the hardware table.
02476    ??? This could leave out insns not supported by the specified mach/isa,
02477    but that would cause errors like "foo only supported by bar" to become
02478    "unknown insn", so for now we include all insns and require the app to
02479    do the checking later.
02480    ??? On the other hand, parsing of such insns may require their hardware or
02481    operand elements to be in the table [which they mightn't be].  */
02482 
02483 static void
02484 build_insn_table (CGEN_CPU_TABLE *cd)
02485 {
02486   int i;
02487   const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
02488   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
02489 
02490   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
02491   for (i = 0; i < MAX_INSNS; ++i)
02492     insns[i].base = &ib[i];
02493   cd->insn_table.init_entries = insns;
02494   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
02495   cd->insn_table.num_init_entries = MAX_INSNS;
02496 }
02497 
02498 /* Subroutine of mep_cgen_cpu_open to rebuild the tables.  */
02499 
02500 static void
02501 mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
02502 {
02503   int i;
02504   CGEN_BITSET *isas = cd->isas;
02505   unsigned int machs = cd->machs;
02506 
02507   cd->int_insn_p = CGEN_INT_INSN_P;
02508 
02509   /* Data derived from the isa spec.  */
02510 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
02511   cd->default_insn_bitsize = UNSET;
02512   cd->base_insn_bitsize = UNSET;
02513   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
02514   cd->max_insn_bitsize = 0;
02515   for (i = 0; i < MAX_ISAS; ++i)
02516     if (cgen_bitset_contains (isas, i))
02517       {
02518        const CGEN_ISA *isa = & mep_cgen_isa_table[i];
02519 
02520        /* Default insn sizes of all selected isas must be
02521           equal or we set the result to 0, meaning "unknown".  */
02522        if (cd->default_insn_bitsize == UNSET)
02523          cd->default_insn_bitsize = isa->default_insn_bitsize;
02524        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
02525          ; /* This is ok.  */
02526        else
02527          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
02528 
02529        /* Base insn sizes of all selected isas must be equal
02530           or we set the result to 0, meaning "unknown".  */
02531        if (cd->base_insn_bitsize == UNSET)
02532          cd->base_insn_bitsize = isa->base_insn_bitsize;
02533        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
02534          ; /* This is ok.  */
02535        else
02536          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
02537 
02538        /* Set min,max insn sizes.  */
02539        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
02540          cd->min_insn_bitsize = isa->min_insn_bitsize;
02541        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
02542          cd->max_insn_bitsize = isa->max_insn_bitsize;
02543       }
02544 
02545   /* Data derived from the mach spec.  */
02546   for (i = 0; i < MAX_MACHS; ++i)
02547     if (((1 << i) & machs) != 0)
02548       {
02549        const CGEN_MACH *mach = & mep_cgen_mach_table[i];
02550 
02551        if (mach->insn_chunk_bitsize != 0)
02552        {
02553          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
02554            {
02555              fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
02556                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
02557              abort ();
02558            }
02559 
02560          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
02561        }
02562       }
02563 
02564   /* Determine which hw elements are used by MACH.  */
02565   build_hw_table (cd);
02566 
02567   /* Build the ifield table.  */
02568   build_ifield_table (cd);
02569 
02570   /* Determine which operands are used by MACH/ISA.  */
02571   build_operand_table (cd);
02572 
02573   /* Build the instruction table.  */
02574   build_insn_table (cd);
02575 }
02576 
02577 /* Initialize a cpu table and return a descriptor.
02578    It's much like opening a file, and must be the first function called.
02579    The arguments are a set of (type/value) pairs, terminated with
02580    CGEN_CPU_OPEN_END.
02581 
02582    Currently supported values:
02583    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
02584    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
02585    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
02586    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
02587    CGEN_CPU_OPEN_END:     terminates arguments
02588 
02589    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
02590    precluded.
02591 
02592    ??? We only support ISO C stdargs here, not K&R.
02593    Laziness, plus experiment to see if anything requires K&R - eventually
02594    K&R will no longer be supported - e.g. GDB is currently trying this.  */
02595 
02596 CGEN_CPU_DESC
02597 mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
02598 {
02599   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
02600   static int init_p;
02601   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
02602   unsigned int machs = 0; /* 0 = "unspecified" */
02603   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
02604   va_list ap;
02605 
02606   if (! init_p)
02607     {
02608       init_tables ();
02609       init_p = 1;
02610     }
02611 
02612   memset (cd, 0, sizeof (*cd));
02613 
02614   va_start (ap, arg_type);
02615   while (arg_type != CGEN_CPU_OPEN_END)
02616     {
02617       switch (arg_type)
02618        {
02619        case CGEN_CPU_OPEN_ISAS :
02620          isas = va_arg (ap, CGEN_BITSET *);
02621          break;
02622        case CGEN_CPU_OPEN_MACHS :
02623          machs = va_arg (ap, unsigned int);
02624          break;
02625        case CGEN_CPU_OPEN_BFDMACH :
02626          {
02627            const char *name = va_arg (ap, const char *);
02628            const CGEN_MACH *mach =
02629              lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
02630 
02631            machs |= 1 << mach->num;
02632            break;
02633          }
02634        case CGEN_CPU_OPEN_ENDIAN :
02635          endian = va_arg (ap, enum cgen_endian);
02636          break;
02637        default :
02638          fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n",
02639                  arg_type);
02640          abort (); /* ??? return NULL? */
02641        }
02642       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
02643     }
02644   va_end (ap);
02645 
02646   /* Mach unspecified means "all".  */
02647   if (machs == 0)
02648     machs = (1 << MAX_MACHS) - 1;
02649   /* Base mach is always selected.  */
02650   machs |= 1;
02651   if (endian == CGEN_ENDIAN_UNKNOWN)
02652     {
02653       /* ??? If target has only one, could have a default.  */
02654       fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n");
02655       abort ();
02656     }
02657 
02658   cd->isas = cgen_bitset_copy (isas);
02659   cd->machs = machs;
02660   cd->endian = endian;
02661   /* FIXME: for the sparc case we can determine insn-endianness statically.
02662      The worry here is where both data and insn endian can be independently
02663      chosen, in which case this function will need another argument.
02664      Actually, will want to allow for more arguments in the future anyway.  */
02665   cd->insn_endian = endian;
02666 
02667   /* Table (re)builder.  */
02668   cd->rebuild_tables = mep_cgen_rebuild_tables;
02669   mep_cgen_rebuild_tables (cd);
02670 
02671   /* Default to not allowing signed overflow.  */
02672   cd->signed_overflow_ok_p = 0;
02673   
02674   return (CGEN_CPU_DESC) cd;
02675 }
02676 
02677 /* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
02678    MACH_NAME is the bfd name of the mach.  */
02679 
02680 CGEN_CPU_DESC
02681 mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
02682 {
02683   return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
02684                             CGEN_CPU_OPEN_ENDIAN, endian,
02685                             CGEN_CPU_OPEN_END);
02686 }
02687 
02688 /* Close a cpu table.
02689    ??? This can live in a machine independent file, but there's currently
02690    no place to put this file (there's no libcgen).  libopcodes is the wrong
02691    place as some simulator ports use this but they don't use libopcodes.  */
02692 
02693 void
02694 mep_cgen_cpu_close (CGEN_CPU_DESC cd)
02695 {
02696   unsigned int i;
02697   const CGEN_INSN *insns;
02698 
02699   if (cd->macro_insn_table.init_entries)
02700     {
02701       insns = cd->macro_insn_table.init_entries;
02702       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
02703        if (CGEN_INSN_RX ((insns)))
02704          regfree (CGEN_INSN_RX (insns));
02705     }
02706 
02707   if (cd->insn_table.init_entries)
02708     {
02709       insns = cd->insn_table.init_entries;
02710       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
02711        if (CGEN_INSN_RX (insns))
02712          regfree (CGEN_INSN_RX (insns));
02713     }  
02714 
02715   if (cd->macro_insn_table.init_entries)
02716     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
02717 
02718   if (cd->insn_table.init_entries)
02719     free ((CGEN_INSN *) cd->insn_table.init_entries);
02720 
02721   if (cd->hw_table.entries)
02722     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
02723 
02724   if (cd->operand_table.entries)
02725     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
02726 
02727   free (cd);
02728 }
02729