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cell-binutils  2.17cvs20070401
mcore-opc.h
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00001 /* Assembler instructions for Motorola's Mcore processor
00002    Copyright 1999, 2000, 2002 Free Software Foundation, Inc.
00003 
00004    
00005 This program is free software; you can redistribute it and/or modify
00006 it under the terms of the GNU General Public License as published by
00007 the Free Software Foundation; either version 2 of the License, or
00008 (at your option) any later version.
00009 
00010 This program is distributed in the hope that it will be useful,
00011 but WITHOUT ANY WARRANTY; without even the implied warranty of
00012 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013 GNU General Public License for more details.
00014 
00015 You should have received a copy of the GNU General Public License
00016 along with this program; if not, write to the Free Software
00017 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00018 
00019 #include "ansidecl.h"
00020 
00021 typedef enum
00022 {
00023   O0,    OT,   O1,   OC,   O2,    X1,    OI,    OB,
00024   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
00025   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
00026   O1R1,  OMb,  OMc,  SIa,
00027   MULSH, OPSR,
00028   JC,    JU,   JL,   RSI,  DO21,  OB2
00029 }
00030 mcore_opclass;
00031 
00032 typedef struct inst
00033 {
00034   char *         name;
00035   mcore_opclass  opclass;
00036   unsigned char  transfer;
00037   unsigned short inst;
00038 }
00039 mcore_opcode_info;
00040 
00041 #ifdef DEFINE_TABLE
00042 const mcore_opcode_info mcore_table[] =
00043 {
00044   { "bkpt",   O0,    0,     0x0000 },
00045   { "sync",   O0,    0,     0x0001 },
00046   { "rte",    O0,    1,     0x0002 },
00047   { "rfe",    O0,    1,     0x0002 },
00048   { "rfi",    O0,    1,     0x0003 },
00049   { "stop",   O0,    0,     0x0004 },
00050   { "wait",   O0,    0,     0x0005 },
00051   { "doze",   O0,    0,     0x0006 },
00052   { "idly4",    O0,     0,      0x0007 },
00053   { "trap",   OT,    0,     0x0008 },
00054 /* SPACE:                       0x000C - 0x000F */
00055 /* SPACE:                       0x0010 - 0x001F */
00056   { "mvc",    O1,    0,     0x0020 },
00057   { "mvcv",   O1,    0,     0x0030 },
00058   { "ldq",    RQ,    0,     0x0040 },
00059   { "stq",    RQ,    0,     0x0050 },
00060   { "ldm",    RM,    0,     0x0060 },
00061   { "stm",    RM,    0,     0x0070 },
00062   { "dect",   O1,    0,     0x0080 },
00063   { "decf",   O1,    0,     0x0090 },
00064   { "inct",   O1,    0,     0x00A0 },
00065   { "incf",   O1,    0,     0x00B0 },
00066   { "jmp",    JMP,   2,     0x00C0 },
00067 #define       MCORE_INST_JMP       0x00C0
00068   { "jsr",    JSR,   0,     0x00D0 },
00069 #define       MCORE_INST_JSR       0x00E0
00070   { "ff1",    O1,    0,     0x00E0 },
00071   { "brev",   O1,    0,     0x00F0 },
00072   { "xtrb3",  X1,    0,     0x0100 },
00073   { "xtrb2",  X1,    0,     0x0110 },
00074   { "xtrb1",  X1,    0,     0x0120 },
00075   { "xtrb0",  X1,    0,     0x0130 },
00076   { "zextb",  O1,    0,     0x0140 },
00077   { "sextb",  O1,    0,     0x0150 },
00078   { "zexth",  O1,    0,     0x0160 },
00079   { "sexth",  O1,    0,     0x0170 },
00080   { "declt",  O1,    0,     0x0180 },
00081   { "tstnbz", O1,    0,     0x0190 },
00082   { "decgt",  O1,    0,     0x01A0 },
00083   { "decne",  O1,    0,     0x01B0 },
00084   { "clrt",   O1,    0,     0x01C0 },
00085   { "clrf",   O1,    0,     0x01D0 },
00086   { "abs",    O1,    0,     0x01E0 },
00087   { "not",    O1,    0,     0x01F0 },
00088   { "movt",   O2,    0,     0x0200 },
00089   { "mult",   O2,    0,     0x0300 },
00090   { "loopt",  BL,    0,     0x0400 },
00091   { "subu",   O2,    0,     0x0500 },
00092   { "sub",    O2,    0,     0x0500 }, /* Official alias.  */
00093   { "addc",   O2,    0,     0x0600 },
00094   { "subc",   O2,    0,     0x0700 },
00095 /* SPACE: 0x0800-0x08ff for a diadic operation */
00096 /* SPACE: 0x0900-0x09ff for a diadic operation */
00097   { "movf",   O2,    0,     0x0A00 },
00098   { "lsr",    O2,    0,     0x0B00 },
00099   { "cmphs",  O2,    0,     0x0C00 },
00100   { "cmplt",  O2,    0,     0x0D00 },
00101   { "tst",    O2,    0,     0x0E00 },
00102   { "cmpne",  O2,    0,     0x0F00 },
00103   { "mfcr",   OC,    0,     0x1000 },
00104   { "psrclr", OPSR,  0,     0x11F0 },
00105   { "psrset", OPSR,  0,     0x11F8 },
00106   { "mov",    O2,    0,     0x1200 },
00107   { "bgenr",  O2,    0,     0x1300 },
00108   { "rsub",   O2,    0,     0x1400 },
00109   { "ixw",    O2,    0,     0x1500 },
00110   { "and",    O2,    0,     0x1600 },
00111   { "xor",    O2,    0,     0x1700 },
00112   { "mtcr",   OC,    0,     0x1800 },
00113   { "asr",    O2,    0,     0x1A00 },
00114   { "lsl",    O2,    0,     0x1B00 },
00115   { "addu",   O2,    0,     0x1C00 },
00116   { "add",    O2,    0,     0x1C00 }, /* Official alias.  */
00117   { "ixh",    O2,    0,     0x1D00 },
00118   { "or",     O2,    0,     0x1E00 },
00119   { "andn",   O2,    0,     0x1F00 },
00120   { "addi",   OI,    0,     0x2000 },
00121 #define       MCORE_INST_ADDI      0x2000
00122   { "cmplti", OI,    0,     0x2200 },
00123   { "subi",   OI,    0,     0x2400 },
00124 /* SPACE: 0x2600-0x27ff open for a register+immediate  operation */
00125   { "rsubi",  OB,    0,     0x2800 },
00126   { "cmpnei", OB,    0,     0x2A00 },
00127   { "bmaski", OMa,   0,     0x2C00 },
00128   { "divu",   O1R1,  0,     0x2C10 },
00129 /* SPACE:                       0x2c20 - 0x2c7f */  
00130   { "bmaski", OMb,   0,     0x2C80 },
00131   { "bmaski", OMc,   0,     0x2D00 },
00132   { "andi",   OB,    0,     0x2E00 },
00133   { "bclri",  OB,    0,     0x3000 },
00134 /* SPACE:                       0x3200 - 0x320f */
00135   { "divs",   O1R1,  0,     0x3210 },
00136 /* SPACE:                       0x3220 - 0x326f */  
00137   { "bgeni",  OBRa,  0,     0x3270 },
00138   { "bgeni",  OBRb,  0,     0x3280 },
00139   { "bgeni",  OBRc,  0,     0x3300 },
00140   { "bseti",  OB,    0,     0x3400 },
00141   { "btsti",  OB,    0,     0x3600 },
00142   { "xsr",    O1,    0,     0x3800 },
00143   { "rotli",  SIa,   0,     0x3800 },
00144   { "asrc",   O1,    0,     0x3A00 },
00145   { "asri",   SIa,   0,     0x3A00 },
00146   { "lslc",   O1,    0,     0x3C00 },
00147   { "lsli",   SIa,   0,     0x3C00 },
00148   { "lsrc",   O1,    0,     0x3E00 },
00149   { "lsri",   SIa,   0,     0x3E00 },
00150 /* SPACE:                       0x4000 - 0x5fff */
00151   { "movi",   I7,    0,     0x6000 },
00152 #define MCORE_INST_BMASKI_ALT      0x6000
00153 #define MCORE_INST_BGENI_ALT       0x6000
00154   { "mulsh",    MULSH,  0,      0x6800 },
00155   { "muls.h",   MULSH,  0,      0x6800 },
00156 /* SPACE:                       0x6900 - 0x6FFF */
00157   { "jmpi",   LJ,    1,     0x7000 },
00158   { "jsri",   LJ,    0,     0x7F00 },
00159 #define       MCORE_INST_JMPI      0x7000
00160   { "lrw",    LR,    0,     0x7000 },
00161 #define       MCORE_INST_JSRI      0x7F00
00162   { "ld",     LS,    0,     0x8000 },
00163   { "ldw",    LS,    0,     0x8000 },
00164   { "ld.w",   LS,    0,     0x8000 },
00165   { "st",     LS,    0,     0x9000 },
00166   { "stw",    LS,    0,     0x9000 },
00167   { "st.w",   LS,    0,     0x9000 },
00168   { "ldb",    LS,    0,     0xA000 },
00169   { "ld.b",   LS,    0,     0xA000 },
00170   { "stb",    LS,    0,     0xB000 },
00171   { "st.b",   LS,    0,     0xB000 },
00172   { "ldh",    LS,    0,     0xC000 },
00173   { "ld.h",   LS,    0,     0xC000 },
00174   { "sth",    LS,    0,     0xD000 },
00175   { "st.h",   LS,    0,     0xD000 },
00176   { "bt",     BR,    0,     0xE000 },
00177   { "bf",     BR,    0,     0xE800 },
00178   { "br",     BR,    1,     0xF000 },
00179 #define       MCORE_INST_BR 0xF000
00180   { "bsr",    BR,    0,     0xF800 },
00181 #define       MCORE_INST_BSR       0xF800
00182 
00183 /* The following are relaxable branches */
00184   { "jbt",    JC,    0,     0xE000 },
00185   { "jbf",    JC,    0,     0xE800 },
00186   { "jbr",    JU,    1,     0xF000 },
00187   { "jbsr",   JL,    0,     0xF800 },
00188 
00189 /* The following are aliases for other instructions */
00190   { "rts",    O0,    2,     0x00CF },  /* jmp r15 */
00191   { "rolc",   DO21,  0,     0x0600 },  /* addc rd,rd */
00192   { "rotlc",  DO21,   0,    0x0600 },  /* addc rd,rd */
00193   { "setc",   O0,    0,     0x0C00 },  /* cmphs r0,r0 */
00194   { "clrc",   O0,    0,     0x0F00 },  /* cmpne r0,r0 */
00195   { "tstle",  O1,    0,     0x2200 },  /* cmplti rd,1 */
00196   { "cmplei", OB,    0,     0x2200 },  /* cmplei rd,X -> cmplti rd,X+1 */
00197   { "neg",    O1,    0,     0x2800 },  /* rsubi rd,0 */
00198   { "tstne",  O1,    0,     0x2A00 },  /* cmpnei rd,0 */
00199   { "tstlt",  O1,    0,     0x37F0 },  /* btsti rx,31 */
00200   { "mclri",  OB2,   0,     0x3000 },  /* bclri rx,log2(imm) */
00201   { "mgeni",  OBR2,  0,     0x3200 },  /* bgeni rx,log2(imm) */
00202   { "mseti",  OB2,   0,     0x3400 },  /* bseti rx,log2(imm) */
00203   { "mtsti",  OB2,   0,     0x3600 },  /* btsti rx,log2(imm) */
00204   { "rori",   RSI,   0,     0x3800 },
00205   { "rotri",  RSI,    0,    0x3800 },
00206   { "nop",    O0,     0,    0x1200 },  /* mov r0, r0 */
00207   { 0,        0,     0,      0 }
00208 };
00209 #endif