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cell-binutils  2.17cvs20070401
maxq-dis.c
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00001 /* Instruction printing code for the MAXQ
00002 
00003    Copyright 2004, 2005 Free Software Foundation, Inc.
00004 
00005    Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
00006    S.(inderpreetb@noida.hcltech.com)
00007 
00008    This file is part of GDB.
00009 
00010    This program is free software; you can redistribute it and/or modify it
00011    under the terms of the GNU General Public License as published by the Free 
00012    Software Foundation; either version 2 of the License, or (at your option)
00013    any later version.
00014 
00015    This program is distributed in the hope that it will be useful, but
00016    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
00017    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
00018    for more details.
00019 
00020    You should have received a copy of the GNU General Public License along
00021    with this program; if not, write to the Free Software Foundation, Inc., 
00022    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00023 
00024 #include "sysdep.h"
00025 #include "dis-asm.h"
00026 #include "opcode/maxq.h"
00027 
00028 struct _group_info
00029 {
00030   unsigned char group_no;
00031   unsigned char sub_opcode;
00032   unsigned char src;
00033   unsigned char dst;
00034   unsigned char fbit;
00035   unsigned char bit_no;
00036   unsigned char flag;
00037 
00038 };
00039 
00040 typedef struct _group_info group_info;
00041 
00042 #define SRC   0x01
00043 #define DST   0x02
00044 #define FORMAT       0x04
00045 #define BIT_NO       0x08
00046 #define SUB_OP       0x10
00047 
00048 #define MASK_LOW_BYTE 0x0f
00049 #define MASK_HIGH_BYTE 0xf0
00050 
00051 /* Flags for retrieving the bits from the op-code.  */
00052 #define _DECODE_LOWNIB_LOWBYTE  0x000f
00053 #define _DECODE_HIGHNIB_LOWBYTE 0x00f0
00054 #define _DECODE_LOWNIB_HIGHBYTE 0x0f00
00055 #define _DECODE_HIGHNIB_HIGHBYTE 0xf000
00056 #define _DECODE_HIGHBYTE 0xff00
00057 #define _DECODE_LOWBYTE  0x00ff
00058 #define _DECODE_4TO6_HIGHBYTE 0x7000
00059 #define _DECODE_4TO6_LOWBYTE 0x0070
00060 #define _DECODE_0TO6_HIGHBYTE 0x7f00
00061 #define _DECODE_0TO2_HIGHBYTE 0x0700
00062 #define _DECODE_GET_F_HIGHBYTE 0x8000
00063 #define _DECODE_BIT7_HIGHBYTE 0x8000
00064 #define _DECODE_BIT7_LOWBYTE 0x0080
00065 #define _DECODE_GET_CARRY 0x10000
00066 #define _DECODE_BIT0_LOWBYTE 0x1
00067 #define _DECODE_BIT6AND7_HIGHBYTE 0xc000
00068 
00069 /* Module and Register Indexed of System Registers.  */
00070 #define _CURR_ACC_MODINDEX 0xa
00071 #define _CURR_ACC_REGINDEX 0x0
00072 #define _PSF_REG_MODINDEX  0x8
00073 #define _PSF_REG_REGINDEX  0x4
00074 #define _PFX_REG_MODINDEX  0xb
00075 #define _PFX0_REG_REGINDEX 0x0
00076 #define _PFX2_REG_REGINDEX 0x2
00077 #define _DP_REG_MODINDEX   0xf
00078 #define _DP0_REG_REGINDEX  0x3
00079 #define _DP1_REG_REGINDEX  0x7
00080 #define _IP_REG_MODINDEX   0xc
00081 #define _IP_REG_REGINDEX   0x0
00082 #define _IIR_REG_MODINDEX  0x8
00083 #define _IIR_REG_REGINDEX  0xb
00084 #define _SP_REG_MODINDEX   0xd
00085 #define _SP_REG_REGINDEX   0x1
00086 #define _IC_REG_MODINDEX   0x8
00087 #define _IC_REG_REGINDEX   0x5
00088 #define _LC_REG_MODINDEX   0xe
00089 #define _LC0_REG_REGINDEX  0x0
00090 #define _LC1_REG_REGINDEX  0x1
00091 #define _LC2_REG_REGINDEX  0x2
00092 #define _LC3_REG_REGINDEX  0x3
00093 
00094 /* Flags for finding the bits in PSF Register.  */
00095 #define SIM_ALU_DECODE_CARRY_BIT_POS  0x2
00096 #define SIM_ALU_DECODE_SIGN_BIT_POS   0x40
00097 #define SIM_ALU_DECODE_ZERO_BIT_POS   0x80
00098 #define SIM_ALU_DECODE_EQUAL_BIT_POS  0x1
00099 #define SIM_ALU_DECODE_IGE_BIT_POS    0x1
00100 
00101 /* Number Of Op-code Groups.  */
00102 unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 11;
00103 
00104 /* Op-code Groups.  */
00105 unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
00106 
00107 /* Group1: AND/OR/XOR/ADD/SUB Operations: fxxx 1010 ssss ssss.  */
00108 unsigned char const SIM_ALU_DECODE_AND_OR_ADD_SUB_OP_GROUP = 2;
00109 
00110 /* Group2: Logical Operations: 1000 1010 xxxx 1010.  */
00111 unsigned char const SIM_ALU_DECODE_BIT_OP_GROUP = 3;
00112 
00113 /* XCHG/Bit Operations: 1xxx 1010 xxxx 1010.  */
00114 unsigned char const SIM_ALU_DECODE_SET_DEST_BIT_GROUP = 4;
00115 
00116 /* Move value in bit of destination register: 1ddd dddd xbbb 0111.  */
00117 unsigned char const SIM_ALU_DECODE_JUMP_OP_GROUP = 5;
00118 
00119 #define JUMP_CHECK(insn)   \
00120    (   ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000) \
00121     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x2000) \
00122     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x6000) \
00123     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x1000) \
00124     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000) \
00125     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000) \
00126     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x7000) \
00127     || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000) )
00128 
00129 /* JUMP operations: fxxx 1100 ssss ssss */
00130 unsigned char const SIM_ALU_DECODE_RET_OP_GROUP = 6;
00131 
00132 /* RET Operations: 1xxx 1100 0000 1101 */
00133 unsigned char const SIM_ALU_DECODE_MOVE_SRC_DST_GROUP = 7;
00134 
00135 /* Move src into dest register: fddd dddd ssss ssss */
00136 unsigned char const SIM_ALU_DECODE_SET_SRC_BIT_GROUP = 8;
00137 
00138 /* Move value in bit of source register: fbbb 0111 ssss ssss */
00139 unsigned char const SIM_ALU_DECODE_DJNZ_CALL_PUSH_OP_GROUP = 9;
00140 
00141 /* PUSH, DJNZ and CALL operations: fxxx 1101 ssss ssss */
00142 unsigned char const SIM_ALU_DECODE_POP_OP_GROUP = 10;
00143 
00144 /* POP operation: 1ddd dddd 0000 1101 */
00145 unsigned char const SIM_ALU_DECODE_CMP_SRC_OP_GROUP = 11;
00146 
00147 /* GLOBAL */
00148 char unres_reg_name[20];
00149 
00150 static char *
00151 get_reg_name (unsigned char reg_code, type1 arg_pos)
00152 {
00153   unsigned char module;
00154   unsigned char index;
00155   int ix = 0;
00156   reg_entry const *reg_x;
00157   mem_access_syntax const *syntax;
00158   mem_access *mem_acc;
00159 
00160   module = 0;
00161   index = 0;
00162   module = (reg_code & MASK_LOW_BYTE);
00163   index = (reg_code & MASK_HIGH_BYTE);
00164   index = index >> 4;
00165 
00166   /* Search the system register table.  */
00167   for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL; ++reg_x)
00168     if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
00169       return reg_x->reg_name;
00170 
00171   /* Serch pheripheral table.  */
00172   for (ix = 0; ix < num_of_reg; ix++)
00173     {
00174       reg_x = &new_reg_table[ix];
00175 
00176       if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
00177        return reg_x->reg_name;
00178     }
00179 
00180   for (mem_acc = &mem_table[0]; mem_acc->name != NULL || !mem_acc; ++mem_acc)
00181     {
00182       if (reg_code == mem_acc->opcode)
00183        {
00184          for (syntax = mem_access_syntax_table;
00185               mem_access_syntax_table != NULL || mem_access_syntax_table->name;
00186               ++syntax)
00187            if (!strcmp (mem_acc->name, syntax->name))
00188              {
00189               if ((arg_pos == syntax->type) || (syntax->type == BOTH))
00190                 return mem_acc->name;
00191 
00192               break;
00193              }
00194        }
00195     }
00196 
00197   memset (unres_reg_name, 0, 20);
00198   sprintf (unres_reg_name, "%01x%01xh", index, module);
00199 
00200   return unres_reg_name;
00201 }
00202 
00203 static bfd_boolean
00204 check_move (unsigned char insn0, unsigned char insn8)
00205 {
00206   bfd_boolean first = FALSE;
00207   bfd_boolean second = FALSE;
00208   char *first_reg;
00209   char *second_reg;
00210   reg_entry const *reg_x;
00211   const unsigned char module1 = insn0 & MASK_LOW_BYTE;
00212   const unsigned char index1 = ((insn0 & 0x70) >> 4);
00213   const unsigned char module2 = insn8 & MASK_LOW_BYTE;
00214   const unsigned char index2 = ((insn8 & MASK_HIGH_BYTE) >> 4);
00215 
00216   /* DST */
00217   if (((insn0 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
00218       && ((index1 == 0) || (index1 == 1) || (index1 == 2) || (index1 == 5)
00219          || (index1 == 4) || (index1 == 6)))
00220     first = TRUE;
00221 
00222   else if (((insn0 & MASK_LOW_BYTE) == 0x0D) && (index1 == 0))
00223     first = TRUE;
00224 
00225   else if ((module1 == 0x0E)
00226           && ((index1 == 0) || (index1 == 1) || (index1 == 2)))
00227     first = TRUE;
00228 
00229   else
00230     {
00231       for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL && reg_x;
00232           ++reg_x)
00233        {
00234          if ((reg_x->Mod_name == module1) && (reg_x->Mod_index == index1)
00235              && ((reg_x->rtype == Reg_16W) || (reg_x->rtype == Reg_8W)))
00236            {
00237              /* IP not allowed.  */
00238              if ((reg_x->Mod_name == 0x0C) && (reg_x->Mod_index == 0x00))
00239               continue;
00240 
00241              /* A[AP] not allowed.  */
00242              if ((reg_x->Mod_name == 0x0A) && (reg_x->Mod_index == 0x01))
00243               continue;
00244              first_reg = reg_x->reg_name;
00245              first = TRUE;
00246              break;
00247            }
00248        }
00249     }
00250 
00251   if (!first)
00252     /* No need to check further.  */
00253     return FALSE;
00254 
00255   if (insn0 & 0x80)
00256     {
00257       /* SRC */
00258       if (((insn8 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
00259          && ((index2 == 0) || (index2 == 1) || (index2 == 2) || (index2 == 4)
00260              || (index2 == 5) || (index2 == 6)))
00261        second = TRUE;
00262 
00263       else if (((insn8 & MASK_LOW_BYTE) == 0x0D) && (index2 == 0))
00264        second = TRUE;
00265 
00266       else if ((module2 == 0x0E)
00267               && ((index2 == 0) || (index2 == 1) || (index2 == 2)))
00268        second = TRUE;
00269 
00270       else
00271        {
00272          for (reg_x = &system_reg_table[0];
00273               reg_x->reg_name != NULL && reg_x;
00274               ++reg_x)
00275            {
00276              if ((reg_x->Mod_name == (insn8 & MASK_LOW_BYTE))
00277                 && (reg_x->Mod_index == (((insn8 & 0xf0) >> 4))))
00278               {
00279                 second = TRUE;
00280                 second_reg = reg_x->reg_name;
00281                 break;
00282               }
00283            }
00284        }      
00285 
00286       if (second)
00287        {
00288          if ((module1 == 0x0A && index1 == 0x0)
00289              && (module2 == 0x0A && index2 == 0x01))
00290            return FALSE;
00291 
00292          return TRUE;
00293        }
00294 
00295       return FALSE;
00296     }
00297 
00298   return first;
00299 }
00300 
00301 static void
00302 maxq_print_arg (MAX_ARG_TYPE              arg,
00303               struct disassemble_info * info,
00304               group_info                grp)
00305 {
00306   switch (arg)
00307     {
00308     case FLAG_C:
00309       info->fprintf_func (info->stream, "C");
00310       break;
00311     case FLAG_NC:
00312       info->fprintf_func (info->stream, "NC");
00313       break;
00314 
00315     case FLAG_Z:
00316       info->fprintf_func (info->stream, "Z");
00317       break;
00318 
00319     case FLAG_NZ:
00320       info->fprintf_func (info->stream, "NZ");
00321       break;
00322 
00323     case FLAG_S:
00324       info->fprintf_func (info->stream, "S");
00325       break;
00326 
00327     case FLAG_E:
00328       info->fprintf_func (info->stream, "E");
00329       break;
00330 
00331     case FLAG_NE:
00332       info->fprintf_func (info->stream, "NE");
00333       break;
00334 
00335     case ACC_BIT:
00336       info->fprintf_func (info->stream, "Acc");
00337       if ((grp.flag & BIT_NO) == BIT_NO)
00338        info->fprintf_func (info->stream, ".%d", grp.bit_no);
00339       break;
00340 
00341     case A_BIT_0:
00342       info->fprintf_func (info->stream, "#0");
00343       break;
00344     case A_BIT_1:
00345       info->fprintf_func (info->stream, "#1");
00346       break;
00347 
00348     default:
00349       break;
00350     }
00351 }
00352 
00353 static unsigned char
00354 get_group (const unsigned int insn)
00355 {
00356   if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
00357     return 8;
00358 
00359   if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
00360     {
00361       /* && condition with sec part added on 26 May for resolving 2 & 3 grp
00362         conflict.  */
00363       if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
00364          && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
00365        {
00366          if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
00367            return 2;
00368          else
00369            return 3;
00370        }
00371 
00372       return 1;
00373     }
00374   else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
00375     {
00376       if (((insn & _DECODE_LOWBYTE) == 0x000D) && JUMP_CHECK (insn)
00377          && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
00378        return 6;
00379       else if ((insn & _DECODE_LOWBYTE) == 0x008D)
00380        return 7;
00381 
00382       return 5;
00383     }
00384   else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00)
00385           && (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000)
00386               || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000)
00387               || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000)
00388               || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
00389     return 10;
00390 
00391   else if ((insn & _DECODE_LOWBYTE) == 0x000D)
00392     return 11;
00393 
00394   else if ((insn & _DECODE_LOWBYTE) == 0x008D)
00395     return 12;
00396 
00397   else if ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800)
00398     return 13;
00399 
00400   else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
00401     return 9;
00402 
00403   else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
00404           && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
00405     return 4;
00406 
00407   return 8;
00408 }
00409 
00410 static void
00411 get_insn_opcode (const unsigned int insn, group_info *i)
00412 {
00413   static unsigned char pfx_flag = 0;
00414   static unsigned char count_for_pfx = 0;
00415 
00416   i->flag ^= i->flag;
00417   i->bit_no ^= i->bit_no;
00418   i->dst ^= i->dst;
00419   i->fbit ^= i->fbit;
00420   i->group_no ^= i->group_no;
00421   i->src ^= i->src;
00422   i->sub_opcode ^= i->sub_opcode;
00423 
00424   if (count_for_pfx > 0)
00425     count_for_pfx++;
00426 
00427   if (((insn >> 8) == 0x0b) || ((insn >> 8) == 0x2b))
00428     {
00429       pfx_flag = 1;
00430       count_for_pfx = 1;
00431     }
00432 
00433   i->group_no = get_group (insn);
00434 
00435   if (pfx_flag && (i->group_no == 0x0D) && (count_for_pfx == 2)
00436       && ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800))
00437     {
00438       i->group_no = 0x08;
00439       count_for_pfx = 0;
00440       pfx_flag ^= pfx_flag;
00441     }
00442 
00443   switch (i->group_no)
00444     {
00445     case 1:
00446       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
00447       i->flag |= SUB_OP;
00448       i->src = ((insn & _DECODE_LOWBYTE));
00449       i->flag |= SRC;
00450       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
00451       i->flag |= FORMAT;
00452       break;
00453 
00454     case 2:
00455       i->sub_opcode = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
00456       i->flag |= SUB_OP;
00457       break;
00458 
00459     case 3:
00460       i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
00461       i->flag |= SUB_OP;
00462       i->bit_no = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
00463       i->flag |= BIT_NO;
00464       break;
00465 
00466     case 4:
00467       i->sub_opcode = ((insn & _DECODE_BIT7_LOWBYTE) >> 7);
00468       i->flag |= SUB_OP;
00469       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
00470       i->flag |= DST;
00471       i->bit_no = ((insn & _DECODE_4TO6_LOWBYTE) >> 4);
00472       i->flag |= BIT_NO;
00473       break;
00474 
00475     case 5:
00476       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
00477       i->flag |= SUB_OP;
00478       i->src = ((insn & _DECODE_LOWBYTE));
00479       i->flag |= SRC;
00480       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
00481       i->flag |= FORMAT;
00482       break;
00483 
00484     case 6:
00485       i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
00486       i->flag |= SUB_OP;
00487       break;
00488 
00489     case 7:
00490       i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
00491       i->flag |= SUB_OP;
00492       break;
00493 
00494     case 8:
00495       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
00496       i->flag |= DST;
00497       i->src = ((insn & _DECODE_LOWBYTE));
00498       i->flag |= SRC;
00499       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
00500       i->flag |= FORMAT;
00501       break;
00502 
00503     case 9:
00504       i->sub_opcode = ((insn & _DECODE_0TO2_HIGHBYTE) >> 8);
00505       i->flag |= SUB_OP;
00506       i->bit_no = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
00507       i->flag |= BIT_NO;
00508       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
00509       i->flag |= FORMAT;
00510       i->src = ((insn & _DECODE_LOWBYTE));
00511       i->flag |= SRC;
00512       break;
00513 
00514     case 10:
00515       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
00516       i->flag |= SUB_OP;
00517       i->src = ((insn & _DECODE_LOWBYTE));
00518       i->flag |= SRC;
00519       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
00520       i->flag |= FORMAT;
00521       break;
00522 
00523     case 11:
00524       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
00525       i->flag |= DST;
00526       break;
00527 
00528     case 12:
00529       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
00530       i->flag |= DST;
00531       break;
00532 
00533     case 13:
00534       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
00535       i->flag |= SUB_OP;
00536       i->src = ((insn & _DECODE_LOWBYTE));
00537       i->flag |= SRC;
00538       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
00539       i->flag |= FORMAT;
00540       break;
00541 
00542     }
00543   return;
00544 }
00545 
00546 
00547 /* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the 
00548    instruction (always 2 on MAXQ20).  */
00549 
00550 static int
00551 print_insn (bfd_vma memaddr, struct disassemble_info *info,
00552            enum bfd_endian endianess)
00553 {
00554   /* The raw instruction.  */
00555   unsigned char insn[2], insn0, insn8, derived_code;
00556   unsigned int format;
00557   unsigned int actual_operands;
00558   unsigned int i;
00559   /* The group_info collected/decoded.  */
00560   group_info grp;
00561   MAXQ20_OPCODE_INFO const *opcode;
00562   int status;
00563 
00564   format = 0;
00565 
00566   status = info->read_memory_func (memaddr, (bfd_byte *) & insn[0], 2, info);
00567 
00568   if (status != 0)
00569     {
00570       info->memory_error_func (status, memaddr, info);
00571       return -1;
00572     }
00573 
00574   insn8 = insn[1];
00575   insn0 = insn[0];
00576 
00577   /* FIXME: Endianness always little.  */
00578   if (endianess == BFD_ENDIAN_BIG)
00579     get_insn_opcode (((insn[0] << 8) | (insn[1])), &grp);
00580   else
00581     get_insn_opcode (((insn[1] << 8) | (insn[0])), &grp);
00582 
00583   derived_code = ((grp.group_no << 4) | grp.sub_opcode);
00584 
00585   if (insn[0] == 0 && insn[1] == 0)
00586     {
00587       info->fprintf_func (info->stream, "00 00");
00588       return 2;
00589     }
00590 
00591   /* The opcode is always in insn0.  */
00592   for (opcode = &op_table[0]; opcode->name != NULL; ++opcode)
00593     {
00594       if (opcode->instr_id == derived_code)
00595        {
00596          if (opcode->instr_id == 0x3D)
00597            {
00598              if ((grp.bit_no == 0) && (opcode->arg[1] != A_BIT_0))
00599               continue;
00600              if ((grp.bit_no == 1) && (opcode->arg[1] != A_BIT_1))
00601               continue;
00602              if ((grp.bit_no == 3) && (opcode->arg[0] != 0))
00603               continue;
00604            }
00605 
00606          info->fprintf_func (info->stream, "%s ", opcode->name);
00607 
00608          actual_operands = 0;
00609 
00610          if ((grp.flag & SRC) == SRC)
00611            actual_operands++;
00612 
00613          if ((grp.flag & DST) == DST)
00614            actual_operands++;
00615 
00616          /* If Implict FLAG in the Instruction.  */
00617          if ((opcode->op_number > actual_operands)
00618              && !((grp.flag & SRC) == SRC) && !((grp.flag & DST) == DST))
00619            {
00620              for (i = 0; i < opcode->op_number; i++)
00621               {
00622                 if (i == 1 && (opcode->arg[1] != NO_ARG))
00623                   info->fprintf_func (info->stream, ",");
00624                 maxq_print_arg (opcode->arg[i], info, grp);
00625               }
00626            }
00627 
00628          /* DST is ABSENT in the grp.  */
00629          if ((opcode->op_number > actual_operands)
00630              && ((grp.flag & SRC) == SRC))
00631            {
00632              maxq_print_arg (opcode->arg[0], info, grp);
00633              info->fprintf_func (info->stream, " ");
00634 
00635              if (opcode->instr_id == 0xA4)
00636               info->fprintf_func (info->stream, "LC[0]");
00637 
00638              if (opcode->instr_id == 0xA5)
00639               info->fprintf_func (info->stream, "LC[1]");
00640 
00641              if ((grp.flag & SRC) == SRC)
00642               info->fprintf_func (info->stream, ",");
00643            }
00644 
00645          if ((grp.flag & DST) == DST)
00646            {
00647              if ((grp.flag & BIT_NO) == BIT_NO)
00648               {
00649                 info->fprintf_func (info->stream, " %s.%d",
00650                                   get_reg_name (grp.dst,
00651                                               (type1) 0 /*DST*/),
00652                                   grp.bit_no);
00653               }
00654              else
00655               info->fprintf_func (info->stream, " %s",
00656                                 get_reg_name (grp.dst, (type1) 0));
00657            }
00658 
00659          /* SRC is ABSENT in the grp.  */
00660          if ((opcode->op_number > actual_operands)
00661              && ((grp.flag & DST) == DST))
00662            {
00663              info->fprintf_func (info->stream, ",");
00664              maxq_print_arg (opcode->arg[1], info, grp);
00665              info->fprintf_func (info->stream, " ");
00666            }
00667 
00668          if ((grp.flag & SRC) == SRC)
00669            {
00670              if ((grp.flag & DST) == DST)
00671               info->fprintf_func (info->stream, ",");
00672 
00673              if ((grp.flag & BIT_NO) == BIT_NO)
00674               {
00675                 format = opcode->format;
00676 
00677                 if ((grp.flag & FORMAT) == FORMAT)
00678                   format = grp.fbit;
00679                 if (format == 1)
00680                   info->fprintf_func (info->stream, " %s.%d",
00681                                    get_reg_name (grp.src,
00682                                                 (type1) 1 /*SRC*/),
00683                                    grp.bit_no);
00684                 if (format == 0)
00685                   info->fprintf_func (info->stream, " #%02xh.%d",
00686                                    grp.src, grp.bit_no);
00687               }
00688              else
00689               {
00690                 format = opcode->format;
00691 
00692                 if ((grp.flag & FORMAT) == FORMAT)
00693                   format = grp.fbit;
00694                 if (format == 1)
00695                   info->fprintf_func (info->stream, " %s",
00696                                    get_reg_name (grp.src,
00697                                                 (type1) 1 /*SRC*/));
00698                 if (format == 0)
00699                   info->fprintf_func (info->stream, " #%02xh",
00700                                    (grp.src));
00701               }
00702            }
00703 
00704          return 2;
00705        }
00706     }
00707 
00708   info->fprintf_func (info->stream, "Unable to Decode :  %02x %02x",
00709                     insn[0], insn[1]);
00710   return 2;                 
00711 }
00712 
00713 int
00714 print_insn_maxq_little (bfd_vma memaddr, struct disassemble_info *info)
00715 {
00716   return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);
00717 }