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cell-binutils  2.17cvs20070401
maverick.c
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00001 /* Copyright (C) 2000, 2003 Free Software Foundation
00002    Contributed by Alexandre Oliva <aoliva@cygnus.com>
00003 
00004    This file is free software; you can redistribute it and/or modify it
00005    under the terms of the GNU General Public License as published by
00006    the Free Software Foundation; either version 2 of the License, or
00007    (at your option) any later version.
00008 
00009    This program is distributed in the hope that it will be useful, but
00010    WITHOUT ANY WARRANTY; without even the implied warranty of
00011    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012    General Public License for more details.
00013 
00014    You should have received a copy of the GNU General Public License
00015    along with this program; if not, write to the Free Software
00016    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00017 
00018 /* Generator of tests for Maverick.
00019 
00020    See the following file for usage and documentation.  */
00021 #include "../all/test-gen.c"
00022 
00023 /* These are the ARM registers.  Some of them have canonical names
00024    other than r##, so we'll use both in the asm input, but only the
00025    canonical names in the expected disassembler output.  */
00026 char *arm_regs[] =
00027   {
00028     /* Canonical names.  */
00029     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
00030     "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
00031     /* Alternate names, i.e., those that can be used in the assembler,
00032      * but that will never be emitted by the disassembler.  */
00033     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
00034     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
00035   };
00036 
00037 /* The various types of registers: ARM's registers, Maverick's
00038    f/d/fx/dx registers, Maverick's accumulators and Maverick's
00039    status register.  */
00040 #define armreg(shift) \
00041   reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
00042 #define mvreg(prefix, shift) \
00043   reg_p ("mv" prefix, shift, mk_get_bits (4u))
00044 #define acreg(shift) \
00045   reg_p ("mvax", shift, mk_get_bits (2u))
00046 #define dspsc \
00047   literal ("dspsc"), tick_random
00048 
00049 /* This outputs the condition flag that may follow each ARM insn.
00050    Since the condition 15 is invalid, we use it to check that the
00051    assembler recognizes the absence of a condition as `al'.  However,
00052    the disassembler won't ever output `al', so, if we emit it in the
00053    assembler, expect the condition to be omitted in the disassembler
00054    output.  */
00055 
00056 int
00057 arm_cond (func_arg * arg, insn_data * data)
00058 #define arm_cond { arm_cond }
00059 {
00060   static const char conds[16][3] =
00061     {
00062       "eq", "ne", "cs", "cc",
00063       "mi", "pl", "vs", "vc",
00064       "hi", "ls", "ge", "lt",
00065       "gt", "le", "al", ""
00066     };
00067   unsigned val = get_bits (4u);
00068 
00069   data->as_in = data->dis_out = strdup (conds[val]);
00070   if (val == 14)
00071     data->dis_out = strdup ("");
00072   data->bits = (val == 15 ? 14 : val) << 28;
00073   return 0;
00074 }
00075 
00076 /* The sign of an offset is actually used to determined whether the
00077    absolute value of the offset should be added or subtracted, so we
00078    must adjust negative values so that they do not overflow: -1024 is
00079    not valid, but -0 is distinct from +0.  */
00080 int
00081 off8s (func_arg * arg, insn_data * data)
00082 #define off8s { off8s }
00083 {
00084   int val;
00085   char value[9];
00086 
00087   /* Zero values are problematical.
00088      The assembler performs translations on the addressing modes
00089      for these values, meaning that we cannot just recreate the
00090      disassembler string in the LDST macro without knowing what
00091      value had been generated in off8s.  */
00092   do
00093     {
00094       val  = get_bits (9s);
00095     }
00096   while (val == -1 || val == 0);
00097   
00098   val <<= 2;
00099   if (val < 0)
00100     {
00101       val = -4 - val;
00102       sprintf (value, ", #-%i", val);
00103       data->dis_out = strdup (value);
00104       sprintf (value, ", #-%i", val);
00105       data->as_in = strdup (value);
00106       data->bits = val >> 2;
00107     }
00108   else
00109     {
00110       sprintf (value, ", #%i", val);
00111       data->as_in = data->dis_out = strdup (value);
00112       data->bits = (val >> 2) | (1 << 23);
00113     }
00114   
00115   return 0;
00116 }
00117 
00118 /* This function generates a 7-bit signed constant, emitted as
00119    follows: the 4 least-significant bits are stored in the 4
00120    least-significant bits of the word; the 3 most-significant bits are
00121    stored in bits 7:5, i.e., bit 4 is skipped.  */
00122 int
00123 imm7 (func_arg *arg, insn_data *data)
00124 #define imm7 { imm7 }
00125 {
00126   int val = get_bits (7s);
00127   char value[6];
00128 
00129   data->bits = (val & 0x0f) | (2 * (val & 0x70));
00130   sprintf (value, "#%i", val);
00131   data->as_in = data->dis_out = strdup (value);
00132   return 0;
00133 }
00134 
00135 /* Convenience wrapper to define_insn, that prefixes every insn with
00136    `cf' (so, if you specify command-line arguments, remember that `cf'
00137    must *not* be part of the string), and post-fixes a condition code.
00138    insname and insnvar specify the main insn name and a variant;
00139    they're just concatenated, and insnvar is often empty.  word is the
00140    bit pattern that defines the insn, properly shifted, and funcs is a
00141    sequence of funcs that define the operands and the syntax of the
00142    insn.  */
00143 #define mv_insn(insname, insnvar, word, funcs...) \
00144   define_insn (insname ## insnvar, \
00145              literal ("cf"), \
00146              insn_bits (insname, word), \
00147              arm_cond, \
00148              tab, \
00149              ## funcs)
00150 
00151 /* Define a single LDC/STC variant.  op is the main insn opcode; ld
00152    stands for load (it should be 0 on stores), dword selects 64-bit
00153    operations, pre should be enabled for pre-increment, and wb, for
00154    write-back.  sep1, sep2 and sep3 are syntactical elements ([]!)
00155    that the assembler will use to enable pre and wb.  It would
00156    probably have been cleaner to couple the syntactical elements with
00157    the pre/wb bits directly, but it would have required the definition
00158    of more functions.  */
00159 #define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \
00160   mv_insn (insname, insnvar, \
00161           (12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \
00162            mvreg (regname, 12), comma, \
00163            lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \
00164            tick_random)
00165 
00166 /* Define all variants of an LDR or STR instruction, namely,
00167    pre-indexed without write-back, pre-indexed with write-back and
00168    post-indexed.  */
00169 #define LDSTall(insname, op, ld, dword, regname) \
00170   LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
00171   LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \
00172   LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing)
00173 
00174 /* Produce the insn identifiers of all LDST variants of a given insn.
00175    To be used in the initialization of an insn group array.  */
00176 #define insns_LDSTall(insname) \
00177   insn (insname ## _p), insn (insname ## _pw), insn (insname)
00178 
00179 /* Define a CDP variant that uses two registers, at offsets 12 and 16.
00180    The two opcodes and the co-processor number identify the CDP
00181    insn.  */
00182 #define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
00183   mv_insn (insname##var, , \
00184           (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
00185           mvreg (reg1name, 12), comma, mvreg (reg2name, 16))
00186 
00187 /* Define a 32-bit integer CDP instruction with two operands.  */
00188 #define CDP2fx(insname, opcode1, opcode2) \
00189   CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
00190 
00191 /* Define a 64-bit integer CDP instruction with two operands.  */
00192 #define CDP2dx(insname, opcode1, opcode2) \
00193   CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
00194 
00195 /* Define a float CDP instruction with two operands.  */
00196 #define CDP2f(insname, opcode1, opcode2) \
00197   CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
00198 
00199 /* Define a double CDP instruction with two operands.  */
00200 #define CDP2d(insname, opcode1, opcode2) \
00201   CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")
00202 
00203 /* Define a CDP instruction with two register operands and one 7-bit
00204    signed immediate generated with imm7.  */
00205 #define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \
00206   mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \
00207           mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
00208           tick_random)
00209 
00210 /* Produce the insn identifiers of CDP floating-point or integer insn
00211    pairs (i.e., it appends the suffixes for 32-bit and 64-bit
00212    insns.  */
00213 #define CDPfp_insns(insname) \
00214   insn (insname ## s), insn (insname ## d)
00215 #define CDPx_insns(insname) \
00216   insn (insname ## 32), insn (insname ## 64)
00217 
00218 /* Define a CDP instruction with 3 operands, at offsets 12, 16, 0.  */
00219 #define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \
00220   mv_insn (insname##var, , \
00221           (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
00222           mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
00223           mvreg (reg3name, 0), tick_random)
00224 
00225 /* Define a 32-bit integer CDP instruction with three operands.  */
00226 #define CDP3fx(insname, opcode1, opcode2) \
00227   CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")
00228 
00229 /* Define a 64-bit integer CDP instruction with three operands.  */
00230 #define CDP3dx(insname, opcode1, opcode2) \
00231   CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")
00232 
00233 /* Define a float CDP instruction with three operands.  */
00234 #define CDP3f(insname, opcode1, opcode2) \
00235   CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")
00236 
00237 /* Define a double CDP instruction with three operands.  */
00238 #define CDP3d(insname, opcode1, opcode2) \
00239   CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")
00240 
00241 /* Define a CDP instruction with four operands, at offsets 5, 12, 16
00242  * and 0.  Used only for ACC instructions.  */
00243 #define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \
00244   mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \
00245           acreg (5), comma, reg2spec, comma, \
00246           mvreg (reg3name, 16), comma, mvreg (reg4name, 0))
00247 
00248 /* Define a CDP4 instruction with one accumulator operands.  */
00249 #define CDP41A(insname, opcode1) \
00250   CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")
00251 
00252 /* Define a CDP4 instruction with two accumulator operands.  */
00253 #define CDP42A(insname, opcode1) \
00254   CDP4 (insname, opcode1, acreg (12), "fx", "fx")
00255 
00256 /* Define a MCR or MRC instruction with two register operands.  */
00257 #define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \
00258   mv_insn (insname, , \
00259           ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
00260            ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
00261           reg1spec, comma, reg2spec)
00262 
00263 /* Define a move from a DSP register to an ARM register.  */
00264 #define MVDSPARM(insname, cpnum, opcode2, regDSPname) \
00265   MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
00266         mvreg (regDSPname, 16), armreg (12))
00267 
00268 /* Define a move from an ARM register to a DSP register.  */
00269 #define MVARMDSP(insname, cpnum, opcode2, regDSPname) \
00270   MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
00271         armreg (12), mvreg (regDSPname, 16))
00272 
00273 /* Move between coprocessor registers. A two operand CDP insn.   */
00274 #define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \
00275   mv_insn (insname, , \
00276           ((14 << 24) | ((opcode1) << 20) | \
00277            (4 << 8) | ((opcode2) << 5)), \
00278           reg1spec, comma, reg2spec)
00279 
00280 /* Define a move from a DSP register to a DSP accumulator.  */
00281 #define MVDSPACC(insname, opcode2, regDSPname) \
00282   MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))
00283 
00284 /* Define a move from a DSP accumulator to a DSP register.  */
00285 #define MVACCDSP(insname, opcode2, regDSPname) \
00286   MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))
00287 
00288 /* Define move insns between a float DSP register and an ARM
00289    register.  */
00290 #define MVf(nameAD, nameDA, opcode2) \
00291   MVDSPARM (nameAD, 4, opcode2, "f"); \
00292   MVARMDSP (nameDA, 4, opcode2, "f")
00293 
00294 /* Define move insns between a double DSP register and an ARM
00295    register.  */
00296 #define MVd(nameAD, nameDA, opcode2) \
00297   MVDSPARM (nameAD, 4, opcode2, "d"); \
00298   MVARMDSP (nameDA, 4, opcode2, "d")
00299 
00300 /* Define move insns between a 32-bit integer DSP register and an ARM
00301    register.  */
00302 #define MVfx(nameAD, nameDA, opcode2) \
00303   MVDSPARM (nameAD, 5, opcode2, "fx"); \
00304   MVARMDSP (nameDA, 5, opcode2, "fx")
00305 
00306 /* Define move insns between a 64-bit integer DSP register and an ARM
00307    register.  */
00308 #define MVdx(nameAD, nameDA, opcode2) \
00309   MVDSPARM (nameAD, 5, opcode2, "dx"); \
00310   MVARMDSP (nameDA, 5, opcode2, "dx")
00311 
00312 /* Define move insns between a 32-bit DSP register and a DSP
00313    accumulator.  */
00314 #define MVfxa(nameFA, nameAF, opcode2) \
00315   MVDSPACC (nameFA, opcode2, "fx"); \
00316   MVACCDSP (nameAF, opcode2, "fx")
00317 
00318 /* Define move insns between a 64-bit DSP register and a DSP
00319    accumulator.  */
00320 #define MVdxa(nameDA, nameAD, opcode2) \
00321   MVDSPACC (nameDA, opcode2, "dx"); \
00322   MVACCDSP (nameAD, opcode2, "dx")
00323 
00324 /* Produce the insn identifiers for a pair of mv insns.  */
00325 #define insns_MV(name1, name2) \
00326   insn (mv ## name1), insn (mv ## name2)
00327 
00328 /* Define a MCR or MRC instruction with three register operands.  */
00329 #define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
00330   mv_insn (insname, , \
00331           ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
00332            ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
00333           reg1spec, comma, reg2spec, comma, reg3spec, \
00334           tick_random)
00335 
00336 /* Define all load_store insns.  */
00337 LDSTall (ldrs, 4, 1, 0, "f");
00338 LDSTall (ldrd, 4, 1, 1, "d");
00339 LDSTall (ldr32, 5, 1, 0, "fx");
00340 LDSTall (ldr64, 5, 1, 1, "dx");
00341 LDSTall (strs, 4, 0, 0, "f");
00342 LDSTall (strd, 4, 0, 1, "d");
00343 LDSTall (str32, 5, 0, 0, "fx");
00344 LDSTall (str64, 5, 0, 1, "dx");
00345 
00346 /* Create the load_store insn group.  */
00347 func *load_store_insns[] =
00348   {
00349     insns_LDSTall (ldrs),  insns_LDSTall (ldrd),
00350     insns_LDSTall (ldr32), insns_LDSTall (ldr64),
00351     insns_LDSTall (strs),  insns_LDSTall (strd),
00352     insns_LDSTall (str32), insns_LDSTall (str64),
00353     0
00354   };
00355 
00356 /* Define all move insns.  */
00357 MVf (sr, rs, 2);
00358 MVd (dlr, rdl, 0);
00359 MVd (dhr, rdh, 1);
00360 MVdx (64lr, r64l, 0);
00361 MVdx (64hr, r64h, 1);
00362 MVfxa (al32, 32al, 2);
00363 MVfxa (am32, 32am, 3);
00364 MVfxa (ah32, 32ah, 4);
00365 MVfxa (a32, 32a, 5);
00366 MVdxa (a64, 64a, 6);
00367 MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12));
00368 MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc);
00369 CDP2 (cpys, , 4, 0, 0, "f", "f");
00370 CDP2 (cpyd, , 4, 0, 1, "d", "d");
00371 
00372 /* Create the move insns group.  */
00373 func * move_insns[] =
00374   {
00375     insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
00376     insns_MV (64lr, r64l), insns_MV (64hr, r64h),
00377     insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
00378     insns_MV (a32, 32a), insns_MV (a64, 64a),
00379     insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
00380     0
00381   };
00382 
00383 /* Define all conversion insns.  */
00384 CDP2 (cvtsd, , 4, 0, 3, "d", "f");
00385 CDP2 (cvtds, , 4, 0, 2, "f", "d");
00386 CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
00387 CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
00388 CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
00389 CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
00390 CDP2 (cvts32, , 5, 1, 4, "fx", "f");
00391 CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
00392 CDP2 (truncs32, , 5, 1, 6, "fx", "f");
00393 CDP2 (truncd32, , 5, 1, 7, "fx", "d");
00394 
00395 /* Create the conv insns group.  */
00396 func * conv_insns[] =
00397   {
00398     insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
00399     insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
00400     insn (truncs32), insn (truncd32),
00401     0
00402   };
00403 
00404 /* Define all shift insns.  */
00405 MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12));
00406 MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12));
00407 CDP2_imm7 (sh32, 5, 0, "fx", "fx");
00408 CDP2_imm7 (sh64, 5, 2, "dx", "dx");
00409 
00410 /* Create the shift insns group.  */
00411 func *shift_insns[] =
00412   {
00413     insn (rshl32), insn (rshl64),
00414     insn (sh32), insn (sh64),
00415     0
00416   };
00417 
00418 /* Define all comparison insns.  */
00419 MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
00420 MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
00421 MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
00422 MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));
00423 
00424 /* Create the comp insns group.  */
00425 func *comp_insns[] =
00426   {
00427     insn (cmps), insn (cmpd),
00428     insn (cmp32), insn (cmp64),
00429     0
00430   };
00431 
00432 /* Define all floating-point arithmetic insns.  */
00433 CDP2f (abs, 3, 0);
00434 CDP2d (abs, 3, 1);
00435 CDP2f (neg, 3, 2);
00436 CDP2d (neg, 3, 3);
00437 CDP3f (add, 3, 4);
00438 CDP3d (add, 3, 5);
00439 CDP3f (sub, 3, 6);
00440 CDP3d (sub, 3, 7);
00441 CDP3f (mul, 1, 0);
00442 CDP3d (mul, 1, 1);
00443 
00444 /* Create the fp-arith insns group.  */
00445 func *fp_arith_insns[] =
00446   {
00447     CDPfp_insns (abs), CDPfp_insns (neg),
00448     CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
00449     0
00450   };
00451 
00452 /* Define all integer arithmetic insns.  */
00453 CDP2fx (abs, 3, 0);
00454 CDP2dx (abs, 3, 1);
00455 CDP2fx (neg, 3, 2);
00456 CDP2dx (neg, 3, 3);
00457 CDP3fx (add, 3, 4);
00458 CDP3dx (add, 3, 5);
00459 CDP3fx (sub, 3, 6);
00460 CDP3dx (sub, 3, 7);
00461 CDP3fx (mul, 1, 0);
00462 CDP3dx (mul, 1, 1);
00463 CDP3fx (mac, 1, 2);
00464 CDP3fx (msc, 1, 3);
00465 
00466 /* Create the int-arith insns group.  */
00467 func * int_arith_insns[] =
00468   {
00469     CDPx_insns (abs), CDPx_insns (neg),
00470     CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
00471     insn (mac32), insn (msc32),
00472     0
00473   };
00474 
00475 /* Define all accumulator arithmetic insns.  */
00476 CDP41A (madd32, 0);
00477 CDP41A (msub32, 1);
00478 CDP42A (madda32, 2);
00479 CDP42A (msuba32, 3);
00480 
00481 /* Create the acc-arith insns group.  */
00482 func * acc_arith_insns[] =
00483   {
00484     insn (madd32), insn (msub32),
00485     insn (madda32), insn (msuba32),
00486     0
00487   };
00488 
00489 /* Create the set of all groups.  */
00490 group_t groups[] =
00491   {
00492     { "load_store", load_store_insns },
00493     { "move", move_insns },
00494     { "conv", conv_insns },
00495     { "shift", shift_insns },
00496     { "comp", comp_insns },
00497     { "fp_arith", fp_arith_insns },
00498     { "int_arith", int_arith_insns },
00499     { "acc_arith", acc_arith_insns },
00500     { 0 }
00501   };
00502 
00503 int
00504 main (int argc, char *argv[])
00505 {
00506   FILE *as_in = stdout, *dis_out = stderr;
00507 
00508   /* Check whether we're filtering insns.  */
00509   if (argc > 1)
00510     skip_list = argv + 1;
00511 
00512   /* Output assembler header.  */
00513   fputs ("\t.text\n"
00514         "\t.align\n",
00515         as_in);
00516   /* Output comments for the testsuite-driver and the initial
00517      disassembler output.  */
00518   fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
00519         "#name: Maverick\n"
00520         "#as: -mcpu=ep9312\n"
00521         "\n"
00522         "# Test the instructions of the Cirrus Maverick floating point co-processor\n"
00523         "\n"
00524         ".*: +file format.*arm.*\n"
00525         "\n"
00526         "Disassembly of section .text:\n",
00527         dis_out);
00528 
00529   /* Now emit all (selected) insns.  */
00530   output_groups (groups, as_in, dis_out);
00531 
00532   exit (0);
00533 }