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cell-binutils  2.17cvs20070401
Defines | Functions | Variables
maverick.c File Reference
#include "../all/test-gen.c"

Go to the source code of this file.

Defines

#define armreg(shift)   reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
#define mvreg(prefix, shift)   reg_p ("mv" prefix, shift, mk_get_bits (4u))
#define acreg(shift)   reg_p ("mvax", shift, mk_get_bits (2u))
#define dspsc   literal ("dspsc"), tick_random
#define arm_cond   { arm_cond }
#define off8s   { off8s }
#define imm7   { imm7 }
#define mv_insn(insname, insnvar, word, funcs...)
#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3)
#define LDSTall(insname, op, ld, dword, regname)
#define insns_LDSTall(insname)   insn (insname ## _p), insn (insname ## _pw), insn (insname)
#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name)
#define CDP2fx(insname, opcode1, opcode2)   CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
#define CDP2dx(insname, opcode1, opcode2)   CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
#define CDP2f(insname, opcode1, opcode2)   CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
#define CDP2d(insname, opcode1, opcode2)   CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")
#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name)
#define CDPfp_insns(insname)   insn (insname ## s), insn (insname ## d)
#define CDPx_insns(insname)   insn (insname ## 32), insn (insname ## 64)
#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name)
#define CDP3fx(insname, opcode1, opcode2)   CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")
#define CDP3dx(insname, opcode1, opcode2)   CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")
#define CDP3f(insname, opcode1, opcode2)   CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")
#define CDP3d(insname, opcode1, opcode2)   CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")
#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name)
#define CDP41A(insname, opcode1)   CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")
#define CDP42A(insname, opcode1)   CDP4 (insname, opcode1, acreg (12), "fx", "fx")
#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec)
#define MVDSPARM(insname, cpnum, opcode2, regDSPname)
#define MVARMDSP(insname, cpnum, opcode2, regDSPname)
#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec)
#define MVDSPACC(insname, opcode2, regDSPname)   MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))
#define MVACCDSP(insname, opcode2, regDSPname)   MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))
#define MVf(nameAD, nameDA, opcode2)
#define MVd(nameAD, nameDA, opcode2)
#define MVfx(nameAD, nameDA, opcode2)
#define MVdx(nameAD, nameDA, opcode2)
#define MVfxa(nameFA, nameAF, opcode2)
#define MVdxa(nameDA, nameAD, opcode2)
#define insns_MV(name1, name2)   insn (mv ## name1), insn (mv ## name2)
#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec)

Functions

int arm_cond (func_arg *arg, insn_data *data)
int off8s (func_arg *arg, insn_data *data)
int imm7 (func_arg *arg, insn_data *data)
 LDSTall (ldrs, 4, 1, 0,"f")
 LDSTall (ldrd, 4, 1, 1,"d")
 LDSTall (ldr32, 5, 1, 0,"fx")
 LDSTall (ldr64, 5, 1, 1,"dx")
 LDSTall (strs, 4, 0, 0,"f")
 LDSTall (strd, 4, 0, 1,"d")
 LDSTall (str32, 5, 0, 0,"fx")
 LDSTall (str64, 5, 0, 1,"dx")
 MVf (sr, rs, 2)
 MVd (dlr, rdl, 0)
 MVd (dhr, rdh, 1)
 MVdx (64lr, r64l, 0)
 MVdx (64hr, r64h, 1)
 MVfxa (al32, 32al, 2)
 MVfxa (am32, 32am, 3)
 MVfxa (ah32, 32ah, 4)
 MVfxa (a32, 32a, 5)
 MVdxa (a64, 64a, 6)
 MCC2 (mvsc32, 2, 7, dspsc, mvreg("dx", 12))
 MCC2 (mv32sc, 1, 7, mvreg("dx", 12), dspsc)
 CDP2 (cpys,, 4, 0, 0,"f","f")
 CDP2 (cpyd,, 4, 0, 1,"d","d")
 CDP2 (cvtsd,, 4, 0, 3,"d","f")
 CDP2 (cvtds,, 4, 0, 2,"f","d")
 CDP2 (cvt32s,, 4, 0, 4,"f","fx")
 CDP2 (cvt32d,, 4, 0, 5,"d","fx")
 CDP2 (cvt64s,, 4, 0, 6,"f","dx")
 CDP2 (cvt64d,, 4, 0, 7,"d","dx")
 CDP2 (cvts32,, 5, 1, 4,"fx","f")
 CDP2 (cvtd32,, 5, 1, 5,"fx","d")
 CDP2 (truncs32,, 5, 1, 6,"fx","f")
 CDP2 (truncd32,, 5, 1, 7,"fx","d")
 MCRC3 (rshl32, 5, 0, 0, 2, mvreg("fx", 16), mvreg("fx", 0), armreg(12))
 MCRC3 (rshl64, 5, 0, 0, 3, mvreg("dx", 16), mvreg("dx", 0), armreg(12))
 CDP2_imm7 (sh32, 5, 0,"fx","fx")
 CDP2_imm7 (sh64, 5, 2,"dx","dx")
 MCRC3 (cmps, 4, 0, 1, 4, armreg(12), mvreg("f", 16), mvreg("f", 0))
 MCRC3 (cmpd, 4, 0, 1, 5, armreg(12), mvreg("d", 16), mvreg("d", 0))
 MCRC3 (cmp32, 5, 0, 1, 4, armreg(12), mvreg("fx", 16), mvreg("fx", 0))
 MCRC3 (cmp64, 5, 0, 1, 5, armreg(12), mvreg("dx", 16), mvreg("dx", 0))
 CDP2f (abs, 3, 0)
 CDP2d (abs, 3, 1)
 CDP2f (neg, 3, 2)
 CDP2d (neg, 3, 3)
 CDP3f (add, 3, 4)
 CDP3d (add, 3, 5)
 CDP3f (sub, 3, 6)
 CDP3d (sub, 3, 7)
 CDP3f (mul, 1, 0)
 CDP3d (mul, 1, 1)
 CDP2fx (abs, 3, 0)
 CDP2dx (abs, 3, 1)
 CDP2fx (neg, 3, 2)
 CDP2dx (neg, 3, 3)
 CDP3fx (add, 3, 4)
 CDP3dx (add, 3, 5)
 CDP3fx (sub, 3, 6)
 CDP3dx (sub, 3, 7)
 CDP3fx (mul, 1, 0)
 CDP3dx (mul, 1, 1)
 CDP3fx (mac, 1, 2)
 CDP3fx (msc, 1, 3)
 CDP41A (madd32, 0)
 CDP41A (msub32, 1)
 CDP42A (madda32, 2)
 CDP42A (msuba32, 3)
int main (int argc, char *argv[])

Variables

char * arm_regs []
funcload_store_insns []
funcmove_insns []
funcconv_insns []
funcshift_insns []
funccomp_insns []
funcfp_arith_insns []
funcint_arith_insns []
funcacc_arith_insns []
group_t groups []

Define Documentation

#define acreg (   shift)    reg_p ("mvax", shift, mk_get_bits (2u))

Definition at line 44 of file maverick.c.

#define arm_cond   { arm_cond }
#define armreg (   shift)    reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))

Definition at line 40 of file maverick.c.

#define CDP2 (   insname,
  var,
  cpnum,
  opcode1,
  opcode2,
  reg1name,
  reg2name 
)
Value:
mv_insn (insname##var, , \
          (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
          mvreg (reg1name, 12), comma, mvreg (reg2name, 16))

Definition at line 182 of file maverick.c.

#define CDP2_imm7 (   insname,
  cpnum,
  opcode1,
  reg1name,
  reg2name 
)
Value:
mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \
          mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
          tick_random)

Definition at line 205 of file maverick.c.

#define CDP2d (   insname,
  opcode1,
  opcode2 
)    CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")

Definition at line 200 of file maverick.c.

#define CDP2dx (   insname,
  opcode1,
  opcode2 
)    CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")

Definition at line 192 of file maverick.c.

#define CDP2f (   insname,
  opcode1,
  opcode2 
)    CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")

Definition at line 196 of file maverick.c.

#define CDP2fx (   insname,
  opcode1,
  opcode2 
)    CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")

Definition at line 188 of file maverick.c.

#define CDP3 (   insname,
  var,
  cpnum,
  opcode1,
  opcode2,
  reg1name,
  reg2name,
  reg3name 
)
Value:
mv_insn (insname##var, , \
          (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
          mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
          mvreg (reg3name, 0), tick_random)

Definition at line 219 of file maverick.c.

#define CDP3d (   insname,
  opcode1,
  opcode2 
)    CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")

Definition at line 238 of file maverick.c.

#define CDP3dx (   insname,
  opcode1,
  opcode2 
)    CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")

Definition at line 230 of file maverick.c.

#define CDP3f (   insname,
  opcode1,
  opcode2 
)    CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")

Definition at line 234 of file maverick.c.

#define CDP3fx (   insname,
  opcode1,
  opcode2 
)    CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")

Definition at line 226 of file maverick.c.

#define CDP4 (   insname,
  opcode1,
  reg2spec,
  reg3name,
  reg4name 
)
Value:
mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \
          acreg (5), comma, reg2spec, comma, \
          mvreg (reg3name, 16), comma, mvreg (reg4name, 0))

Definition at line 243 of file maverick.c.

#define CDP41A (   insname,
  opcode1 
)    CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")

Definition at line 249 of file maverick.c.

#define CDP42A (   insname,
  opcode1 
)    CDP4 (insname, opcode1, acreg (12), "fx", "fx")

Definition at line 253 of file maverick.c.

#define CDPfp_insns (   insname)    insn (insname ## s), insn (insname ## d)

Definition at line 213 of file maverick.c.

#define CDPx_insns (   insname)    insn (insname ## 32), insn (insname ## 64)

Definition at line 215 of file maverick.c.

*< load_store\+0x4 > e4 *cfldrsmi *< load_store\+0x8 > ef *cfldrsvc *c< load_store\+0xc > bd ff *cfldrslt *< load_store\+0x10 > c4 *cfldrscc *< load_store\+0x14 > ed b9 d4 *cfldrs *< load_store\+0x18 > ff *cfldrscs *< load_store\+0x1c > *cfldrsls *< load_store\+0x20 > dd b9 *cfldrsle *< load_store\+0x24 > b4 ff *cfldrsvs *< load_store\+0x28 > c4 *cfldrscc *< load_store\+0x2c > ec b9 d4 *cfldrs *< load_store\+0x30 > ff *cfldrscs *< load_store\+0x34 > *cfldrsls *< load_store\+0x38 > dc b9 *cfldrsle *< load_store\+0x3c > b4 ff *cfldrdvs *< load_store\+0x40 > c4 *cfldrdcc *< load_store\+0x44 > ed d9 d4 *cfldrd *< load_store\+0x48 > ff *cfldrdcs *< load_store\+0x4c > *cfldrdls *< load_store\+0x50 > dd f9 *cfldrdle *< load_store\+0x54 > b4 ff *cfldrdvs *< load_store\+0x58 > c4 *cfldrdcc *< load_store\+0x5c > ed f9 d4 *cfldrd *< load_store\+0x60 > ff *cfldrdcs *< load_store\+0x64 > *cfldrdls *< load_store\+0x68 > dc f9 *cfldrdle *< load_store\+0x6c > b4 ff *cfldrdvs *< load_store\+0x70 > c4 *cfldrdcc *< load_store\+0x74 > ec f9 d4 *cfldrd *< load_store\+0x78 > ff *cfldr32cs *< load_store\+0x7c > *cfldr32ls *< load_store\+0x80 > dd *cfldr32le *< load_store\+0x84 > b5 ff *cfldr32vs *< load_store\+0x88 > c5 *cfldr32cc *< load_store\+0x8c > ed b9 d5 *cfldr32 *< load_store\+0x90 > ff *cfldr32cs *< load_store\+0x94 > *cfldr32ls *< load_store\+0x98 > dd b9 *cfldr32le *< load_store\+0x9c > b5 ff *cfldr32vs *a0< load_store\+0xa0 > c5 *cfldr32cc *a4< load_store\+0xa4 > ec b9 d5 *cfldr32 *a8< load_store\+0xa8 > ff *cfldr32cs *ac< load_store\+0xac > *cfldr32ls *b0< load_store\+0xb0 > dc b9 *cfldr32le *b4< load_store\+0xb4 > b5 ff *cfldr64vs *b8< load_store\+0xb8 > c5 *cfldr64cc *bc< load_store\+0xbc > ed d9 d5 *cfldr64 *c0< load_store\+0xc0 > ff *cfldr64cs *c4< load_store\+0xc4 > *cfldr64ls *c8< load_store\+0xc8 > dd f9 *cfldr64le *cc< load_store\+0xcc > b5 ff *cfldr64vs *d0< load_store\+0xd0 > c5 *cfldr64cc *d4< load_store\+0xd4 > ed f9 d5 *cfldr64 *d8< load_store\+0xd8 > ff *cfldr64cs *dc< load_store\+0xdc > *cfldr64ls *e0< load_store\+0xe0 > dc f9 *cfldr64le *e4< load_store\+0xe4 > b5 ff *cfldr64vs *e8< load_store\+0xe8 > c5 *cfldr64cc *ec< load_store\+0xec > ec f9 d5 *cfldr64 *f0< load_store\+0xf0 > ff *cfstrscs *f4< load_store\+0xf4 > *cfstrsls *f8< load_store\+0xf8 > dd *cfstrsle *fc< load_store\+0xfc > b4 ff *cfstrsvs *< load_store\+0x100 > c4 *cfstrscc *< load_store\+0x104 > ed a9 d4 *cfstrs *< load_store\+0x108 > ff *cfstrscs *< load_store\+0x10c > *cfstrsls *< load_store\+0x110 > dd a9 *cfstrsle *< load_store\+0x114 > b4 ff *cfstrsvs *< load_store\+0x118 > c4 *cfstrscc *< load_store\+0x11c > ec a9 d4 *cfstrs *< load_store\+0x120 > ff *cfstrscs *< load_store\+0x124 > *cfstrsls *< load_store\+0x128 > dc a9 *cfstrsle *< load_store\+0x12c > b4 ff *cfstrdvs *< load_store\+0x130 > c4 *cfstrdcc *< load_store\+0x134 > ed c9 d4 *cfstrd *< load_store\+0x138 > ff *cfstrdcs *< load_store\+0x13c > *cfstrdls *< load_store\+0x140 > dd e9 *cfstrdle *< load_store\+0x144 > b4 ff *cfstrdvs *< load_store\+0x148 > c4 *cfstrdcc *< load_store\+0x14c > ed e9 d4 *cfstrd *< load_store\+0x150 > ff *cfstrdcs *< load_store\+0x154 > *cfstrdls *< load_store\+0x158 > dc e9 *cfstrdle *< load_store\+0x15c > b4 ff *cfstrdvs *< load_store\+0x160 > c4 *cfstrdcc *< load_store\+0x164 > ec e9 d4 *cfstrd *< load_store\+0x168 > ff *cfstr32cs *< load_store\+0x16c > *cfstr32ls *< load_store\+0x170 > dd *cfstr32le *< load_store\+0x174 > b5 ff *cfstr32vs *< load_store\+0x178 > c5 *cfstr32cc *< load_store\+0x17c > ed a9 d5 *cfstr32 *< load_store\+0x180 > ff *cfstr32cs *< load_store\+0x184 > *cfstr32ls *< load_store\+0x188 > dd a9 *cfstr32le *< load_store\+0x18c > b5 ff *cfstr32vs *< load_store\+0x190 > c5 *cfstr32cc *< load_store\+0x194 > ec a9 d5 *cfstr32 *< load_store\+0x198 > ff *cfstr32cs *< load_store\+0x19c > *cfstr32ls *< load_store\+0x1a0 > dc a9 *cfstr32le *< load_store\+0x1a4 > b5 ff *cfstr64vs *< load_store\+0x1a8 > c5 *cfstr64cc *< load_store\+0x1ac > ed c9 d5 *cfstr64 *< load_store\+0x1b0 > ff *cfstr64cs *< load_store\+0x1b4 > *cfstr64ls *< load_store\+0x1b8 > dd e9 *cfstr64le *< load_store\+0x1bc > b5 ff *cfstr64vs *< load_store\+0x1c0 > c5 *cfstr64cc *< load_store\+0x1c4 > ed e9 d5 *cfstr64 *< load_store\+0x1c8 > ff *cfstr64cs *< load_store\+0x1cc > *cfstr64ls *< load_store\+0x1d0 > dc e9 *cfstr64le *< load_store\+0x1d4 > b5 ff *cfstr64vs *< load_store\+0x1d8 > c5 *cfstr64cc *< load_store\+0x1dc > ec e9 d5 *cfstr64 *< move > *cfmvsrcs r0 *< move\+0x4 > *cfmvsrpl r7 *< move\+0x8 > *cfmvsrls r1 *< move\+0xc > *cfmvsrcc r2 *< move\+0x10 > c4 *cfmvsrvc ip *< move\+0x14 > ce *cfmvrsgt mvf11 *< move\+0x18 > a4 *cfmvrseq mvf5 *< move\+0x1c > ee *cfmvrs mvf12 *< move\+0x20 > ae b4 *cfmvrsge mvf8 *< move\+0x24 > ee *cfmvrs mvf6 *< move\+0x28 > be *cfmvdlrlt r9 *< move\+0x2c > a4 *cfmvdlrls sl *< move\+0x30 > ee *cfmvdlr r4 *< move\+0x34 > b4 *cfmvdlrmi fp *< move\+0x38 > *cfmvdlrhi r5 *< move\+0x3c > c4 *cfmvrdlcs mvd12 *< move\+0x40 > *cfmvrdlvs mvd0 *< move\+0x44 > d4 *cfmvrdlvc mvd14 *< move\+0x48 > e4 *cfmvrdlcc mvd10 *< move\+0x4c > *cfmvrdlne mvd15 *< move\+0x50 > de c4 *cfmvdhrle ip *< move\+0x54 > *cfmvdhrmi r3 *< move\+0x58 > d4 *cfmvdhreq sp *< move\+0x5c > ae e4 *cfmvdhrge lr *< move\+0x60 > ee *cfmvdhr r8 *< move\+0x64 > de *cfmvrdhle mvd2 *< move\+0x68 > *cfmvrdhne mvd6 *< move\+0x6c > be *cfmvrdhlt mvd7 *< move\+0x70 > *cfmvrdhpl mvd3 *< move\+0x74 > ce *cfmvrdhgt mvd1 *< move\+0x78 > *cfmv64lrhi r5 *< move\+0x7c > *cfmv64lrvs r6 *< move\+0x80 > *cfmv64lrcs r0 *< move\+0x84 > *cfmv64lrpl r7 *< move\+0x88 > *cfmv64lrls r1 *< move\+0x8c > *cfmvr64lcc mvdx13 *< move\+0x90 > f5 *cfmvr64lvc mvdx1 *< move\+0x94 > ce *cfmvr64lgt mvdx11 *< move\+0x98 > a5 *cfmvr64leq mvdx5 *< move\+0x9c > ee *cfmvr64l mvdx12 *< move\+0xa0 > ae *cfmv64hrge r8 *< move\+0xa4 > ee f5 *cfmv64hr pc *< move\+0xa8 > be *cfmv64hrlt r9 *< move\+0xac > a5 *cfmv64hrls sl *< move\+0xb0 > ee *cfmv64hr r4 *< move\+0xb4 > *cfmvr64hmi mvdx3 *< move\+0xb8 > *cfmvr64hhi mvdx7 *< move\+0xbc > c5 *cfmvr64hcs mvdx12 *< move\+0xc0 > *cfmvr64hvs mvdx0 *< move\+0xc4 > d5 *cfmvr64hvc mvdx14 *< move\+0xc8 > *cfmval32cc mvfx10 *< move\+0xcc > *cfmval32ne mvfx15 *< move\+0xd0 > de *cfmval32le mvfx11 *< move\+0xd4 > *cfmval32mi mvfx9 *< move\+0xd8 > *cfmval32eq mvfx15 *< move\+0xdc > ae *cfmv32alge mvax0 *< move\+0xe0 > ee *cfmv32al mvax1 *< move\+0xe4 > de *cfmv32alle mvax0 *< move\+0xe8 > c4 *cfmv32alne mvax0 *< move\+0xec > be *cfmv32allt mvax1 *< move\+0xf0 > *cfmvam32pl mvfx3 *< move\+0xf4 > ce *cfmvam32gt mvfx1 *< move\+0xf8 > *cfmvam32hi mvfx13 *< move\+0xfc > *cfmvam32vs mvfx4 *< move\+0x100 > *cfmvam32cs mvfx0 *< move\+0x104 > f4 *cfmv32ampl mvax2 *< move\+0x108 > *cfmv32amls mvax1 *< move\+0x10c > *cfmv32amcc mvax3 *< move\+0x110 > *cfmv32amvc mvax3 *< move\+0x114 > ce *cfmv32amgt mvax1 *< move\+0x118 > *cfmvah32eq mvfx5 *< move\+0x11c > ee *cfmvah32 mvfx12 *< move\+0x120 > ae *cfmvah32ge mvfx8 *< move\+0x124 > ee *cfmvah32 mvfx6 *< move\+0x128 > be *cfmvah32lt mvfx2 *< move\+0x12c > *cfmv32ahls mvax1 *< move\+0x130 > ee a4 *cfmv32ah mvax2 *< move\+0x134 > e4 *cfmv32ahmi mvax3 *< move\+0x138 > d4 *cfmv32ahhi mvax2 *< move\+0x13c > *cfmv32ahcs mvax2 *< move\+0x140 > a0 *cfmva32vs mvfx0 *< move\+0x144 > a0 *cfmva32vc mvfx14 *< move\+0x148 > a0 *cfmva32cc mvfx10 *< move\+0x14c > a0 *cfmva32ne mvfx15 *< move\+0x150 > de a0 *cfmva32le mvfx11 *< move\+0x154 > a0 *cfmv32ami mvax1 *< move\+0x158 > a0 *cfmv32aeq mvax3 *< move\+0x15c > ae a0 *cfmv32age mvax0 *< move\+0x160 > ee a0 *cfmv32a mvax1 *< move\+0x164 > de a0 *cfmv32ale mvax0 *< move\+0x168 > c0 *cfmva64ne mvdx6 *< move\+0x16c > be c0 *cfmva64lt mvdx7 *< move\+0x170 > c0 *cfmva64pl mvdx3 *< move\+0x174 > ce c0 *cfmva64gt mvdx1 *< move\+0x178 > c0 *cfmva64hi mvdx13 *< move\+0x17c > b4 c0 *cfmv64avs mvax2 *< move\+0x180 > c0 *cfmv64acs mvax0 *< move\+0x184 > f4 c0 *cfmv64apl mvax2 *< move\+0x188 > c0 *cfmv64als mvax1 *< move\+0x18c > c0 *cfmv64acc mvax3 *< move\+0x190 > e0 *cfmvsc32vc mvdx1 *< move\+0x194 > ce b4 e0 *cfmvsc32gt mvdx11 *< move\+0x198 > e0 *cfmvsc32eq mvdx5 *< move\+0x19c > ee c4 e0 *cfmvsc32 mvdx12 *< move\+0x1a0 > ae e0 *cfmvsc32ge dspsc   literal ("dspsc"), tick_random

Definition at line 46 of file maverick.c.

#define imm7   { imm7 }
#define insns_LDSTall (   insname)    insn (insname ## _p), insn (insname ## _pw), insn (insname)

Definition at line 176 of file maverick.c.

#define insns_MV (   name1,
  name2 
)    insn (mv ## name1), insn (mv ## name2)

Definition at line 325 of file maverick.c.

#define LDST (   insname,
  insnvar,
  op,
  ld,
  dword,
  regname,
  pre,
  wb,
  sep1,
  sep2,
  sep3 
)
Value:
mv_insn (insname, insnvar, \
          (12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \
           mvreg (regname, 12), comma, \
           lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \
           tick_random)

Definition at line 159 of file maverick.c.

#define LDSTall (   insname,
  op,
  ld,
  dword,
  regname 
)
Value:
LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
  LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \
  LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing)

Definition at line 169 of file maverick.c.

#define MCC2 (   insname,
  opcode1,
  opcode2,
  reg1spec,
  reg2spec 
)
Value:
mv_insn (insname, , \
          ((14 << 24) | ((opcode1) << 20) | \
           (4 << 8) | ((opcode2) << 5)), \
          reg1spec, comma, reg2spec)

Definition at line 274 of file maverick.c.

#define MCRC2 (   insname,
  cpnum,
  opcode1,
  dir,
  opcode2,
  reg1spec,
  reg2spec 
)
Value:
mv_insn (insname, , \
          ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
           ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
          reg1spec, comma, reg2spec)

Definition at line 257 of file maverick.c.

#define MCRC3 (   insname,
  cpnum,
  opcode1,
  dir,
  opcode2,
  reg1spec,
  reg2spec,
  reg3spec 
)
Value:
mv_insn (insname, , \
          ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
           ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
          reg1spec, comma, reg2spec, comma, reg3spec, \
          tick_random)

Definition at line 329 of file maverick.c.

#define mv_insn (   insname,
  insnvar,
  word,
  funcs... 
)
Value:
define_insn (insname ## insnvar, \
             literal ("cf"), \
             insn_bits (insname, word), \
             arm_cond, \
             tab, \
             ## funcs)

Definition at line 143 of file maverick.c.

#define MVACCDSP (   insname,
  opcode2,
  regDSPname 
)    MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))

Definition at line 285 of file maverick.c.

#define MVARMDSP (   insname,
  cpnum,
  opcode2,
  regDSPname 
)
Value:
MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
        armreg (12), mvreg (regDSPname, 16))

Definition at line 269 of file maverick.c.

#define MVd (   nameAD,
  nameDA,
  opcode2 
)
Value:
MVDSPARM (nameAD, 4, opcode2, "d"); \
  MVARMDSP (nameDA, 4, opcode2, "d")

Definition at line 296 of file maverick.c.

#define MVDSPACC (   insname,
  opcode2,
  regDSPname 
)    MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))

Definition at line 281 of file maverick.c.

#define MVDSPARM (   insname,
  cpnum,
  opcode2,
  regDSPname 
)
Value:
MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
        mvreg (regDSPname, 16), armreg (12))

Definition at line 264 of file maverick.c.

#define MVdx (   nameAD,
  nameDA,
  opcode2 
)
Value:
MVDSPARM (nameAD, 5, opcode2, "dx"); \
  MVARMDSP (nameDA, 5, opcode2, "dx")

Definition at line 308 of file maverick.c.

#define MVdxa (   nameDA,
  nameAD,
  opcode2 
)
Value:
MVDSPACC (nameDA, opcode2, "dx"); \
  MVACCDSP (nameAD, opcode2, "dx")

Definition at line 320 of file maverick.c.

#define MVf (   nameAD,
  nameDA,
  opcode2 
)
Value:
MVDSPARM (nameAD, 4, opcode2, "f"); \
  MVARMDSP (nameDA, 4, opcode2, "f")

Definition at line 290 of file maverick.c.

#define MVfx (   nameAD,
  nameDA,
  opcode2 
)
Value:
MVDSPARM (nameAD, 5, opcode2, "fx"); \
  MVARMDSP (nameDA, 5, opcode2, "fx")

Definition at line 302 of file maverick.c.

#define MVfxa (   nameFA,
  nameAF,
  opcode2 
)
Value:
MVDSPACC (nameFA, opcode2, "fx"); \
  MVACCDSP (nameAF, opcode2, "fx")

Definition at line 314 of file maverick.c.

#define mvreg (   prefix,
  shift 
)    reg_p ("mv" prefix, shift, mk_get_bits (4u))

Definition at line 42 of file maverick.c.

#define off8s   { off8s }

Function Documentation

int arm_cond ( func_arg arg,
insn_data data 
)

Definition at line 57 of file maverick.c.

                 { arm_cond }
{
  static const char conds[16][3] =
    {
      "eq", "ne", "cs", "cc",
      "mi", "pl", "vs", "vc",
      "hi", "ls", "ge", "lt",
      "gt", "le", "al", ""
    };
  unsigned val = get_bits (4u);

  data->as_in = data->dis_out = strdup (conds[val]);
  if (val == 14)
    data->dis_out = strdup ("");
  data->bits = (val == 15 ? 14 : val) << 28;
  return 0;
}

Here is the call graph for this function:

CDP2 ( cpys  ,
,
,
,
"f"  ,
"f"   
)
CDP2 ( cpyd  ,
,
,
,
"d"  ,
"d"   
)
CDP2 ( cvtsd  ,
,
,
,
"d"  ,
"f"   
)
CDP2 ( cvtds  ,
,
,
,
"f"  ,
"d"   
)
CDP2 ( cvt32s  ,
,
,
,
"f"  ,
"fx"   
)
CDP2 ( cvt32d  ,
,
,
,
"d"  ,
"fx"   
)
CDP2 ( cvt64s  ,
,
,
,
"f"  ,
"dx"   
)
CDP2 ( cvt64d  ,
,
,
,
"d"  ,
"dx"   
)
CDP2 ( cvts32  ,
,
,
,
"fx"  ,
"f"   
)
CDP2 ( cvtd32  ,
,
,
,
"fx"  ,
"d"   
)
CDP2 ( truncs32  ,
,
,
,
"fx"  ,
"f"   
)
CDP2 ( truncd32  ,
,
,
,
"fx"  ,
"d"   
)
CDP2_imm7 ( sh32  ,
,
,
"fx"  ,
"fx"   
)
CDP2_imm7 ( sh64  ,
,
,
"dx"  ,
"dx"   
)
CDP2d ( abs  ,
,
 
)
CDP2d ( neg  ,
,
 
)
CDP2dx ( abs  ,
,
 
)
CDP2dx ( neg  ,
,
 
)
CDP2f ( abs  ,
,
 
)
CDP2f ( neg  ,
,
 
)
CDP2fx ( abs  ,
,
 
)
CDP2fx ( neg  ,
,
 
)
CDP3d ( add  ,
,
 
)
CDP3d ( sub  ,
,
 
)
CDP3d ( mul  ,
,
 
)
CDP3dx ( add  ,
,
 
)
CDP3dx ( sub  ,
,
 
)
CDP3dx ( mul  ,
,
 
)
CDP3f ( add  ,
,
 
)
CDP3f ( sub  ,
,
 
)
CDP3f ( mul  ,
,
 
)
CDP3fx ( add  ,
,
 
)
CDP3fx ( sub  ,
,
 
)
CDP3fx ( mul  ,
,
 
)
CDP3fx ( mac  ,
,
 
)
CDP3fx ( msc  ,
,
 
)
CDP41A ( madd32  ,
 
)
CDP41A ( msub32  ,
 
)
CDP42A ( madda32  ,
 
)
CDP42A ( msuba32  ,
 
)
int imm7 ( func_arg arg,
insn_data data 
)

Definition at line 123 of file maverick.c.

             { imm7 }
{
  int val = get_bits (7s);
  char value[6];

  data->bits = (val & 0x0f) | (2 * (val & 0x70));
  sprintf (value, "#%i", val);
  data->as_in = data->dis_out = strdup (value);
  return 0;
}

Here is the call graph for this function:

LDSTall ( ldrs  ,
,
,
,
"f"   
)
LDSTall ( ldrd  ,
,
,
,
"d"   
)
LDSTall ( ldr32  ,
,
,
,
"fx"   
)
LDSTall ( ldr64  ,
,
,
,
"dx"   
)
LDSTall ( strs  ,
,
,
,
"f"   
)
LDSTall ( strd  ,
,
,
,
"d"   
)
LDSTall ( str32  ,
,
,
,
"fx"   
)
LDSTall ( str64  ,
,
,
,
"dx"   
)
int main ( int  argc,
char *  argv[] 
)

Definition at line 504 of file maverick.c.

{
  FILE *as_in = stdout, *dis_out = stderr;

  /* Check whether we're filtering insns.  */
  if (argc > 1)
    skip_list = argv + 1;

  /* Output assembler header.  */
  fputs ("\t.text\n"
        "\t.align\n",
        as_in);
  /* Output comments for the testsuite-driver and the initial
     disassembler output.  */
  fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
        "#name: Maverick\n"
        "#as: -mcpu=ep9312\n"
        "\n"
        "# Test the instructions of the Cirrus Maverick floating point co-processor\n"
        "\n"
        ".*: +file format.*arm.*\n"
        "\n"
        "Disassembly of section .text:\n",
        dis_out);

  /* Now emit all (selected) insns.  */
  output_groups (groups, as_in, dis_out);

  exit (0);
}

Here is the call graph for this function:

MCC2 ( mvsc32  ,
,
,
dspsc  ,
mvreg("dx", 12)   
)
MCC2 ( mv32sc  ,
,
,
mvreg("dx", 12)  ,
dspsc   
)
MCRC3 ( rshl32  ,
,
,
,
,
mvreg("fx", 16)  ,
mvreg("fx", 0)  ,
armreg(12)   
)
MCRC3 ( rshl64  ,
,
,
,
,
mvreg("dx", 16)  ,
mvreg("dx", 0)  ,
armreg(12)   
)
MCRC3 ( cmps  ,
,
,
,
,
armreg(12)  ,
mvreg("f", 16)  ,
mvreg("f", 0)   
)
MCRC3 ( cmpd  ,
,
,
,
,
armreg(12)  ,
mvreg("d", 16)  ,
mvreg("d", 0)   
)
MCRC3 ( cmp32  ,
,
,
,
,
armreg(12)  ,
mvreg("fx", 16)  ,
mvreg("fx", 0)   
)
MCRC3 ( cmp64  ,
,
,
,
,
armreg(12)  ,
mvreg("dx", 16)  ,
mvreg("dx", 0)   
)
MVd ( dlr  ,
rdl  ,
 
)
MVd ( dhr  ,
rdh  ,
 
)
MVdx ( 64lr  ,
r64l  ,
 
)
MVdx ( 64hr  ,
r64h  ,
 
)
MVdxa ( a64  ,
64a  ,
 
)
MVf ( sr  ,
rs  ,
 
)
MVfxa ( al32  ,
32al  ,
 
)
MVfxa ( am32  ,
32am  ,
 
)
MVfxa ( ah32  ,
32ah  ,
 
)
MVfxa ( a32  ,
32a  ,
 
)
int off8s ( func_arg arg,
insn_data data 
)

Definition at line 81 of file maverick.c.

              { off8s }
{
  int val;
  char value[9];

  /* Zero values are problematical.
     The assembler performs translations on the addressing modes
     for these values, meaning that we cannot just recreate the
     disassembler string in the LDST macro without knowing what
     value had been generated in off8s.  */
  do
    {
      val  = get_bits (9s);
    }
  while (val == -1 || val == 0);
  
  val <<= 2;
  if (val < 0)
    {
      val = -4 - val;
      sprintf (value, ", #-%i", val);
      data->dis_out = strdup (value);
      sprintf (value, ", #-%i", val);
      data->as_in = strdup (value);
      data->bits = val >> 2;
    }
  else
    {
      sprintf (value, ", #%i", val);
      data->as_in = data->dis_out = strdup (value);
      data->bits = (val >> 2) | (1 << 23);
    }
  
  return 0;
}

Here is the call graph for this function:


Variable Documentation

Initial value:
  {
    insn (madd32), insn (msub32),
    insn (madda32), insn (msuba32),
    0
  }

Definition at line 482 of file maverick.c.

char* arm_regs[]
Initial value:
  {
    
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
    
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
  }

Definition at line 26 of file maverick.c.

Initial value:
  {
    insn (cmps), insn (cmpd),
    insn (cmp32), insn (cmp64),
    0
  }

Definition at line 425 of file maverick.c.

Initial value:
  {
    insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
    insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
    insn (truncs32), insn (truncd32),
    0
  }

Definition at line 396 of file maverick.c.

Initial value:

Definition at line 445 of file maverick.c.

Initial value:
  {
    { "load_store", load_store_insns },
    { "move", move_insns },
    { "conv", conv_insns },
    { "shift", shift_insns },
    { "comp", comp_insns },
    { "fp_arith", fp_arith_insns },
    { "int_arith", int_arith_insns },
    { "acc_arith", acc_arith_insns },
    { 0 }
  }

Definition at line 490 of file maverick.c.

Initial value:
  {
    CDPx_insns (abs), CDPx_insns (neg),
    CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
    insn (mac32), insn (msc32),
    0
  }

Definition at line 467 of file maverick.c.

Initial value:
  {
    insns_LDSTall (ldrs),  insns_LDSTall (ldrd),
    insns_LDSTall (ldr32), insns_LDSTall (ldr64),
    insns_LDSTall (strs),  insns_LDSTall (strd),
    insns_LDSTall (str32), insns_LDSTall (str64),
    0
  }

Definition at line 347 of file maverick.c.

Initial value:
  {
    insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
    insns_MV (64lr, r64l), insns_MV (64hr, r64h),
    insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
    insns_MV (a32, 32a), insns_MV (a64, 64a),
    insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
    0
  }

Definition at line 373 of file maverick.c.

Initial value:
  {
    insn (rshl32), insn (rshl64),
    insn (sh32), insn (sh64),
    0
  }

Definition at line 411 of file maverick.c.