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cell-binutils  2.17cvs20070401
m68k-parse.h
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00001 /* m68k-parse.h -- header file for m68k assembler
00002    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
00003    2003, 2004, 2005 Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with GAS; see the file COPYING.  If not, write to the Free
00019    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00020    02110-1301, USA.  */
00021 
00022 #ifndef M68K_PARSE_H
00023 #define M68K_PARSE_H
00024 
00025 /* This header file defines things which are shared between the
00026    operand parser in m68k.y and the m68k assembler proper in
00027    tc-m68k.c.  */
00028 
00029 /* The various m68k registers.  */
00030 
00031 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
00032    0-7==data reg, 8-15==addr reg for operands that take both types.
00033 
00034    We don't use forms like "ADDR0 = ADDR" here because this file is
00035    likely to be used on an Apollo, and the broken Apollo compiler
00036    gives an `undefined variable' error if we do that, according to
00037    troy@cbme.unsw.edu.au.  */
00038 
00039 #define DATA DATA0
00040 #define ADDR ADDR0
00041 #define SP ADDR7
00042 #define BAD BAD0
00043 #define BAC BAC0
00044 
00045 enum m68k_register
00046 {
00047   DATA0 = 1,                /*   1- 8 == data registers 0-7 */
00048   DATA1,
00049   DATA2,
00050   DATA3,
00051   DATA4,
00052   DATA5,
00053   DATA6,
00054   DATA7,
00055 
00056   ADDR0,
00057   ADDR1,
00058   ADDR2,
00059   ADDR3,
00060   ADDR4,
00061   ADDR5,
00062   ADDR6,
00063   ADDR7,
00064 
00065   FP0,                      /* Eight FP registers */
00066   FP1,
00067   FP2,
00068   FP3,
00069   FP4,
00070   FP5,
00071   FP6,
00072   FP7,
00073 
00074   COP0,                            /* Co-processor #0-#7 */
00075   COP1,
00076   COP2,
00077   COP3,
00078   COP4,
00079   COP5,
00080   COP6,
00081   COP7,
00082 
00083   PC,                       /* Program counter */
00084   ZPC,                      /* Hack for Program space, but 0 addressing */
00085   SR,                       /* Status Reg */
00086   CCR,                      /* Condition code Reg */
00087   ACC,                      /* Accumulator Reg0 (EMAC or ACC on MAC).  */
00088   ACC1,                            /* Accumulator Reg 1 (EMAC).  */
00089   ACC2,                            /* Accumulator Reg 2 (EMAC).  */
00090   ACC3,                            /* Accumulator Reg 3 (EMAC).  */
00091   ACCEXT01,                 /* Accumulator extension 0&1 (EMAC).  */
00092   ACCEXT23,                 /* Accumulator extension 2&3 (EMAC).  */
00093   MACSR,                    /* MAC Status Reg */
00094   MASK,                            /* Modulus Reg */
00095 
00096   /* These have to be grouped together for the movec instruction to work.  */
00097   USP,                      /*  User Stack Pointer */
00098   ISP,                      /*  Interrupt stack pointer */
00099   SFC,
00100   DFC,
00101   CACR,
00102   VBR,
00103   CAAR,
00104   MSP,
00105   ITT0,
00106   ITT1,
00107   DTT0,
00108   DTT1,
00109   MMUSR,
00110   TC,
00111   SRP,
00112   URP,
00113   BUSCR,                    /* 68060 added these.  */
00114   PCR,
00115   ROMBAR,                   /* mcf5200 added these.  */
00116   RAMBAR0,
00117   RAMBAR1,
00118   MMUBAR,                   /* mcfv4e added these.  */
00119   ROMBAR0,                  /* mcfv4e added these.  */
00120   ROMBAR1,                  /* mcfv4e added these.  */
00121   MPCR, EDRAMBAR, SECMBAR,  /* mcfv4e added these.  */
00122   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
00123   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
00124   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
00125   MBAR0, MBAR1,                    /* mcfv4e added these.  */
00126   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
00127   FLASHBAR, RAMBAR,                /* mcf528x added these.  */
00128   MBAR2,                     /* mcf5249 added this.  */
00129   MBAR,
00130   ASID,                            /* m5475.  */
00131   CAC,                       /* fido added this.  */
00132   MBB,
00133 #define last_movec_reg MBB
00134   /* End of movec ordering constraints.  */
00135 
00136   FPI,
00137   FPS,
00138   FPC,
00139 
00140   DRP,                      /* 68851 or 68030 MMU regs */
00141   CRP,
00142   CAL,
00143   VAL,
00144   SCC,
00145   AC,
00146   BAD0,
00147   BAD1,
00148   BAD2,
00149   BAD3,
00150   BAD4,
00151   BAD5,
00152   BAD6,
00153   BAD7,
00154   BAC0,
00155   BAC1,
00156   BAC2,
00157   BAC3,
00158   BAC4,
00159   BAC5,
00160   BAC6,
00161   BAC7,
00162   PSR,                      /* aka MMUSR on 68030 (but not MMUSR on 68040)
00163                                and ACUSR on 68ec030 */
00164   PCSR,
00165 
00166   IC,                       /* instruction cache token */
00167   DC,                       /* data cache token */
00168   NC,                       /* no cache token */
00169   BC,                       /* both caches token */
00170 
00171   TT0,                      /* 68030 access control unit regs */
00172   TT1,
00173 
00174   ZDATA0,                   /* suppressed data registers.  */
00175   ZDATA1,
00176   ZDATA2,
00177   ZDATA3,
00178   ZDATA4,
00179   ZDATA5,
00180   ZDATA6,
00181   ZDATA7,
00182 
00183   ZADDR0,                   /* suppressed address registers.  */
00184   ZADDR1,
00185   ZADDR2,
00186   ZADDR3,
00187   ZADDR4,
00188   ZADDR5,
00189   ZADDR6,
00190   ZADDR7,
00191 
00192   /* Upper and lower half of data and address registers.  Order *must*
00193      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
00194   DATA0L,                   /* lower half of data registers */
00195   DATA1L,
00196   DATA2L,
00197   DATA3L,
00198   DATA4L,
00199   DATA5L,
00200   DATA6L,
00201   DATA7L,
00202 
00203   ADDR0L,                   /* lower half of address registers */
00204   ADDR1L,
00205   ADDR2L,
00206   ADDR3L,
00207   ADDR4L,
00208   ADDR5L,
00209   ADDR6L,
00210   ADDR7L,
00211 
00212   DATA0U,                   /* upper half of data registers */
00213   DATA1U,
00214   DATA2U,
00215   DATA3U,
00216   DATA4U,
00217   DATA5U,
00218   DATA6U,
00219   DATA7U,
00220 
00221   ADDR0U,                   /* upper half of address registers */
00222   ADDR1U,
00223   ADDR2U,
00224   ADDR3U,
00225   ADDR4U,
00226   ADDR5U,
00227   ADDR6U,
00228   ADDR7U,
00229 };
00230 
00231 /* Size information.  */
00232 
00233 enum m68k_size
00234 {
00235   /* Unspecified.  */
00236   SIZE_UNSPEC,
00237 
00238   /* Byte.  */
00239   SIZE_BYTE,
00240 
00241   /* Word (2 bytes).  */
00242   SIZE_WORD,
00243 
00244   /* Longword (4 bytes).  */
00245   SIZE_LONG
00246 };
00247 
00248 /* The structure used to hold information about an index register.  */
00249 
00250 struct m68k_indexreg
00251 {
00252   /* The index register itself.  */
00253   enum m68k_register reg;
00254 
00255   /* The size to use.  */
00256   enum m68k_size size;
00257 
00258   /* The value to scale by.  */
00259   int scale;
00260 };
00261 
00262 #ifdef OBJ_ELF
00263 /* The type of a PIC expression.  */
00264 
00265 enum pic_relocation
00266 {
00267   pic_none,                 /* not pic */
00268   pic_plt_pcrel,            /* @PLTPC */
00269   pic_got_pcrel,            /* @GOTPC */
00270   pic_plt_off,                     /* @PLT */
00271   pic_got_off               /* @GOT */
00272 };
00273 #endif
00274 
00275 /* The structure used to hold information about an expression.  */
00276 
00277 struct m68k_exp
00278 {
00279   /* The size to use.  */
00280   enum m68k_size size;
00281 
00282 #ifdef OBJ_ELF
00283   /* The type of pic relocation if any.  */
00284   enum pic_relocation pic_reloc;
00285 #endif
00286 
00287   /* The expression itself.  */
00288   expressionS exp;
00289 };
00290 
00291 /* The operand modes.  */
00292 
00293 enum m68k_operand_type
00294 {
00295   IMMED = 1,
00296   ABSL,
00297   DREG,
00298   AREG,
00299   FPREG,
00300   CONTROL,
00301   AINDR,
00302   AINC,
00303   ADEC,
00304   DISP,
00305   BASE,
00306   POST,
00307   PRE,
00308   LSH,  /* MAC/EMAC scalefactor '<<'.  */
00309   RSH,  /* MAC/EMAC scalefactor '>>'.  */
00310   REGLST
00311 };
00312 
00313 /* The structure used to hold a parsed operand.  */
00314 
00315 struct m68k_op
00316 {
00317   /* The type of operand.  */
00318   enum m68k_operand_type mode;
00319 
00320   /* The main register.  */
00321   enum m68k_register reg;
00322 
00323   /* The register mask for mode REGLST.  */
00324   unsigned long mask;
00325 
00326   /* An error message.  */
00327   const char *error;
00328 
00329   /* The index register.  */
00330   struct m68k_indexreg index;
00331 
00332   /* The displacement.  */
00333   struct m68k_exp disp;
00334 
00335   /* The outer displacement.  */
00336   struct m68k_exp odisp;
00337 
00338   /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
00339   int trailing_ampersand;
00340 };
00341 
00342 #endif /* ! defined (M68K_PARSE_H) */
00343 
00344 /* The parsing function.  */
00345 
00346 extern int m68k_ip_op (char *, struct m68k_op *);
00347 
00348 /* Whether register prefixes are optional.  */
00349 extern int flag_reg_prefix_optional;