Back to index

cell-binutils  2.17cvs20070401
m32rx.d
Go to the documentation of this file.
00001 #as: -m32rx --no-warn-explicit-parallel-conflicts --hidden -O
00002 #objdump: -dr
00003 #name: m32rx
00004 
00005 .*: +file format .*
00006 
00007 Disassembly of section .text:
00008 
00009 0+0000 <bcl>:
00010    0:  78 00 f0 00   bcl 0 <bcl> \|\| nop
00011 
00012 0+0004 <bncl>:
00013    4:  79 ff f0 00   bncl 0 <bcl> \|\| nop
00014 
00015 0+0008 <cmpz>:
00016    8:  00 7d f0 00   cmpz fp \|\| nop
00017 
00018 0+000c <cmpeq>:
00019    c:  0d 6d f0 00   cmpeq fp,fp \|\| nop
00020 
00021 0+0010 <maclh1>:
00022   10:  5d cd f0 00   maclh1 fp,fp \|\| nop
00023 
00024 0+0014 <msblo>:
00025   14:  5d dd f0 00   msblo fp,fp \|\| nop
00026 
00027 0+0018 <mulwu1>:
00028   18:  5d ad f0 00   mulwu1 fp,fp \|\| nop
00029 
00030 0+001c <macwu1>:
00031   1c:  5d bd f0 00   macwu1 fp,fp \|\| nop
00032 
00033 0+0020 <sadd>:
00034   20:  50 e4 f0 00   sadd \|\| nop
00035 
00036 0+0024 <satb>:
00037   24:  8d 6d 03 00   satb fp,fp
00038 
00039 0+0028 <mulhi>:
00040   28:  3d 8d f0 00   mulhi fp,fp,a1 \|\| nop
00041 
00042 0+002c <mullo>:
00043   2c:  3d 1d f0 00   mullo fp,fp \|\| nop
00044 
00045 0+0030 <divh>:
00046   30:  9d 0d 00 10   divh fp,fp
00047 
00048 0+0034 <machi>:
00049   34:  3d cd f0 00   machi fp,fp,a1 \|\| nop
00050 
00051 0+0038 <maclo>:
00052   38:  3d 5d f0 00   maclo fp,fp \|\| nop
00053 
00054 0+003c <mvfachi>:
00055   3c:  5d f4 f0 00   mvfachi fp,a1 \|\| nop
00056 
00057 0+0040 <mvfacmi>:
00058   40:  5d f6 f0 00   mvfacmi fp,a1 \|\| nop
00059 
00060 0+0044 <mvfaclo>:
00061   44:  5d f5 f0 00   mvfaclo fp,a1 \|\| nop
00062 
00063 0+0048 <mvtachi>:
00064   48:  5d 74 f0 00   mvtachi fp,a1 \|\| nop
00065 
00066 0+004c <mvtaclo>:
00067   4c:  5d 71 f0 00   mvtaclo fp \|\| nop
00068 
00069 0+0050 <rac>:
00070   50:  54 90 f0 00   rac a1 \|\| nop
00071 
00072 0+0054 <rac_ds>:
00073   54:  54 90 f0 00   rac a1 \|\| nop
00074 
00075 0+0058 <rac_dsi>:
00076   58:  50 94 f0 00   rac a0,a1 \|\| nop
00077 
00078 0+005c <rach>:
00079   5c:  54 80 f0 00   rach a1 \|\| nop
00080 
00081 0+0060 <rach_ds>:
00082   60:  50 84 f0 00   rach a0,a1 \|\| nop
00083 
00084 0+0064 <rach_dsi>:
00085   64:  54 81 f0 00   rach a1,a0,#0x2 \|\| nop
00086 
00087 0+0068 <bc__add>:
00088   68:  7c 00 8d ad   bc 68 <bc__add> \|\| add fp,fp
00089                      68: R_M32R_10_PCREL_RELA    bcl
00090   6c:  7c 00 0d ad   bc 6c <bc__add\+0x4> -> add fp,fp
00091                      6c: R_M32R_10_PCREL_RELA    bcl
00092 
00093 0+0070 <bcl__addi>:
00094   70:  78 00 cd 4d   bcl 70 <bcl__addi> \|\| addi fp,#77
00095                      70: R_M32R_10_PCREL_RELA    bcl
00096   74:  78 00 cd 4d   bcl 74 <bcl__addi\+0x4> \|\| addi fp,#77
00097                      74: R_M32R_10_PCREL_RELA    bcl
00098 
00099 0+0078 <bl__addv>:
00100   78:  7e 00 8d 8d   bl 78 <bl__addv> \|\| addv fp,fp
00101                      78: R_M32R_10_PCREL_RELA    bcl
00102   7c:  7e 00 8d 8d   bl 7c <bl__addv\+0x4> \|\| addv fp,fp
00103                      7c: R_M32R_10_PCREL_RELA    bcl
00104 
00105 0+0080 <bnc__addx>:
00106   80:  7d 00 8d 9d   bnc 80 <bnc__addx> \|\| addx fp,fp
00107                      80: R_M32R_10_PCREL_RELA    bcl
00108   84:  7d 00 0d 9d   bnc 84 <bnc__addx\+0x4> -> addx fp,fp
00109                      84: R_M32R_10_PCREL_RELA    bcl
00110 
00111 0+0088 <bncl__and>:
00112   88:  79 00 8d cd   bncl 88 <bncl__and> \|\| and fp,fp
00113                      88: R_M32R_10_PCREL_RELA    bcl
00114   8c:  79 00 8d cd   bncl 8c <bncl__and\+0x4> \|\| and fp,fp
00115                      8c: R_M32R_10_PCREL_RELA    bcl
00116 
00117 0+0090 <bra__cmp>:
00118   90:  7f 00 8d 4d   bra 90 <bra__cmp> \|\| cmp fp,fp
00119                      90: R_M32R_10_PCREL_RELA    bcl
00120   94:  7f 00 8d 4d   bra 94 <bra__cmp\+0x4> \|\| cmp fp,fp
00121                      94: R_M32R_10_PCREL_RELA    bcl
00122 
00123 0+0098 <jl__cmpeq>:
00124   98:  1e cd 8d 6d   jl fp \|\| cmpeq fp,fp
00125   9c:  1e cd 8d 6d   jl fp \|\| cmpeq fp,fp
00126 
00127 0+00a0 <jmp__cmpu>:
00128   a0:  1f cd 8d 5d   jmp fp \|\| cmpu fp,fp
00129   a4:  1f cd 8d 5d   jmp fp \|\| cmpu fp,fp
00130 
00131 0+00a8 <ld__cmpz>:
00132   a8:  2d cd 80 71   ld fp,@fp \|\| cmpz r1
00133   ac:  2d cd 80 71   ld fp,@fp \|\| cmpz r1
00134 
00135 0+00b0 <ld__ldi>:
00136   b0:  2d e1 e2 4d   ld fp,@r1\+ \|\| ldi r2,#77
00137   b4:  2d e1 e2 4d   ld fp,@r1\+ \|\| ldi r2,#77
00138 
00139 0+00b8 <ldb__mv>:
00140   b8:  2d 8d 92 8d   ldb fp,@fp \|\| mv r2,fp
00141   bc:  2d 8d 12 8d   ldb fp,@fp -> mv r2,fp
00142 
00143 0+00c0 <ldh__neg>:
00144   c0:  2d ad 82 3d   ldh fp,@fp \|\| neg r2,fp
00145   c4:  2d ad 02 3d   ldh fp,@fp -> neg r2,fp
00146 
00147 0+00c8 <ldub__nop>:
00148   c8:  2d 9d f0 00   ldub fp,@fp \|\| nop
00149   cc:  2d 9d f0 00   ldub fp,@fp \|\| nop
00150 
00151 0+00d0 <lduh__not>:
00152   d0:  2d bd 82 bd   lduh fp,@fp \|\| not r2,fp
00153   d4:  2d bd 02 bd   lduh fp,@fp -> not r2,fp
00154 
00155 0+00d8 <lock__or>:
00156   d8:  2d dd 82 ed   lock fp,@fp \|\| or r2,fp
00157   dc:  2d dd 02 ed   lock fp,@fp -> or r2,fp
00158 
00159 0+00e0 <mvfc__sub>:
00160   e0:  1d 91 82 2d   mvfc fp,cbr \|\| sub r2,fp
00161   e4:  1d 91 02 2d   mvfc fp,cbr -> sub r2,fp
00162 
00163 0+00e8 <mvtc__subv>:
00164   e8:  12 ad 82 0d   mvtc fp,spi \|\| subv r2,fp
00165   ec:  12 ad 82 0d   mvtc fp,spi \|\| subv r2,fp
00166 
00167 0+00f0 <rte__subx>:
00168   f0:  10 d6 82 2d   rte \|\| sub r2,fp
00169   f4:  10 d6 02 1d   rte -> subx r2,fp
00170 
00171 0+00f8 <sll__xor>:
00172   f8:  1d 41 82 dd   sll fp,r1 \|\| xor r2,fp
00173   fc:  1d 41 02 dd   sll fp,r1 -> xor r2,fp
00174 
00175 0+0100 <slli__machi>:
00176  100:  5d 56 b2 4d   slli fp,#0x16 \|\| machi r2,fp
00177  104:  5d 56 32 4d   slli fp,#0x16 -> machi r2,fp
00178 
00179 0+0108 <sra__maclh1>:
00180  108:  1d 2d d2 cd   sra fp,fp \|\| maclh1 r2,fp
00181  10c:  1d 2d 52 cd   sra fp,fp -> maclh1 r2,fp
00182 
00183 0+0110 <srai__maclo>:
00184  110:  5d 36 b2 5d   srai fp,#0x16 \|\| maclo r2,fp
00185  114:  5d 36 32 5d   srai fp,#0x16 -> maclo r2,fp
00186 
00187 0+0118 <srl__macwhi>:
00188  118:  1d 0d b2 6d   srl fp,fp \|\| macwhi r2,fp
00189  11c:  1d 0d 32 6d   srl fp,fp -> macwhi r2,fp
00190 
00191 0+0120 <srli__macwlo>:
00192  120:  5d 16 b2 7d   srli fp,#0x16 \|\| macwlo r2,fp
00193  124:  5d 16 32 7d   srli fp,#0x16 -> macwlo r2,fp
00194 
00195 0+0128 <st__macwu1>:
00196  128:  2d 4d d2 bd   st fp,@fp \|\| macwu1 r2,fp
00197  12c:  2d 4d d2 bd   st fp,@fp \|\| macwu1 r2,fp
00198 
00199 0+0130 <st__msblo>:
00200  130:  2d 6d d2 dd   st fp,@\+fp \|\| msblo r2,fp
00201  134:  2d 6d 52 dd   st fp,@\+fp -> msblo r2,fp
00202 
00203 0+0138 <st__mul>:
00204  138:  2d 7d 92 6d   st fp,@-fp \|\| mul r2,fp
00205  13c:  2d 7d 12 6d   st fp,@-fp -> mul r2,fp
00206 
00207 0+0140 <stb__mulhi>:
00208  140:  2d 0d b2 0d   stb fp,@fp \|\| mulhi r2,fp
00209  144:  2d 0d b2 0d   stb fp,@fp \|\| mulhi r2,fp
00210 
00211 0+0148 <sth__mullo>:
00212  148:  2d 2d b2 1d   sth fp,@fp \|\| mullo r2,fp
00213  14c:  2d 2d b2 1d   sth fp,@fp \|\| mullo r2,fp
00214 
00215 0+0150 <trap__mulwhi>:
00216  150:  10 f2 b2 2d   trap #0x2 \|\| mulwhi r2,fp
00217  154:  10 f2 f0 00   trap #0x2 \|\| nop
00218  158:  32 2d f0 00   mulwhi r2,fp \|\| nop
00219 
00220 0+015c <unlock__mulwlo>:
00221  15c:  2d 5d b2 3d   unlock fp,@fp \|\| mulwlo r2,fp
00222  160:  2d 5d b2 3d   unlock fp,@fp \|\| mulwlo r2,fp
00223 
00224 0+0164 <add__mulwu1>:
00225  164:  0d ad d2 ad   add fp,fp \|\| mulwu1 r2,fp
00226  168:  0d ad 52 ad   add fp,fp -> mulwu1 r2,fp
00227 
00228 0+016c <addi__mvfachi>:
00229  16c:  4d 4d d2 f0   addi fp,#77 \|\| mvfachi r2
00230  170:  4d 4d d2 f0   addi fp,#77 \|\| mvfachi r2
00231 
00232 0+0174 <addv__mvfaclo>:
00233  174:  0d 8d d2 f5   addv fp,fp \|\| mvfaclo r2,a1
00234  178:  0d 8d d2 f5   addv fp,fp \|\| mvfaclo r2,a1
00235 
00236 0+017c <addx__mvfacmi>:
00237  17c:  0d 9d d2 f2   addx fp,fp \|\| mvfacmi r2
00238  180:  0d 9d d2 f2   addx fp,fp \|\| mvfacmi r2
00239 
00240 0+0184 <and__mvtachi>:
00241  184:  0d cd d2 70   and fp,fp \|\| mvtachi r2
00242  188:  0d cd d2 70   and fp,fp \|\| mvtachi r2
00243 
00244 0+018c <cmp__mvtaclo>:
00245  18c:  0d 4d d2 71   cmp fp,fp \|\| mvtaclo r2
00246  190:  0d 4d d2 71   cmp fp,fp \|\| mvtaclo r2
00247 
00248 0+0194 <cmpeq__rac>:
00249  194:  0d 6d d4 90   cmpeq fp,fp \|\| rac a1
00250  198:  0d 6d d4 90   cmpeq fp,fp \|\| rac a1
00251 
00252 0+019c <cmpu__rach>:
00253  19c:  0d 5d d0 84   cmpu fp,fp \|\| rach a0,a1
00254  1a0:  0d 5d d4 84   cmpu fp,fp \|\| rach a1,a1
00255 
00256 0+01a4 <cmpz__sadd>:
00257  1a4:  00 7d d0 e4   cmpz fp \|\| sadd
00258  1a8:  00 7d d0 e4   cmpz fp \|\| sadd
00259 
00260 0+01ac <sc>:
00261  1ac:  74 01 d0 e4   sc \|\| sadd
00262 
00263 0+01b0 <snc>:
00264  1b0:  75 01 d0 e4   snc \|\| sadd
00265 
00266 0+01b4 <jc>:
00267  1b4:  1c cd f0 00   jc fp \|\| nop
00268 
00269 0+01b8 <jnc>:
00270  1b8:  1d cd f0 00   jnc fp \|\| nop
00271 
00272 0+01bc <pcmpbz>:
00273  1bc:  03 7d f0 00   pcmpbz fp \|\| nop
00274 
00275 0+01c0 <sat>:
00276  1c0:  8d 6d 00 00   sat fp,fp
00277 
00278 0+01c4 <sath>:
00279  1c4:  8d 6d 02 00   sath fp,fp
00280 
00281 0+01c8 <jc__pcmpbz>:
00282  1c8:  1c cd 83 7d   jc fp \|\| pcmpbz fp
00283  1cc:  1c cd 03 7d   jc fp -> pcmpbz fp
00284 
00285 0+01d0 <jnc__ldi>:
00286  1d0:  1d cd ed 4d   jnc fp \|\| ldi fp,#77
00287  1d4:  1d cd 6d 4d   jnc fp -> ldi fp,#77
00288 
00289 0+01d8 <sc__mv>:
00290  1d8:  74 01 9d 82   sc \|\| mv fp,r2
00291  1dc:  74 01 9d 82   sc \|\| mv fp,r2
00292 
00293 0+01e0 <snc__neg>:
00294  1e0:  75 01 8d 32   snc \|\| neg fp,r2
00295  1e4:  75 01 8d 32   snc \|\| neg fp,r2
00296 
00297 0+01e8 <nop__sadd>:
00298  1e8:  70 00 d0 e4   nop \|\| sadd
00299 
00300 0+01ec <sadd__nop>:
00301  1ec:  70 00 d0 e4   nop \|\| sadd
00302 
00303 0+01f0 <sadd__nop_reverse>:
00304  1f0:  70 00 d0 e4   nop \|\| sadd
00305 
00306 0+01f4 <add__not>:
00307  1f4:  00 a1 83 b5   add r0,r1 \|\| not r3,r5
00308 
00309 0+01f8 <add__not_dest_clash>:
00310  1f8:  03 a4 03 b5   add r3,r4 -> not r3,r5
00311 
00312 0+01fc <add__not__src_clash>:
00313  1fc:  03 a4 05 b3   add r3,r4 -> not r5,r3
00314 
00315 0+0200 <add__not__no_clash>:
00316  200:  03 a4 84 b5   add r3,r4 \|\| not r4,r5
00317 
00318 0+0204 <mul__sra>:
00319  204:  13 24 91 62   sra r3,r4 \|\| mul r1,r2
00320 
00321 0+0208 <mul__sra__reverse_src_clash>:
00322  208:  13 24 91 63   sra r3,r4 \|\| mul r1,r3
00323 
00324 0+020c <bc__add_>:
00325  20c:  7c 04 01 a2   bc 21c <label> -> add r1,r2
00326 
00327 0+0210 <add__bc>:
00328  210:  7c 03 83 a4   bc 21c <label> \|\| add r3,r4
00329 
00330 0+0214 <bc__add__forced_parallel>:
00331  214:  7c 02 85 a6   bc 21c <label> \|\| add r5,r6
00332 
00333 0+0218 <add__bc__forced_parallel>:
00334  218:  7c 01 87 a8   bc 21c <label> \|\| add r7,r8
00335 
00336 0+021c <label>:
00337  21c:  70 00 f0 00   nop \|\| nop
00338 
00339 0+0220 <mulwhi>:
00340  220:  3d 2d 3d ad   mulwhi fp,fp -> mulwhi fp,fp,a1
00341 
00342 0+0224 <mulwlo>:
00343  224:  3d 3d 3d bd   mulwlo fp,fp -> mulwlo fp,fp,a1
00344 
00345 0+0228 <macwhi>:
00346  228:  3d 6d 3d ed   macwhi fp,fp -> macwhi fp,fp,a1
00347 
00348 0+022c <macwlo>:
00349  22c:  3d 7d 3d fd   macwlo fp,fp -> macwlo fp,fp,a1