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cell-binutils  2.17cvs20070401
m32r2.d
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00001 #as: -m32r2
00002 #objdump: -dr
00003 #name: m32r2
00004 
00005 .*: +file format .*
00006 
00007 Disassembly of section .text:
00008 
00009 0+0000 <setpsw>:
00010    0:  71 c1 71 ff   setpsw #0xc1 -> setpsw #0xff
00011 
00012 0+0004 <clrpsw>:
00013    4:  72 c1 72 ff   clrpsw #0xc1 -> clrpsw #0xff
00014 
00015 0+0008 <bset>:
00016    8:  a0 61 00 04   bset #0x0,@\(4,r1\)
00017    c:  a1 61 00 04   bset #0x1,@\(4,r1\)
00018   10:  a7 61 00 04   bset #0x7,@\(4,r1\)
00019 
00020 0+0014 <bclr>:
00021   14:  a0 71 00 04   bclr #0x0,@\(4,r1\)
00022   18:  a1 71 00 04   bclr #0x1,@\(4,r1\)
00023   1c:  a7 71 00 04   bclr #0x7,@\(4,r1\)
00024 
00025 0+0020 <btst>:
00026   20:  00 fd 01 fd   btst #0x0,fp -> btst #0x1,fp
00027   24:  07 fd f0 00   btst #0x7,fp \|\| nop
00028   28:  01 fd 90 82   btst #0x1,fp \|\| mv r0,r2
00029   2c:  01 fd 90 82   btst #0x1,fp \|\| mv r0,r2
00030 
00031 0+0030 <divuh>:
00032   30:  9d 1d 00 10   divuh fp,fp
00033 
00034 0+0034 <divb>:
00035   34:  9d 0d 00 18   divb fp,fp
00036 
00037 0+0038 <divub>:
00038   38:  9d 1d 00 18   divub fp,fp
00039 
00040 0+003c <remh>:
00041   3c:  9d 2d 00 10   remh fp,fp
00042 
00043 0+0040 <remuh>:
00044   40:  9d 3d 00 10   remuh fp,fp
00045 
00046 0+0044 <remb>:
00047   44:  9d 2d 00 18   remb fp,fp
00048 
00049 0+0048 <remub>:
00050   48:  9d 3d 00 18   remub fp,fp
00051 
00052 0+004c <sll>:
00053   4c:  10 41 92 43   sll r0,r1 \|\| sll r2,r3
00054   50:  12 43 90 61   sll r2,r3 \|\| mul r0,r1
00055   54:  10 41 92 63   sll r0,r1 \|\| mul r2,r3
00056   58:  60 01 92 43   ldi r0,#1 \|\| sll r2,r3
00057   5c:  10 41 e2 01   sll r0,r1 \|\| ldi r2,#1
00058 
00059 0+0060 <slli>:
00060   60:  50 41 d2 5f   slli r0,#0x1 \|\| slli r2,#0x1f
00061   64:  52 5f 90 61   slli r2,#0x1f \|\| mul r0,r1
00062   68:  50 41 92 63   slli r0,#0x1 \|\| mul r2,r3
00063   6c:  60 01 d2 5f   ldi r0,#1 \|\| slli r2,#0x1f
00064   70:  50 41 e2 01   slli r0,#0x1 \|\| ldi r2,#1
00065 
00066 0+0074 <sra>:
00067   74:  10 21 92 23   sra r0,r1 \|\| sra r2,r3
00068   78:  12 23 90 61   sra r2,r3 \|\| mul r0,r1
00069   7c:  10 21 92 63   sra r0,r1 \|\| mul r2,r3
00070   80:  60 01 92 23   ldi r0,#1 \|\| sra r2,r3
00071   84:  10 21 e2 01   sra r0,r1 \|\| ldi r2,#1
00072 
00073 0+0088 <srai>:
00074   88:  50 21 d2 3f   srai r0,#0x1 \|\| srai r2,#0x1f
00075   8c:  52 3f 90 61   srai r2,#0x1f \|\| mul r0,r1
00076   90:  50 21 92 63   srai r0,#0x1 \|\| mul r2,r3
00077   94:  60 01 d2 3f   ldi r0,#1 \|\| srai r2,#0x1f
00078   98:  50 21 e2 01   srai r0,#0x1 \|\| ldi r2,#1
00079 
00080 0+009c <srl>:
00081   9c:  10 01 92 03   srl r0,r1 \|\| srl r2,r3
00082   a0:  12 03 90 61   srl r2,r3 \|\| mul r0,r1
00083   a4:  10 01 92 63   srl r0,r1 \|\| mul r2,r3
00084   a8:  60 01 92 03   ldi r0,#1 \|\| srl r2,r3
00085   ac:  10 01 e2 01   srl r0,r1 \|\| ldi r2,#1
00086 
00087 0+00b0 <srli>:
00088   b0:  50 01 d2 1f   srli r0,#0x1 \|\| srli r2,#0x1f
00089   b4:  52 1f 90 61   srli r2,#0x1f \|\| mul r0,r1
00090   b8:  50 01 92 63   srli r0,#0x1 \|\| mul r2,r3
00091   bc:  60 01 d2 1f   ldi r0,#1 \|\| srli r2,#0x1f
00092   c0:  50 01 e2 01   srli r0,#0x1 \|\| ldi r2,#1