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cell-binutils  2.17cvs20070401
m32r-opc.h
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00001 /* Instruction opcode header for m32r.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef M32R_OPC_H
00026 #define M32R_OPC_H
00027 
00028 /* -- opc.h */
00029 
00030 #undef  CGEN_DIS_HASH_SIZE
00031 #define CGEN_DIS_HASH_SIZE 256
00032 #undef  CGEN_DIS_HASH
00033 #if 0
00034 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
00035 #define CGEN_DIS_HASH(buffer, value) \
00036 (X (buffer) | \
00037  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
00038   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
00039   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
00040   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
00041 #else
00042 #define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
00043 extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
00044 #endif
00045 
00046 /* -- */
00047 /* Enum declaration for m32r instruction types.  */
00048 typedef enum cgen_insn_type {
00049   M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
00050  , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
00051  , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
00052  , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
00053  , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
00054  , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
00055  , M32R_INSN_BCL8, M32R_INSN_BCL24, M32R_INSN_BNC8, M32R_INSN_BNC24
00056  , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
00057  , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
00058  , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
00059  , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH
00060  , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH
00061  , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC
00062  , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD
00063  , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH
00064  , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH
00065  , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8
00066  , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A
00067  , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A
00068  , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI
00069  , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI
00070  , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV
00071  , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A
00072  , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI
00073  , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC
00074  , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC
00075  , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE
00076  , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI
00077  , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL
00078  , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D
00079  , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D
00080  , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS
00081  , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
00082  , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT
00083  , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO
00084  , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
00085  , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR
00086  , M32R_INSN_BTST
00087 } CGEN_INSN_TYPE;
00088 
00089 /* Index of `invalid' insn place holder.  */
00090 #define CGEN_INSN_INVALID M32R_INSN_INVALID
00091 
00092 /* Total number of insns in table.  */
00093 #define MAX_INSNS ((int) M32R_INSN_BTST + 1)
00094 
00095 /* This struct records data prior to insertion or after extraction.  */
00096 struct cgen_fields
00097 {
00098   int length;
00099   long f_nil;
00100   long f_anyof;
00101   long f_op1;
00102   long f_op2;
00103   long f_cond;
00104   long f_r1;
00105   long f_r2;
00106   long f_simm8;
00107   long f_simm16;
00108   long f_shift_op2;
00109   long f_uimm3;
00110   long f_uimm4;
00111   long f_uimm5;
00112   long f_uimm8;
00113   long f_uimm16;
00114   long f_uimm24;
00115   long f_hi16;
00116   long f_disp8;
00117   long f_disp16;
00118   long f_disp24;
00119   long f_op23;
00120   long f_op3;
00121   long f_acc;
00122   long f_accs;
00123   long f_accd;
00124   long f_bits67;
00125   long f_bit4;
00126   long f_bit14;
00127   long f_imm1;
00128 };
00129 
00130 #define CGEN_INIT_PARSE(od) \
00131 {\
00132 }
00133 #define CGEN_INIT_INSERT(od) \
00134 {\
00135 }
00136 #define CGEN_INIT_EXTRACT(od) \
00137 {\
00138 }
00139 #define CGEN_INIT_PRINT(od) \
00140 {\
00141 }
00142 
00143 
00144 #endif /* M32R_OPC_H */