Back to index

cell-binutils  2.17cvs20070401
m32r-opc.c
Go to the documentation of this file.
00001 /* Instruction opcode table for m32r.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include "ansidecl.h"
00027 #include "bfd.h"
00028 #include "symcat.h"
00029 #include "m32r-desc.h"
00030 #include "m32r-opc.h"
00031 #include "libiberty.h"
00032 
00033 /* -- opc.c */
00034 unsigned int
00035 m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
00036 {
00037   unsigned int x;
00038 
00039   if (value & 0xffff0000) /* 32bit instructions.  */
00040     value = (value >> 16) & 0xffff;
00041 
00042   x = (value >> 8) & 0xf0;
00043   if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
00044     return x;
00045 
00046   if (x == 0x70 || x == 0xf0)
00047     return x | ((value >> 8) & 0x0f);
00048 
00049   if (x == 0x30)
00050     return x | ((value & 0x70) >> 4);
00051   else
00052     return x | ((value & 0xf0) >> 4);
00053 }
00054 
00055 /* -- */
00056 /* The hash functions are recorded here to help keep assembler code out of
00057    the disassembler and vice versa.  */
00058 
00059 static int asm_hash_insn_p        (const CGEN_INSN *);
00060 static unsigned int asm_hash_insn (const char *);
00061 static int dis_hash_insn_p        (const CGEN_INSN *);
00062 static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
00063 
00064 /* Instruction formats.  */
00065 
00066 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00067 #define F(f) & m32r_cgen_ifld_table[M32R_##f]
00068 #else
00069 #define F(f) & m32r_cgen_ifld_table[M32R_f]
00070 #endif
00071 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
00072   0, 0, 0x0, { { 0 } }
00073 };
00074 
00075 static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
00076   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00077 };
00078 
00079 static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = {
00080   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00081 };
00082 
00083 static const CGEN_IFMT ifmt_and3 ATTRIBUTE_UNUSED = {
00084   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
00085 };
00086 
00087 static const CGEN_IFMT ifmt_or3 ATTRIBUTE_UNUSED = {
00088   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
00089 };
00090 
00091 static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
00092   16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
00093 };
00094 
00095 static const CGEN_IFMT ifmt_addv3 ATTRIBUTE_UNUSED = {
00096   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00097 };
00098 
00099 static const CGEN_IFMT ifmt_bc8 ATTRIBUTE_UNUSED = {
00100   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
00101 };
00102 
00103 static const CGEN_IFMT ifmt_bc24 ATTRIBUTE_UNUSED = {
00104   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
00105 };
00106 
00107 static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = {
00108   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
00109 };
00110 
00111 static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = {
00112   32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
00113 };
00114 
00115 static const CGEN_IFMT ifmt_cmp ATTRIBUTE_UNUSED = {
00116   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00117 };
00118 
00119 static const CGEN_IFMT ifmt_cmpi ATTRIBUTE_UNUSED = {
00120   32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00121 };
00122 
00123 static const CGEN_IFMT ifmt_cmpz ATTRIBUTE_UNUSED = {
00124   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00125 };
00126 
00127 static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = {
00128   32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00129 };
00130 
00131 static const CGEN_IFMT ifmt_jc ATTRIBUTE_UNUSED = {
00132   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00133 };
00134 
00135 static const CGEN_IFMT ifmt_ld24 ATTRIBUTE_UNUSED = {
00136   32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
00137 };
00138 
00139 static const CGEN_IFMT ifmt_ldi16 ATTRIBUTE_UNUSED = {
00140   32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00141 };
00142 
00143 static const CGEN_IFMT ifmt_machi_a ATTRIBUTE_UNUSED = {
00144   16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
00145 };
00146 
00147 static const CGEN_IFMT ifmt_mvfachi ATTRIBUTE_UNUSED = {
00148   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00149 };
00150 
00151 static const CGEN_IFMT ifmt_mvfachi_a ATTRIBUTE_UNUSED = {
00152   16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
00153 };
00154 
00155 static const CGEN_IFMT ifmt_mvfc ATTRIBUTE_UNUSED = {
00156   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00157 };
00158 
00159 static const CGEN_IFMT ifmt_mvtachi ATTRIBUTE_UNUSED = {
00160   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00161 };
00162 
00163 static const CGEN_IFMT ifmt_mvtachi_a ATTRIBUTE_UNUSED = {
00164   16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
00165 };
00166 
00167 static const CGEN_IFMT ifmt_mvtc ATTRIBUTE_UNUSED = {
00168   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00169 };
00170 
00171 static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
00172   16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00173 };
00174 
00175 static const CGEN_IFMT ifmt_rac_dsi ATTRIBUTE_UNUSED = {
00176   16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
00177 };
00178 
00179 static const CGEN_IFMT ifmt_seth ATTRIBUTE_UNUSED = {
00180   32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
00181 };
00182 
00183 static const CGEN_IFMT ifmt_slli ATTRIBUTE_UNUSED = {
00184   16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
00185 };
00186 
00187 static const CGEN_IFMT ifmt_st_d ATTRIBUTE_UNUSED = {
00188   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00189 };
00190 
00191 static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = {
00192   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
00193 };
00194 
00195 static const CGEN_IFMT ifmt_satb ATTRIBUTE_UNUSED = {
00196   32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
00197 };
00198 
00199 static const CGEN_IFMT ifmt_clrpsw ATTRIBUTE_UNUSED = {
00200   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
00201 };
00202 
00203 static const CGEN_IFMT ifmt_bset ATTRIBUTE_UNUSED = {
00204   32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00205 };
00206 
00207 static const CGEN_IFMT ifmt_btst ATTRIBUTE_UNUSED = {
00208   16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00209 };
00210 
00211 #undef F
00212 
00213 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00214 #define A(a) (1 << CGEN_INSN_##a)
00215 #else
00216 #define A(a) (1 << CGEN_INSN_a)
00217 #endif
00218 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00219 #define OPERAND(op) M32R_OPERAND_##op
00220 #else
00221 #define OPERAND(op) M32R_OPERAND_op
00222 #endif
00223 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
00224 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00225 
00226 /* The instruction table.  */
00227 
00228 static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
00229 {
00230   /* Special null first entry.
00231      A `num' value of zero is thus invalid.
00232      Also, the special `invalid' insn resides here.  */
00233   { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
00234 /* add $dr,$sr */
00235   {
00236     { 0, 0, 0, 0 },
00237     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00238     & ifmt_add, { 0xa0 }
00239   },
00240 /* add3 $dr,$sr,$hash$slo16 */
00241   {
00242     { 0, 0, 0, 0 },
00243     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
00244     & ifmt_add3, { 0x80a00000 }
00245   },
00246 /* and $dr,$sr */
00247   {
00248     { 0, 0, 0, 0 },
00249     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00250     & ifmt_add, { 0xc0 }
00251   },
00252 /* and3 $dr,$sr,$uimm16 */
00253   {
00254     { 0, 0, 0, 0 },
00255     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
00256     & ifmt_and3, { 0x80c00000 }
00257   },
00258 /* or $dr,$sr */
00259   {
00260     { 0, 0, 0, 0 },
00261     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00262     & ifmt_add, { 0xe0 }
00263   },
00264 /* or3 $dr,$sr,$hash$ulo16 */
00265   {
00266     { 0, 0, 0, 0 },
00267     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
00268     & ifmt_or3, { 0x80e00000 }
00269   },
00270 /* xor $dr,$sr */
00271   {
00272     { 0, 0, 0, 0 },
00273     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00274     & ifmt_add, { 0xd0 }
00275   },
00276 /* xor3 $dr,$sr,$uimm16 */
00277   {
00278     { 0, 0, 0, 0 },
00279     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
00280     & ifmt_and3, { 0x80d00000 }
00281   },
00282 /* addi $dr,$simm8 */
00283   {
00284     { 0, 0, 0, 0 },
00285     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
00286     & ifmt_addi, { 0x4000 }
00287   },
00288 /* addv $dr,$sr */
00289   {
00290     { 0, 0, 0, 0 },
00291     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00292     & ifmt_add, { 0x80 }
00293   },
00294 /* addv3 $dr,$sr,$simm16 */
00295   {
00296     { 0, 0, 0, 0 },
00297     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00298     & ifmt_addv3, { 0x80800000 }
00299   },
00300 /* addx $dr,$sr */
00301   {
00302     { 0, 0, 0, 0 },
00303     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00304     & ifmt_add, { 0x90 }
00305   },
00306 /* bc.s $disp8 */
00307   {
00308     { 0, 0, 0, 0 },
00309     { { MNEM, ' ', OP (DISP8), 0 } },
00310     & ifmt_bc8, { 0x7c00 }
00311   },
00312 /* bc.l $disp24 */
00313   {
00314     { 0, 0, 0, 0 },
00315     { { MNEM, ' ', OP (DISP24), 0 } },
00316     & ifmt_bc24, { 0xfc000000 }
00317   },
00318 /* beq $src1,$src2,$disp16 */
00319   {
00320     { 0, 0, 0, 0 },
00321     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
00322     & ifmt_beq, { 0xb0000000 }
00323   },
00324 /* beqz $src2,$disp16 */
00325   {
00326     { 0, 0, 0, 0 },
00327     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00328     & ifmt_beqz, { 0xb0800000 }
00329   },
00330 /* bgez $src2,$disp16 */
00331   {
00332     { 0, 0, 0, 0 },
00333     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00334     & ifmt_beqz, { 0xb0b00000 }
00335   },
00336 /* bgtz $src2,$disp16 */
00337   {
00338     { 0, 0, 0, 0 },
00339     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00340     & ifmt_beqz, { 0xb0d00000 }
00341   },
00342 /* blez $src2,$disp16 */
00343   {
00344     { 0, 0, 0, 0 },
00345     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00346     & ifmt_beqz, { 0xb0c00000 }
00347   },
00348 /* bltz $src2,$disp16 */
00349   {
00350     { 0, 0, 0, 0 },
00351     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00352     & ifmt_beqz, { 0xb0a00000 }
00353   },
00354 /* bnez $src2,$disp16 */
00355   {
00356     { 0, 0, 0, 0 },
00357     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00358     & ifmt_beqz, { 0xb0900000 }
00359   },
00360 /* bl.s $disp8 */
00361   {
00362     { 0, 0, 0, 0 },
00363     { { MNEM, ' ', OP (DISP8), 0 } },
00364     & ifmt_bc8, { 0x7e00 }
00365   },
00366 /* bl.l $disp24 */
00367   {
00368     { 0, 0, 0, 0 },
00369     { { MNEM, ' ', OP (DISP24), 0 } },
00370     & ifmt_bc24, { 0xfe000000 }
00371   },
00372 /* bcl.s $disp8 */
00373   {
00374     { 0, 0, 0, 0 },
00375     { { MNEM, ' ', OP (DISP8), 0 } },
00376     & ifmt_bc8, { 0x7800 }
00377   },
00378 /* bcl.l $disp24 */
00379   {
00380     { 0, 0, 0, 0 },
00381     { { MNEM, ' ', OP (DISP24), 0 } },
00382     & ifmt_bc24, { 0xf8000000 }
00383   },
00384 /* bnc.s $disp8 */
00385   {
00386     { 0, 0, 0, 0 },
00387     { { MNEM, ' ', OP (DISP8), 0 } },
00388     & ifmt_bc8, { 0x7d00 }
00389   },
00390 /* bnc.l $disp24 */
00391   {
00392     { 0, 0, 0, 0 },
00393     { { MNEM, ' ', OP (DISP24), 0 } },
00394     & ifmt_bc24, { 0xfd000000 }
00395   },
00396 /* bne $src1,$src2,$disp16 */
00397   {
00398     { 0, 0, 0, 0 },
00399     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
00400     & ifmt_beq, { 0xb0100000 }
00401   },
00402 /* bra.s $disp8 */
00403   {
00404     { 0, 0, 0, 0 },
00405     { { MNEM, ' ', OP (DISP8), 0 } },
00406     & ifmt_bc8, { 0x7f00 }
00407   },
00408 /* bra.l $disp24 */
00409   {
00410     { 0, 0, 0, 0 },
00411     { { MNEM, ' ', OP (DISP24), 0 } },
00412     & ifmt_bc24, { 0xff000000 }
00413   },
00414 /* bncl.s $disp8 */
00415   {
00416     { 0, 0, 0, 0 },
00417     { { MNEM, ' ', OP (DISP8), 0 } },
00418     & ifmt_bc8, { 0x7900 }
00419   },
00420 /* bncl.l $disp24 */
00421   {
00422     { 0, 0, 0, 0 },
00423     { { MNEM, ' ', OP (DISP24), 0 } },
00424     & ifmt_bc24, { 0xf9000000 }
00425   },
00426 /* cmp $src1,$src2 */
00427   {
00428     { 0, 0, 0, 0 },
00429     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00430     & ifmt_cmp, { 0x40 }
00431   },
00432 /* cmpi $src2,$simm16 */
00433   {
00434     { 0, 0, 0, 0 },
00435     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
00436     & ifmt_cmpi, { 0x80400000 }
00437   },
00438 /* cmpu $src1,$src2 */
00439   {
00440     { 0, 0, 0, 0 },
00441     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00442     & ifmt_cmp, { 0x50 }
00443   },
00444 /* cmpui $src2,$simm16 */
00445   {
00446     { 0, 0, 0, 0 },
00447     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
00448     & ifmt_cmpi, { 0x80500000 }
00449   },
00450 /* cmpeq $src1,$src2 */
00451   {
00452     { 0, 0, 0, 0 },
00453     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00454     & ifmt_cmp, { 0x60 }
00455   },
00456 /* cmpz $src2 */
00457   {
00458     { 0, 0, 0, 0 },
00459     { { MNEM, ' ', OP (SRC2), 0 } },
00460     & ifmt_cmpz, { 0x70 }
00461   },
00462 /* div $dr,$sr */
00463   {
00464     { 0, 0, 0, 0 },
00465     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00466     & ifmt_div, { 0x90000000 }
00467   },
00468 /* divu $dr,$sr */
00469   {
00470     { 0, 0, 0, 0 },
00471     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00472     & ifmt_div, { 0x90100000 }
00473   },
00474 /* rem $dr,$sr */
00475   {
00476     { 0, 0, 0, 0 },
00477     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00478     & ifmt_div, { 0x90200000 }
00479   },
00480 /* remu $dr,$sr */
00481   {
00482     { 0, 0, 0, 0 },
00483     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00484     & ifmt_div, { 0x90300000 }
00485   },
00486 /* remh $dr,$sr */
00487   {
00488     { 0, 0, 0, 0 },
00489     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00490     & ifmt_div, { 0x90200010 }
00491   },
00492 /* remuh $dr,$sr */
00493   {
00494     { 0, 0, 0, 0 },
00495     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00496     & ifmt_div, { 0x90300010 }
00497   },
00498 /* remb $dr,$sr */
00499   {
00500     { 0, 0, 0, 0 },
00501     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00502     & ifmt_div, { 0x90200018 }
00503   },
00504 /* remub $dr,$sr */
00505   {
00506     { 0, 0, 0, 0 },
00507     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00508     & ifmt_div, { 0x90300018 }
00509   },
00510 /* divuh $dr,$sr */
00511   {
00512     { 0, 0, 0, 0 },
00513     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00514     & ifmt_div, { 0x90100010 }
00515   },
00516 /* divb $dr,$sr */
00517   {
00518     { 0, 0, 0, 0 },
00519     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00520     & ifmt_div, { 0x90000018 }
00521   },
00522 /* divub $dr,$sr */
00523   {
00524     { 0, 0, 0, 0 },
00525     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00526     & ifmt_div, { 0x90100018 }
00527   },
00528 /* divh $dr,$sr */
00529   {
00530     { 0, 0, 0, 0 },
00531     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00532     & ifmt_div, { 0x90000010 }
00533   },
00534 /* jc $sr */
00535   {
00536     { 0, 0, 0, 0 },
00537     { { MNEM, ' ', OP (SR), 0 } },
00538     & ifmt_jc, { 0x1cc0 }
00539   },
00540 /* jnc $sr */
00541   {
00542     { 0, 0, 0, 0 },
00543     { { MNEM, ' ', OP (SR), 0 } },
00544     & ifmt_jc, { 0x1dc0 }
00545   },
00546 /* jl $sr */
00547   {
00548     { 0, 0, 0, 0 },
00549     { { MNEM, ' ', OP (SR), 0 } },
00550     & ifmt_jc, { 0x1ec0 }
00551   },
00552 /* jmp $sr */
00553   {
00554     { 0, 0, 0, 0 },
00555     { { MNEM, ' ', OP (SR), 0 } },
00556     & ifmt_jc, { 0x1fc0 }
00557   },
00558 /* ld $dr,@$sr */
00559   {
00560     { 0, 0, 0, 0 },
00561     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00562     & ifmt_add, { 0x20c0 }
00563   },
00564 /* ld $dr,@($slo16,$sr) */
00565   {
00566     { 0, 0, 0, 0 },
00567     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00568     & ifmt_add3, { 0xa0c00000 }
00569   },
00570 /* ldb $dr,@$sr */
00571   {
00572     { 0, 0, 0, 0 },
00573     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00574     & ifmt_add, { 0x2080 }
00575   },
00576 /* ldb $dr,@($slo16,$sr) */
00577   {
00578     { 0, 0, 0, 0 },
00579     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00580     & ifmt_add3, { 0xa0800000 }
00581   },
00582 /* ldh $dr,@$sr */
00583   {
00584     { 0, 0, 0, 0 },
00585     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00586     & ifmt_add, { 0x20a0 }
00587   },
00588 /* ldh $dr,@($slo16,$sr) */
00589   {
00590     { 0, 0, 0, 0 },
00591     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00592     & ifmt_add3, { 0xa0a00000 }
00593   },
00594 /* ldub $dr,@$sr */
00595   {
00596     { 0, 0, 0, 0 },
00597     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00598     & ifmt_add, { 0x2090 }
00599   },
00600 /* ldub $dr,@($slo16,$sr) */
00601   {
00602     { 0, 0, 0, 0 },
00603     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00604     & ifmt_add3, { 0xa0900000 }
00605   },
00606 /* lduh $dr,@$sr */
00607   {
00608     { 0, 0, 0, 0 },
00609     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00610     & ifmt_add, { 0x20b0 }
00611   },
00612 /* lduh $dr,@($slo16,$sr) */
00613   {
00614     { 0, 0, 0, 0 },
00615     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00616     & ifmt_add3, { 0xa0b00000 }
00617   },
00618 /* ld $dr,@$sr+ */
00619   {
00620     { 0, 0, 0, 0 },
00621     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
00622     & ifmt_add, { 0x20e0 }
00623   },
00624 /* ld24 $dr,$uimm24 */
00625   {
00626     { 0, 0, 0, 0 },
00627     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
00628     & ifmt_ld24, { 0xe0000000 }
00629   },
00630 /* ldi8 $dr,$simm8 */
00631   {
00632     { 0, 0, 0, 0 },
00633     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
00634     & ifmt_addi, { 0x6000 }
00635   },
00636 /* ldi16 $dr,$hash$slo16 */
00637   {
00638     { 0, 0, 0, 0 },
00639     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
00640     & ifmt_ldi16, { 0x90f00000 }
00641   },
00642 /* lock $dr,@$sr */
00643   {
00644     { 0, 0, 0, 0 },
00645     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00646     & ifmt_add, { 0x20d0 }
00647   },
00648 /* machi $src1,$src2 */
00649   {
00650     { 0, 0, 0, 0 },
00651     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00652     & ifmt_cmp, { 0x3040 }
00653   },
00654 /* machi $src1,$src2,$acc */
00655   {
00656     { 0, 0, 0, 0 },
00657     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00658     & ifmt_machi_a, { 0x3040 }
00659   },
00660 /* maclo $src1,$src2 */
00661   {
00662     { 0, 0, 0, 0 },
00663     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00664     & ifmt_cmp, { 0x3050 }
00665   },
00666 /* maclo $src1,$src2,$acc */
00667   {
00668     { 0, 0, 0, 0 },
00669     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00670     & ifmt_machi_a, { 0x3050 }
00671   },
00672 /* macwhi $src1,$src2 */
00673   {
00674     { 0, 0, 0, 0 },
00675     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00676     & ifmt_cmp, { 0x3060 }
00677   },
00678 /* macwhi $src1,$src2,$acc */
00679   {
00680     { 0, 0, 0, 0 },
00681     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00682     & ifmt_machi_a, { 0x3060 }
00683   },
00684 /* macwlo $src1,$src2 */
00685   {
00686     { 0, 0, 0, 0 },
00687     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00688     & ifmt_cmp, { 0x3070 }
00689   },
00690 /* macwlo $src1,$src2,$acc */
00691   {
00692     { 0, 0, 0, 0 },
00693     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00694     & ifmt_machi_a, { 0x3070 }
00695   },
00696 /* mul $dr,$sr */
00697   {
00698     { 0, 0, 0, 0 },
00699     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00700     & ifmt_add, { 0x1060 }
00701   },
00702 /* mulhi $src1,$src2 */
00703   {
00704     { 0, 0, 0, 0 },
00705     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00706     & ifmt_cmp, { 0x3000 }
00707   },
00708 /* mulhi $src1,$src2,$acc */
00709   {
00710     { 0, 0, 0, 0 },
00711     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00712     & ifmt_machi_a, { 0x3000 }
00713   },
00714 /* mullo $src1,$src2 */
00715   {
00716     { 0, 0, 0, 0 },
00717     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00718     & ifmt_cmp, { 0x3010 }
00719   },
00720 /* mullo $src1,$src2,$acc */
00721   {
00722     { 0, 0, 0, 0 },
00723     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00724     & ifmt_machi_a, { 0x3010 }
00725   },
00726 /* mulwhi $src1,$src2 */
00727   {
00728     { 0, 0, 0, 0 },
00729     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00730     & ifmt_cmp, { 0x3020 }
00731   },
00732 /* mulwhi $src1,$src2,$acc */
00733   {
00734     { 0, 0, 0, 0 },
00735     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00736     & ifmt_machi_a, { 0x3020 }
00737   },
00738 /* mulwlo $src1,$src2 */
00739   {
00740     { 0, 0, 0, 0 },
00741     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00742     & ifmt_cmp, { 0x3030 }
00743   },
00744 /* mulwlo $src1,$src2,$acc */
00745   {
00746     { 0, 0, 0, 0 },
00747     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00748     & ifmt_machi_a, { 0x3030 }
00749   },
00750 /* mv $dr,$sr */
00751   {
00752     { 0, 0, 0, 0 },
00753     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00754     & ifmt_add, { 0x1080 }
00755   },
00756 /* mvfachi $dr */
00757   {
00758     { 0, 0, 0, 0 },
00759     { { MNEM, ' ', OP (DR), 0 } },
00760     & ifmt_mvfachi, { 0x50f0 }
00761   },
00762 /* mvfachi $dr,$accs */
00763   {
00764     { 0, 0, 0, 0 },
00765     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
00766     & ifmt_mvfachi_a, { 0x50f0 }
00767   },
00768 /* mvfaclo $dr */
00769   {
00770     { 0, 0, 0, 0 },
00771     { { MNEM, ' ', OP (DR), 0 } },
00772     & ifmt_mvfachi, { 0x50f1 }
00773   },
00774 /* mvfaclo $dr,$accs */
00775   {
00776     { 0, 0, 0, 0 },
00777     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
00778     & ifmt_mvfachi_a, { 0x50f1 }
00779   },
00780 /* mvfacmi $dr */
00781   {
00782     { 0, 0, 0, 0 },
00783     { { MNEM, ' ', OP (DR), 0 } },
00784     & ifmt_mvfachi, { 0x50f2 }
00785   },
00786 /* mvfacmi $dr,$accs */
00787   {
00788     { 0, 0, 0, 0 },
00789     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
00790     & ifmt_mvfachi_a, { 0x50f2 }
00791   },
00792 /* mvfc $dr,$scr */
00793   {
00794     { 0, 0, 0, 0 },
00795     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
00796     & ifmt_mvfc, { 0x1090 }
00797   },
00798 /* mvtachi $src1 */
00799   {
00800     { 0, 0, 0, 0 },
00801     { { MNEM, ' ', OP (SRC1), 0 } },
00802     & ifmt_mvtachi, { 0x5070 }
00803   },
00804 /* mvtachi $src1,$accs */
00805   {
00806     { 0, 0, 0, 0 },
00807     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
00808     & ifmt_mvtachi_a, { 0x5070 }
00809   },
00810 /* mvtaclo $src1 */
00811   {
00812     { 0, 0, 0, 0 },
00813     { { MNEM, ' ', OP (SRC1), 0 } },
00814     & ifmt_mvtachi, { 0x5071 }
00815   },
00816 /* mvtaclo $src1,$accs */
00817   {
00818     { 0, 0, 0, 0 },
00819     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
00820     & ifmt_mvtachi_a, { 0x5071 }
00821   },
00822 /* mvtc $sr,$dcr */
00823   {
00824     { 0, 0, 0, 0 },
00825     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
00826     & ifmt_mvtc, { 0x10a0 }
00827   },
00828 /* neg $dr,$sr */
00829   {
00830     { 0, 0, 0, 0 },
00831     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00832     & ifmt_add, { 0x30 }
00833   },
00834 /* nop */
00835   {
00836     { 0, 0, 0, 0 },
00837     { { MNEM, 0 } },
00838     & ifmt_nop, { 0x7000 }
00839   },
00840 /* not $dr,$sr */
00841   {
00842     { 0, 0, 0, 0 },
00843     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00844     & ifmt_add, { 0xb0 }
00845   },
00846 /* rac */
00847   {
00848     { 0, 0, 0, 0 },
00849     { { MNEM, 0 } },
00850     & ifmt_nop, { 0x5090 }
00851   },
00852 /* rac $accd,$accs,$imm1 */
00853   {
00854     { 0, 0, 0, 0 },
00855     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
00856     & ifmt_rac_dsi, { 0x5090 }
00857   },
00858 /* rach */
00859   {
00860     { 0, 0, 0, 0 },
00861     { { MNEM, 0 } },
00862     & ifmt_nop, { 0x5080 }
00863   },
00864 /* rach $accd,$accs,$imm1 */
00865   {
00866     { 0, 0, 0, 0 },
00867     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
00868     & ifmt_rac_dsi, { 0x5080 }
00869   },
00870 /* rte */
00871   {
00872     { 0, 0, 0, 0 },
00873     { { MNEM, 0 } },
00874     & ifmt_nop, { 0x10d6 }
00875   },
00876 /* seth $dr,$hash$hi16 */
00877   {
00878     { 0, 0, 0, 0 },
00879     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
00880     & ifmt_seth, { 0xd0c00000 }
00881   },
00882 /* sll $dr,$sr */
00883   {
00884     { 0, 0, 0, 0 },
00885     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00886     & ifmt_add, { 0x1040 }
00887   },
00888 /* sll3 $dr,$sr,$simm16 */
00889   {
00890     { 0, 0, 0, 0 },
00891     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00892     & ifmt_addv3, { 0x90c00000 }
00893   },
00894 /* slli $dr,$uimm5 */
00895   {
00896     { 0, 0, 0, 0 },
00897     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
00898     & ifmt_slli, { 0x5040 }
00899   },
00900 /* sra $dr,$sr */
00901   {
00902     { 0, 0, 0, 0 },
00903     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00904     & ifmt_add, { 0x1020 }
00905   },
00906 /* sra3 $dr,$sr,$simm16 */
00907   {
00908     { 0, 0, 0, 0 },
00909     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00910     & ifmt_addv3, { 0x90a00000 }
00911   },
00912 /* srai $dr,$uimm5 */
00913   {
00914     { 0, 0, 0, 0 },
00915     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
00916     & ifmt_slli, { 0x5020 }
00917   },
00918 /* srl $dr,$sr */
00919   {
00920     { 0, 0, 0, 0 },
00921     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00922     & ifmt_add, { 0x1000 }
00923   },
00924 /* srl3 $dr,$sr,$simm16 */
00925   {
00926     { 0, 0, 0, 0 },
00927     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00928     & ifmt_addv3, { 0x90800000 }
00929   },
00930 /* srli $dr,$uimm5 */
00931   {
00932     { 0, 0, 0, 0 },
00933     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
00934     & ifmt_slli, { 0x5000 }
00935   },
00936 /* st $src1,@$src2 */
00937   {
00938     { 0, 0, 0, 0 },
00939     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
00940     & ifmt_cmp, { 0x2040 }
00941   },
00942 /* st $src1,@($slo16,$src2) */
00943   {
00944     { 0, 0, 0, 0 },
00945     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
00946     & ifmt_st_d, { 0xa0400000 }
00947   },
00948 /* stb $src1,@$src2 */
00949   {
00950     { 0, 0, 0, 0 },
00951     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
00952     & ifmt_cmp, { 0x2000 }
00953   },
00954 /* stb $src1,@($slo16,$src2) */
00955   {
00956     { 0, 0, 0, 0 },
00957     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
00958     & ifmt_st_d, { 0xa0000000 }
00959   },
00960 /* sth $src1,@$src2 */
00961   {
00962     { 0, 0, 0, 0 },
00963     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
00964     & ifmt_cmp, { 0x2020 }
00965   },
00966 /* sth $src1,@($slo16,$src2) */
00967   {
00968     { 0, 0, 0, 0 },
00969     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
00970     & ifmt_st_d, { 0xa0200000 }
00971   },
00972 /* st $src1,@+$src2 */
00973   {
00974     { 0, 0, 0, 0 },
00975     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
00976     & ifmt_cmp, { 0x2060 }
00977   },
00978 /* sth $src1,@$src2+ */
00979   {
00980     { 0, 0, 0, 0 },
00981     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
00982     & ifmt_cmp, { 0x2030 }
00983   },
00984 /* stb $src1,@$src2+ */
00985   {
00986     { 0, 0, 0, 0 },
00987     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
00988     & ifmt_cmp, { 0x2010 }
00989   },
00990 /* st $src1,@-$src2 */
00991   {
00992     { 0, 0, 0, 0 },
00993     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
00994     & ifmt_cmp, { 0x2070 }
00995   },
00996 /* sub $dr,$sr */
00997   {
00998     { 0, 0, 0, 0 },
00999     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01000     & ifmt_add, { 0x20 }
01001   },
01002 /* subv $dr,$sr */
01003   {
01004     { 0, 0, 0, 0 },
01005     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01006     & ifmt_add, { 0x0 }
01007   },
01008 /* subx $dr,$sr */
01009   {
01010     { 0, 0, 0, 0 },
01011     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01012     & ifmt_add, { 0x10 }
01013   },
01014 /* trap $uimm4 */
01015   {
01016     { 0, 0, 0, 0 },
01017     { { MNEM, ' ', OP (UIMM4), 0 } },
01018     & ifmt_trap, { 0x10f0 }
01019   },
01020 /* unlock $src1,@$src2 */
01021   {
01022     { 0, 0, 0, 0 },
01023     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
01024     & ifmt_cmp, { 0x2050 }
01025   },
01026 /* satb $dr,$sr */
01027   {
01028     { 0, 0, 0, 0 },
01029     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01030     & ifmt_satb, { 0x80600300 }
01031   },
01032 /* sath $dr,$sr */
01033   {
01034     { 0, 0, 0, 0 },
01035     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01036     & ifmt_satb, { 0x80600200 }
01037   },
01038 /* sat $dr,$sr */
01039   {
01040     { 0, 0, 0, 0 },
01041     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01042     & ifmt_satb, { 0x80600000 }
01043   },
01044 /* pcmpbz $src2 */
01045   {
01046     { 0, 0, 0, 0 },
01047     { { MNEM, ' ', OP (SRC2), 0 } },
01048     & ifmt_cmpz, { 0x370 }
01049   },
01050 /* sadd */
01051   {
01052     { 0, 0, 0, 0 },
01053     { { MNEM, 0 } },
01054     & ifmt_nop, { 0x50e4 }
01055   },
01056 /* macwu1 $src1,$src2 */
01057   {
01058     { 0, 0, 0, 0 },
01059     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01060     & ifmt_cmp, { 0x50b0 }
01061   },
01062 /* msblo $src1,$src2 */
01063   {
01064     { 0, 0, 0, 0 },
01065     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01066     & ifmt_cmp, { 0x50d0 }
01067   },
01068 /* mulwu1 $src1,$src2 */
01069   {
01070     { 0, 0, 0, 0 },
01071     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01072     & ifmt_cmp, { 0x50a0 }
01073   },
01074 /* maclh1 $src1,$src2 */
01075   {
01076     { 0, 0, 0, 0 },
01077     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01078     & ifmt_cmp, { 0x50c0 }
01079   },
01080 /* sc */
01081   {
01082     { 0, 0, 0, 0 },
01083     { { MNEM, 0 } },
01084     & ifmt_nop, { 0x7401 }
01085   },
01086 /* snc */
01087   {
01088     { 0, 0, 0, 0 },
01089     { { MNEM, 0 } },
01090     & ifmt_nop, { 0x7501 }
01091   },
01092 /* clrpsw $uimm8 */
01093   {
01094     { 0, 0, 0, 0 },
01095     { { MNEM, ' ', OP (UIMM8), 0 } },
01096     & ifmt_clrpsw, { 0x7200 }
01097   },
01098 /* setpsw $uimm8 */
01099   {
01100     { 0, 0, 0, 0 },
01101     { { MNEM, ' ', OP (UIMM8), 0 } },
01102     & ifmt_clrpsw, { 0x7100 }
01103   },
01104 /* bset $uimm3,@($slo16,$sr) */
01105   {
01106     { 0, 0, 0, 0 },
01107     { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
01108     & ifmt_bset, { 0xa0600000 }
01109   },
01110 /* bclr $uimm3,@($slo16,$sr) */
01111   {
01112     { 0, 0, 0, 0 },
01113     { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
01114     & ifmt_bset, { 0xa0700000 }
01115   },
01116 /* btst $uimm3,$sr */
01117   {
01118     { 0, 0, 0, 0 },
01119     { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
01120     & ifmt_btst, { 0xf0 }
01121   },
01122 };
01123 
01124 #undef A
01125 #undef OPERAND
01126 #undef MNEM
01127 #undef OP
01128 
01129 /* Formats for ALIAS macro-insns.  */
01130 
01131 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01132 #define F(f) & m32r_cgen_ifld_table[M32R_##f]
01133 #else
01134 #define F(f) & m32r_cgen_ifld_table[M32R_f]
01135 #endif
01136 static const CGEN_IFMT ifmt_bc8r ATTRIBUTE_UNUSED = {
01137   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01138 };
01139 
01140 static const CGEN_IFMT ifmt_bc24r ATTRIBUTE_UNUSED = {
01141   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01142 };
01143 
01144 static const CGEN_IFMT ifmt_bl8r ATTRIBUTE_UNUSED = {
01145   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01146 };
01147 
01148 static const CGEN_IFMT ifmt_bl24r ATTRIBUTE_UNUSED = {
01149   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01150 };
01151 
01152 static const CGEN_IFMT ifmt_bcl8r ATTRIBUTE_UNUSED = {
01153   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01154 };
01155 
01156 static const CGEN_IFMT ifmt_bcl24r ATTRIBUTE_UNUSED = {
01157   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01158 };
01159 
01160 static const CGEN_IFMT ifmt_bnc8r ATTRIBUTE_UNUSED = {
01161   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01162 };
01163 
01164 static const CGEN_IFMT ifmt_bnc24r ATTRIBUTE_UNUSED = {
01165   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01166 };
01167 
01168 static const CGEN_IFMT ifmt_bra8r ATTRIBUTE_UNUSED = {
01169   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01170 };
01171 
01172 static const CGEN_IFMT ifmt_bra24r ATTRIBUTE_UNUSED = {
01173   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01174 };
01175 
01176 static const CGEN_IFMT ifmt_bncl8r ATTRIBUTE_UNUSED = {
01177   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01178 };
01179 
01180 static const CGEN_IFMT ifmt_bncl24r ATTRIBUTE_UNUSED = {
01181   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01182 };
01183 
01184 static const CGEN_IFMT ifmt_ld_2 ATTRIBUTE_UNUSED = {
01185   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01186 };
01187 
01188 static const CGEN_IFMT ifmt_ld_d2 ATTRIBUTE_UNUSED = {
01189   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01190 };
01191 
01192 static const CGEN_IFMT ifmt_ldb_2 ATTRIBUTE_UNUSED = {
01193   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01194 };
01195 
01196 static const CGEN_IFMT ifmt_ldb_d2 ATTRIBUTE_UNUSED = {
01197   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01198 };
01199 
01200 static const CGEN_IFMT ifmt_ldh_2 ATTRIBUTE_UNUSED = {
01201   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01202 };
01203 
01204 static const CGEN_IFMT ifmt_ldh_d2 ATTRIBUTE_UNUSED = {
01205   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01206 };
01207 
01208 static const CGEN_IFMT ifmt_ldub_2 ATTRIBUTE_UNUSED = {
01209   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01210 };
01211 
01212 static const CGEN_IFMT ifmt_ldub_d2 ATTRIBUTE_UNUSED = {
01213   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01214 };
01215 
01216 static const CGEN_IFMT ifmt_lduh_2 ATTRIBUTE_UNUSED = {
01217   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01218 };
01219 
01220 static const CGEN_IFMT ifmt_lduh_d2 ATTRIBUTE_UNUSED = {
01221   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01222 };
01223 
01224 static const CGEN_IFMT ifmt_pop ATTRIBUTE_UNUSED = {
01225   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
01226 };
01227 
01228 static const CGEN_IFMT ifmt_ldi8a ATTRIBUTE_UNUSED = {
01229   16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
01230 };
01231 
01232 static const CGEN_IFMT ifmt_ldi16a ATTRIBUTE_UNUSED = {
01233   32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
01234 };
01235 
01236 static const CGEN_IFMT ifmt_rac_d ATTRIBUTE_UNUSED = {
01237   16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01238 };
01239 
01240 static const CGEN_IFMT ifmt_rac_ds ATTRIBUTE_UNUSED = {
01241   16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01242 };
01243 
01244 static const CGEN_IFMT ifmt_rach_d ATTRIBUTE_UNUSED = {
01245   16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01246 };
01247 
01248 static const CGEN_IFMT ifmt_rach_ds ATTRIBUTE_UNUSED = {
01249   16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01250 };
01251 
01252 static const CGEN_IFMT ifmt_st_2 ATTRIBUTE_UNUSED = {
01253   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01254 };
01255 
01256 static const CGEN_IFMT ifmt_st_d2 ATTRIBUTE_UNUSED = {
01257   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01258 };
01259 
01260 static const CGEN_IFMT ifmt_stb_2 ATTRIBUTE_UNUSED = {
01261   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01262 };
01263 
01264 static const CGEN_IFMT ifmt_stb_d2 ATTRIBUTE_UNUSED = {
01265   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01266 };
01267 
01268 static const CGEN_IFMT ifmt_sth_2 ATTRIBUTE_UNUSED = {
01269   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01270 };
01271 
01272 static const CGEN_IFMT ifmt_sth_d2 ATTRIBUTE_UNUSED = {
01273   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01274 };
01275 
01276 static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = {
01277   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01278 };
01279 
01280 #undef F
01281 
01282 /* Each non-simple macro entry points to an array of expansion possibilities.  */
01283 
01284 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01285 #define A(a) (1 << CGEN_INSN_##a)
01286 #else
01287 #define A(a) (1 << CGEN_INSN_a)
01288 #endif
01289 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01290 #define OPERAND(op) M32R_OPERAND_##op
01291 #else
01292 #define OPERAND(op) M32R_OPERAND_op
01293 #endif
01294 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
01295 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
01296 
01297 /* The macro instruction table.  */
01298 
01299 static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
01300 {
01301 /* bc $disp8 */
01302   {
01303     -1, "bc8r", "bc", 16,
01304     { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01305   },
01306 /* bc $disp24 */
01307   {
01308     -1, "bc24r", "bc", 32,
01309     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01310   },
01311 /* bl $disp8 */
01312   {
01313     -1, "bl8r", "bl", 16,
01314     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01315   },
01316 /* bl $disp24 */
01317   {
01318     -1, "bl24r", "bl", 32,
01319     { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01320   },
01321 /* bcl $disp8 */
01322   {
01323     -1, "bcl8r", "bcl", 16,
01324     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
01325   },
01326 /* bcl $disp24 */
01327   {
01328     -1, "bcl24r", "bcl", 32,
01329     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
01330   },
01331 /* bnc $disp8 */
01332   {
01333     -1, "bnc8r", "bnc", 16,
01334     { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01335   },
01336 /* bnc $disp24 */
01337   {
01338     -1, "bnc24r", "bnc", 32,
01339     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01340   },
01341 /* bra $disp8 */
01342   {
01343     -1, "bra8r", "bra", 16,
01344     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01345   },
01346 /* bra $disp24 */
01347   {
01348     -1, "bra24r", "bra", 32,
01349     { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01350   },
01351 /* bncl $disp8 */
01352   {
01353     -1, "bncl8r", "bncl", 16,
01354     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
01355   },
01356 /* bncl $disp24 */
01357   {
01358     -1, "bncl24r", "bncl", 32,
01359     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
01360   },
01361 /* ld $dr,@($sr) */
01362   {
01363     -1, "ld-2", "ld", 16,
01364     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01365   },
01366 /* ld $dr,@($sr,$slo16) */
01367   {
01368     -1, "ld-d2", "ld", 32,
01369     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01370   },
01371 /* ldb $dr,@($sr) */
01372   {
01373     -1, "ldb-2", "ldb", 16,
01374     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01375   },
01376 /* ldb $dr,@($sr,$slo16) */
01377   {
01378     -1, "ldb-d2", "ldb", 32,
01379     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01380   },
01381 /* ldh $dr,@($sr) */
01382   {
01383     -1, "ldh-2", "ldh", 16,
01384     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01385   },
01386 /* ldh $dr,@($sr,$slo16) */
01387   {
01388     -1, "ldh-d2", "ldh", 32,
01389     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01390   },
01391 /* ldub $dr,@($sr) */
01392   {
01393     -1, "ldub-2", "ldub", 16,
01394     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01395   },
01396 /* ldub $dr,@($sr,$slo16) */
01397   {
01398     -1, "ldub-d2", "ldub", 32,
01399     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01400   },
01401 /* lduh $dr,@($sr) */
01402   {
01403     -1, "lduh-2", "lduh", 16,
01404     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01405   },
01406 /* lduh $dr,@($sr,$slo16) */
01407   {
01408     -1, "lduh-d2", "lduh", 32,
01409     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01410   },
01411 /* pop $dr */
01412   {
01413     -1, "pop", "pop", 16,
01414     { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01415   },
01416 /* ldi $dr,$simm8 */
01417   {
01418     -1, "ldi8a", "ldi", 16,
01419     { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01420   },
01421 /* ldi $dr,$hash$slo16 */
01422   {
01423     -1, "ldi16a", "ldi", 32,
01424     { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01425   },
01426 /* rac $accd */
01427   {
01428     -1, "rac-d", "rac", 16,
01429     { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01430   },
01431 /* rac $accd,$accs */
01432   {
01433     -1, "rac-ds", "rac", 16,
01434     { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01435   },
01436 /* rach $accd */
01437   {
01438     -1, "rach-d", "rach", 16,
01439     { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01440   },
01441 /* rach $accd,$accs */
01442   {
01443     -1, "rach-ds", "rach", 16,
01444     { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01445   },
01446 /* st $src1,@($src2) */
01447   {
01448     -1, "st-2", "st", 16,
01449     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01450   },
01451 /* st $src1,@($src2,$slo16) */
01452   {
01453     -1, "st-d2", "st", 32,
01454     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01455   },
01456 /* stb $src1,@($src2) */
01457   {
01458     -1, "stb-2", "stb", 16,
01459     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01460   },
01461 /* stb $src1,@($src2,$slo16) */
01462   {
01463     -1, "stb-d2", "stb", 32,
01464     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01465   },
01466 /* sth $src1,@($src2) */
01467   {
01468     -1, "sth-2", "sth", 16,
01469     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01470   },
01471 /* sth $src1,@($src2,$slo16) */
01472   {
01473     -1, "sth-d2", "sth", 32,
01474     { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01475   },
01476 /* push $src1 */
01477   {
01478     -1, "push", "push", 16,
01479     { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01480   },
01481 };
01482 
01483 /* The macro instruction opcode table.  */
01484 
01485 static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
01486 {
01487 /* bc $disp8 */
01488   {
01489     { 0, 0, 0, 0 },
01490     { { MNEM, ' ', OP (DISP8), 0 } },
01491     & ifmt_bc8r, { 0x7c00 }
01492   },
01493 /* bc $disp24 */
01494   {
01495     { 0, 0, 0, 0 },
01496     { { MNEM, ' ', OP (DISP24), 0 } },
01497     & ifmt_bc24r, { 0xfc000000 }
01498   },
01499 /* bl $disp8 */
01500   {
01501     { 0, 0, 0, 0 },
01502     { { MNEM, ' ', OP (DISP8), 0 } },
01503     & ifmt_bl8r, { 0x7e00 }
01504   },
01505 /* bl $disp24 */
01506   {
01507     { 0, 0, 0, 0 },
01508     { { MNEM, ' ', OP (DISP24), 0 } },
01509     & ifmt_bl24r, { 0xfe000000 }
01510   },
01511 /* bcl $disp8 */
01512   {
01513     { 0, 0, 0, 0 },
01514     { { MNEM, ' ', OP (DISP8), 0 } },
01515     & ifmt_bcl8r, { 0x7800 }
01516   },
01517 /* bcl $disp24 */
01518   {
01519     { 0, 0, 0, 0 },
01520     { { MNEM, ' ', OP (DISP24), 0 } },
01521     & ifmt_bcl24r, { 0xf8000000 }
01522   },
01523 /* bnc $disp8 */
01524   {
01525     { 0, 0, 0, 0 },
01526     { { MNEM, ' ', OP (DISP8), 0 } },
01527     & ifmt_bnc8r, { 0x7d00 }
01528   },
01529 /* bnc $disp24 */
01530   {
01531     { 0, 0, 0, 0 },
01532     { { MNEM, ' ', OP (DISP24), 0 } },
01533     & ifmt_bnc24r, { 0xfd000000 }
01534   },
01535 /* bra $disp8 */
01536   {
01537     { 0, 0, 0, 0 },
01538     { { MNEM, ' ', OP (DISP8), 0 } },
01539     & ifmt_bra8r, { 0x7f00 }
01540   },
01541 /* bra $disp24 */
01542   {
01543     { 0, 0, 0, 0 },
01544     { { MNEM, ' ', OP (DISP24), 0 } },
01545     & ifmt_bra24r, { 0xff000000 }
01546   },
01547 /* bncl $disp8 */
01548   {
01549     { 0, 0, 0, 0 },
01550     { { MNEM, ' ', OP (DISP8), 0 } },
01551     & ifmt_bncl8r, { 0x7900 }
01552   },
01553 /* bncl $disp24 */
01554   {
01555     { 0, 0, 0, 0 },
01556     { { MNEM, ' ', OP (DISP24), 0 } },
01557     & ifmt_bncl24r, { 0xf9000000 }
01558   },
01559 /* ld $dr,@($sr) */
01560   {
01561     { 0, 0, 0, 0 },
01562     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01563     & ifmt_ld_2, { 0x20c0 }
01564   },
01565 /* ld $dr,@($sr,$slo16) */
01566   {
01567     { 0, 0, 0, 0 },
01568     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01569     & ifmt_ld_d2, { 0xa0c00000 }
01570   },
01571 /* ldb $dr,@($sr) */
01572   {
01573     { 0, 0, 0, 0 },
01574     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01575     & ifmt_ldb_2, { 0x2080 }
01576   },
01577 /* ldb $dr,@($sr,$slo16) */
01578   {
01579     { 0, 0, 0, 0 },
01580     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01581     & ifmt_ldb_d2, { 0xa0800000 }
01582   },
01583 /* ldh $dr,@($sr) */
01584   {
01585     { 0, 0, 0, 0 },
01586     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01587     & ifmt_ldh_2, { 0x20a0 }
01588   },
01589 /* ldh $dr,@($sr,$slo16) */
01590   {
01591     { 0, 0, 0, 0 },
01592     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01593     & ifmt_ldh_d2, { 0xa0a00000 }
01594   },
01595 /* ldub $dr,@($sr) */
01596   {
01597     { 0, 0, 0, 0 },
01598     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01599     & ifmt_ldub_2, { 0x2090 }
01600   },
01601 /* ldub $dr,@($sr,$slo16) */
01602   {
01603     { 0, 0, 0, 0 },
01604     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01605     & ifmt_ldub_d2, { 0xa0900000 }
01606   },
01607 /* lduh $dr,@($sr) */
01608   {
01609     { 0, 0, 0, 0 },
01610     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01611     & ifmt_lduh_2, { 0x20b0 }
01612   },
01613 /* lduh $dr,@($sr,$slo16) */
01614   {
01615     { 0, 0, 0, 0 },
01616     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01617     & ifmt_lduh_d2, { 0xa0b00000 }
01618   },
01619 /* pop $dr */
01620   {
01621     { 0, 0, 0, 0 },
01622     { { MNEM, ' ', OP (DR), 0 } },
01623     & ifmt_pop, { 0x20ef }
01624   },
01625 /* ldi $dr,$simm8 */
01626   {
01627     { 0, 0, 0, 0 },
01628     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
01629     & ifmt_ldi8a, { 0x6000 }
01630   },
01631 /* ldi $dr,$hash$slo16 */
01632   {
01633     { 0, 0, 0, 0 },
01634     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
01635     & ifmt_ldi16a, { 0x90f00000 }
01636   },
01637 /* rac $accd */
01638   {
01639     { 0, 0, 0, 0 },
01640     { { MNEM, ' ', OP (ACCD), 0 } },
01641     & ifmt_rac_d, { 0x5090 }
01642   },
01643 /* rac $accd,$accs */
01644   {
01645     { 0, 0, 0, 0 },
01646     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
01647     & ifmt_rac_ds, { 0x5090 }
01648   },
01649 /* rach $accd */
01650   {
01651     { 0, 0, 0, 0 },
01652     { { MNEM, ' ', OP (ACCD), 0 } },
01653     & ifmt_rach_d, { 0x5080 }
01654   },
01655 /* rach $accd,$accs */
01656   {
01657     { 0, 0, 0, 0 },
01658     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
01659     & ifmt_rach_ds, { 0x5080 }
01660   },
01661 /* st $src1,@($src2) */
01662   {
01663     { 0, 0, 0, 0 },
01664     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
01665     & ifmt_st_2, { 0x2040 }
01666   },
01667 /* st $src1,@($src2,$slo16) */
01668   {
01669     { 0, 0, 0, 0 },
01670     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
01671     & ifmt_st_d2, { 0xa0400000 }
01672   },
01673 /* stb $src1,@($src2) */
01674   {
01675     { 0, 0, 0, 0 },
01676     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
01677     & ifmt_stb_2, { 0x2000 }
01678   },
01679 /* stb $src1,@($src2,$slo16) */
01680   {
01681     { 0, 0, 0, 0 },
01682     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
01683     & ifmt_stb_d2, { 0xa0000000 }
01684   },
01685 /* sth $src1,@($src2) */
01686   {
01687     { 0, 0, 0, 0 },
01688     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
01689     & ifmt_sth_2, { 0x2020 }
01690   },
01691 /* sth $src1,@($src2,$slo16) */
01692   {
01693     { 0, 0, 0, 0 },
01694     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
01695     & ifmt_sth_d2, { 0xa0200000 }
01696   },
01697 /* push $src1 */
01698   {
01699     { 0, 0, 0, 0 },
01700     { { MNEM, ' ', OP (SRC1), 0 } },
01701     & ifmt_push, { 0x207f }
01702   },
01703 };
01704 
01705 #undef A
01706 #undef OPERAND
01707 #undef MNEM
01708 #undef OP
01709 
01710 #ifndef CGEN_ASM_HASH_P
01711 #define CGEN_ASM_HASH_P(insn) 1
01712 #endif
01713 
01714 #ifndef CGEN_DIS_HASH_P
01715 #define CGEN_DIS_HASH_P(insn) 1
01716 #endif
01717 
01718 /* Return non-zero if INSN is to be added to the hash table.
01719    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
01720 
01721 static int
01722 asm_hash_insn_p (insn)
01723      const CGEN_INSN *insn ATTRIBUTE_UNUSED;
01724 {
01725   return CGEN_ASM_HASH_P (insn);
01726 }
01727 
01728 static int
01729 dis_hash_insn_p (insn)
01730      const CGEN_INSN *insn;
01731 {
01732   /* If building the hash table and the NO-DIS attribute is present,
01733      ignore.  */
01734   if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
01735     return 0;
01736   return CGEN_DIS_HASH_P (insn);
01737 }
01738 
01739 #ifndef CGEN_ASM_HASH
01740 #define CGEN_ASM_HASH_SIZE 127
01741 #ifdef CGEN_MNEMONIC_OPERANDS
01742 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
01743 #else
01744 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
01745 #endif
01746 #endif
01747 
01748 /* It doesn't make much sense to provide a default here,
01749    but while this is under development we do.
01750    BUFFER is a pointer to the bytes of the insn, target order.
01751    VALUE is the first base_insn_bitsize bits as an int in host order.  */
01752 
01753 #ifndef CGEN_DIS_HASH
01754 #define CGEN_DIS_HASH_SIZE 256
01755 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
01756 #endif
01757 
01758 /* The result is the hash value of the insn.
01759    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
01760 
01761 static unsigned int
01762 asm_hash_insn (mnem)
01763      const char * mnem;
01764 {
01765   return CGEN_ASM_HASH (mnem);
01766 }
01767 
01768 /* BUF is a pointer to the bytes of the insn, target order.
01769    VALUE is the first base_insn_bitsize bits as an int in host order.  */
01770 
01771 static unsigned int
01772 dis_hash_insn (buf, value)
01773      const char * buf ATTRIBUTE_UNUSED;
01774      CGEN_INSN_INT value ATTRIBUTE_UNUSED;
01775 {
01776   return CGEN_DIS_HASH (buf, value);
01777 }
01778 
01779 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
01780 
01781 static void
01782 set_fields_bitsize (CGEN_FIELDS *fields, int size)
01783 {
01784   CGEN_FIELDS_BITSIZE (fields) = size;
01785 }
01786 
01787 /* Function to call before using the operand instance table.
01788    This plugs the opcode entries and macro instructions into the cpu table.  */
01789 
01790 void
01791 m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd)
01792 {
01793   int i;
01794   int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
01795                   sizeof (m32r_cgen_macro_insn_table[0]));
01796   const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
01797   const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
01798   CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
01799 
01800   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
01801   for (i = 0; i < num_macros; ++i)
01802     {
01803       insns[i].base = &ib[i];
01804       insns[i].opcode = &oc[i];
01805       m32r_cgen_build_insn_regex (& insns[i]);
01806     }
01807   cd->macro_insn_table.init_entries = insns;
01808   cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
01809   cd->macro_insn_table.num_init_entries = num_macros;
01810 
01811   oc = & m32r_cgen_insn_opcode_table[0];
01812   insns = (CGEN_INSN *) cd->insn_table.init_entries;
01813   for (i = 0; i < MAX_INSNS; ++i)
01814     {
01815       insns[i].opcode = &oc[i];
01816       m32r_cgen_build_insn_regex (& insns[i]);
01817     }
01818 
01819   cd->sizeof_fields = sizeof (CGEN_FIELDS);
01820   cd->set_fields_bitsize = set_fields_bitsize;
01821 
01822   cd->asm_hash_p = asm_hash_insn_p;
01823   cd->asm_hash = asm_hash_insn;
01824   cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
01825 
01826   cd->dis_hash_p = dis_hash_insn_p;
01827   cd->dis_hash = dis_hash_insn;
01828   cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
01829 }