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cell-binutils  2.17cvs20070401
m32r-ibld.c
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00001 /* Instruction building/extraction support for m32r. -*- C -*-
00002 
00003    THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
00004    - the resultant file is machine generated, cgen-ibld.in isn't
00005 
00006    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006
00007    Free Software Foundation, Inc.
00008 
00009    This file is part of the GNU Binutils and GDB, the GNU debugger.
00010 
00011    This program is free software; you can redistribute it and/or modify
00012    it under the terms of the GNU General Public License as published by
00013    the Free Software Foundation; either version 2, or (at your option)
00014    any later version.
00015 
00016    This program is distributed in the hope that it will be useful,
00017    but WITHOUT ANY WARRANTY; without even the implied warranty of
00018    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019    GNU General Public License for more details.
00020 
00021    You should have received a copy of the GNU General Public License
00022    along with this program; if not, write to the Free Software Foundation, Inc.,
00023    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00024 
00025 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
00026    Keep that in mind.  */
00027 
00028 #include "sysdep.h"
00029 #include <stdio.h>
00030 #include "ansidecl.h"
00031 #include "dis-asm.h"
00032 #include "bfd.h"
00033 #include "symcat.h"
00034 #include "m32r-desc.h"
00035 #include "m32r-opc.h"
00036 #include "opintl.h"
00037 #include "safe-ctype.h"
00038 
00039 #undef  min
00040 #define min(a,b) ((a) < (b) ? (a) : (b))
00041 #undef  max
00042 #define max(a,b) ((a) > (b) ? (a) : (b))
00043 
00044 /* Used by the ifield rtx function.  */
00045 #define FLD(f) (fields->f)
00046 
00047 static const char * insert_normal
00048   (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
00049    unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
00050 static const char * insert_insn_normal
00051   (CGEN_CPU_DESC, const CGEN_INSN *,
00052    CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
00053 static int extract_normal
00054   (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
00055    unsigned int, unsigned int, unsigned int, unsigned int,
00056    unsigned int, unsigned int, bfd_vma, long *);
00057 static int extract_insn_normal
00058   (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
00059    CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
00060 #if CGEN_INT_INSN_P
00061 static void put_insn_int_value
00062   (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
00063 #endif
00064 #if ! CGEN_INT_INSN_P
00065 static CGEN_INLINE void insert_1
00066   (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
00067 static CGEN_INLINE int fill_cache
00068   (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
00069 static CGEN_INLINE long extract_1
00070   (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
00071 #endif
00072 
00073 /* Operand insertion.  */
00074 
00075 #if ! CGEN_INT_INSN_P
00076 
00077 /* Subroutine of insert_normal.  */
00078 
00079 static CGEN_INLINE void
00080 insert_1 (CGEN_CPU_DESC cd,
00081          unsigned long value,
00082          int start,
00083          int length,
00084          int word_length,
00085          unsigned char *bufp)
00086 {
00087   unsigned long x,mask;
00088   int shift;
00089 
00090   x = cgen_get_insn_value (cd, bufp, word_length);
00091 
00092   /* Written this way to avoid undefined behaviour.  */
00093   mask = (((1L << (length - 1)) - 1) << 1) | 1;
00094   if (CGEN_INSN_LSB0_P)
00095     shift = (start + 1) - length;
00096   else
00097     shift = (word_length - (start + length));
00098   x = (x & ~(mask << shift)) | ((value & mask) << shift);
00099 
00100   cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
00101 }
00102 
00103 #endif /* ! CGEN_INT_INSN_P */
00104 
00105 /* Default insertion routine.
00106 
00107    ATTRS is a mask of the boolean attributes.
00108    WORD_OFFSET is the offset in bits from the start of the insn of the value.
00109    WORD_LENGTH is the length of the word in bits in which the value resides.
00110    START is the starting bit number in the word, architecture origin.
00111    LENGTH is the length of VALUE in bits.
00112    TOTAL_LENGTH is the total length of the insn in bits.
00113 
00114    The result is an error message or NULL if success.  */
00115 
00116 /* ??? This duplicates functionality with bfd's howto table and
00117    bfd_install_relocation.  */
00118 /* ??? This doesn't handle bfd_vma's.  Create another function when
00119    necessary.  */
00120 
00121 static const char *
00122 insert_normal (CGEN_CPU_DESC cd,
00123               long value,
00124               unsigned int attrs,
00125               unsigned int word_offset,
00126               unsigned int start,
00127               unsigned int length,
00128               unsigned int word_length,
00129               unsigned int total_length,
00130               CGEN_INSN_BYTES_PTR buffer)
00131 {
00132   static char errbuf[100];
00133   /* Written this way to avoid undefined behaviour.  */
00134   unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
00135 
00136   /* If LENGTH is zero, this operand doesn't contribute to the value.  */
00137   if (length == 0)
00138     return NULL;
00139 
00140   if (word_length > 32)
00141     abort ();
00142 
00143   /* For architectures with insns smaller than the base-insn-bitsize,
00144      word_length may be too big.  */
00145   if (cd->min_insn_bitsize < cd->base_insn_bitsize)
00146     {
00147       if (word_offset == 0
00148          && word_length > total_length)
00149        word_length = total_length;
00150     }
00151 
00152   /* Ensure VALUE will fit.  */
00153   if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
00154     {
00155       long minval = - (1L << (length - 1));
00156       unsigned long maxval = mask;
00157       
00158       if ((value > 0 && (unsigned long) value > maxval)
00159          || value < minval)
00160        {
00161          /* xgettext:c-format */
00162          sprintf (errbuf,
00163                  _("operand out of range (%ld not between %ld and %lu)"),
00164                  value, minval, maxval);
00165          return errbuf;
00166        }
00167     }
00168   else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
00169     {
00170       unsigned long maxval = mask;
00171       unsigned long val = (unsigned long) value;
00172 
00173       /* For hosts with a word size > 32 check to see if value has been sign
00174         extended beyond 32 bits.  If so then ignore these higher sign bits
00175         as the user is attempting to store a 32-bit signed value into an
00176         unsigned 32-bit field which is allowed.  */
00177       if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
00178        val &= 0xFFFFFFFF;
00179 
00180       if (val > maxval)
00181        {
00182          /* xgettext:c-format */
00183          sprintf (errbuf,
00184                  _("operand out of range (0x%lx not between 0 and 0x%lx)"),
00185                  val, maxval);
00186          return errbuf;
00187        }
00188     }
00189   else
00190     {
00191       if (! cgen_signed_overflow_ok_p (cd))
00192        {
00193          long minval = - (1L << (length - 1));
00194          long maxval =   (1L << (length - 1)) - 1;
00195          
00196          if (value < minval || value > maxval)
00197            {
00198              sprintf
00199               /* xgettext:c-format */
00200               (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
00201                value, minval, maxval);
00202              return errbuf;
00203            }
00204        }
00205     }
00206 
00207 #if CGEN_INT_INSN_P
00208 
00209   {
00210     int shift;
00211 
00212     if (CGEN_INSN_LSB0_P)
00213       shift = (word_offset + start + 1) - length;
00214     else
00215       shift = total_length - (word_offset + start + length);
00216     *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
00217   }
00218 
00219 #else /* ! CGEN_INT_INSN_P */
00220 
00221   {
00222     unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
00223 
00224     insert_1 (cd, value, start, length, word_length, bufp);
00225   }
00226 
00227 #endif /* ! CGEN_INT_INSN_P */
00228 
00229   return NULL;
00230 }
00231 
00232 /* Default insn builder (insert handler).
00233    The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
00234    that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
00235    recorded in host byte order, otherwise BUFFER is an array of bytes
00236    and the value is recorded in target byte order).
00237    The result is an error message or NULL if success.  */
00238 
00239 static const char *
00240 insert_insn_normal (CGEN_CPU_DESC cd,
00241                   const CGEN_INSN * insn,
00242                   CGEN_FIELDS * fields,
00243                   CGEN_INSN_BYTES_PTR buffer,
00244                   bfd_vma pc)
00245 {
00246   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
00247   unsigned long value;
00248   const CGEN_SYNTAX_CHAR_TYPE * syn;
00249 
00250   CGEN_INIT_INSERT (cd);
00251   value = CGEN_INSN_BASE_VALUE (insn);
00252 
00253   /* If we're recording insns as numbers (rather than a string of bytes),
00254      target byte order handling is deferred until later.  */
00255 
00256 #if CGEN_INT_INSN_P
00257 
00258   put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
00259                     CGEN_FIELDS_BITSIZE (fields), value);
00260 
00261 #else
00262 
00263   cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
00264                                    (unsigned) CGEN_FIELDS_BITSIZE (fields)),
00265                      value);
00266 
00267 #endif /* ! CGEN_INT_INSN_P */
00268 
00269   /* ??? It would be better to scan the format's fields.
00270      Still need to be able to insert a value based on the operand though;
00271      e.g. storing a branch displacement that got resolved later.
00272      Needs more thought first.  */
00273 
00274   for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
00275     {
00276       const char *errmsg;
00277 
00278       if (CGEN_SYNTAX_CHAR_P (* syn))
00279        continue;
00280 
00281       errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
00282                                    fields, buffer, pc);
00283       if (errmsg)
00284        return errmsg;
00285     }
00286 
00287   return NULL;
00288 }
00289 
00290 #if CGEN_INT_INSN_P
00291 /* Cover function to store an insn value into an integral insn.  Must go here
00292    because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
00293 
00294 static void
00295 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00296                   CGEN_INSN_BYTES_PTR buf,
00297                   int length,
00298                   int insn_length,
00299                   CGEN_INSN_INT value)
00300 {
00301   /* For architectures with insns smaller than the base-insn-bitsize,
00302      length may be too big.  */
00303   if (length > insn_length)
00304     *buf = value;
00305   else
00306     {
00307       int shift = insn_length - length;
00308       /* Written this way to avoid undefined behaviour.  */
00309       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
00310 
00311       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
00312     }
00313 }
00314 #endif
00315 
00316 /* Operand extraction.  */
00317 
00318 #if ! CGEN_INT_INSN_P
00319 
00320 /* Subroutine of extract_normal.
00321    Ensure sufficient bytes are cached in EX_INFO.
00322    OFFSET is the offset in bytes from the start of the insn of the value.
00323    BYTES is the length of the needed value.
00324    Returns 1 for success, 0 for failure.  */
00325 
00326 static CGEN_INLINE int
00327 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00328            CGEN_EXTRACT_INFO *ex_info,
00329            int offset,
00330            int bytes,
00331            bfd_vma pc)
00332 {
00333   /* It's doubtful that the middle part has already been fetched so
00334      we don't optimize that case.  kiss.  */
00335   unsigned int mask;
00336   disassemble_info *info = (disassemble_info *) ex_info->dis_info;
00337 
00338   /* First do a quick check.  */
00339   mask = (1 << bytes) - 1;
00340   if (((ex_info->valid >> offset) & mask) == mask)
00341     return 1;
00342 
00343   /* Search for the first byte we need to read.  */
00344   for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
00345     if (! (mask & ex_info->valid))
00346       break;
00347 
00348   if (bytes)
00349     {
00350       int status;
00351 
00352       pc += offset;
00353       status = (*info->read_memory_func)
00354        (pc, ex_info->insn_bytes + offset, bytes, info);
00355 
00356       if (status != 0)
00357        {
00358          (*info->memory_error_func) (status, pc, info);
00359          return 0;
00360        }
00361 
00362       ex_info->valid |= ((1 << bytes) - 1) << offset;
00363     }
00364 
00365   return 1;
00366 }
00367 
00368 /* Subroutine of extract_normal.  */
00369 
00370 static CGEN_INLINE long
00371 extract_1 (CGEN_CPU_DESC cd,
00372           CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
00373           int start,
00374           int length,
00375           int word_length,
00376           unsigned char *bufp,
00377           bfd_vma pc ATTRIBUTE_UNUSED)
00378 {
00379   unsigned long x;
00380   int shift;
00381 
00382   x = cgen_get_insn_value (cd, bufp, word_length);
00383 
00384   if (CGEN_INSN_LSB0_P)
00385     shift = (start + 1) - length;
00386   else
00387     shift = (word_length - (start + length));
00388   return x >> shift;
00389 }
00390 
00391 #endif /* ! CGEN_INT_INSN_P */
00392 
00393 /* Default extraction routine.
00394 
00395    INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
00396    or sometimes less for cases like the m32r where the base insn size is 32
00397    but some insns are 16 bits.
00398    ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
00399    but for generality we take a bitmask of all of them.
00400    WORD_OFFSET is the offset in bits from the start of the insn of the value.
00401    WORD_LENGTH is the length of the word in bits in which the value resides.
00402    START is the starting bit number in the word, architecture origin.
00403    LENGTH is the length of VALUE in bits.
00404    TOTAL_LENGTH is the total length of the insn in bits.
00405 
00406    Returns 1 for success, 0 for failure.  */
00407 
00408 /* ??? The return code isn't properly used.  wip.  */
00409 
00410 /* ??? This doesn't handle bfd_vma's.  Create another function when
00411    necessary.  */
00412 
00413 static int
00414 extract_normal (CGEN_CPU_DESC cd,
00415 #if ! CGEN_INT_INSN_P
00416               CGEN_EXTRACT_INFO *ex_info,
00417 #else
00418               CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
00419 #endif
00420               CGEN_INSN_INT insn_value,
00421               unsigned int attrs,
00422               unsigned int word_offset,
00423               unsigned int start,
00424               unsigned int length,
00425               unsigned int word_length,
00426               unsigned int total_length,
00427 #if ! CGEN_INT_INSN_P
00428               bfd_vma pc,
00429 #else
00430               bfd_vma pc ATTRIBUTE_UNUSED,
00431 #endif
00432               long *valuep)
00433 {
00434   long value, mask;
00435 
00436   /* If LENGTH is zero, this operand doesn't contribute to the value
00437      so give it a standard value of zero.  */
00438   if (length == 0)
00439     {
00440       *valuep = 0;
00441       return 1;
00442     }
00443 
00444   if (word_length > 32)
00445     abort ();
00446 
00447   /* For architectures with insns smaller than the insn-base-bitsize,
00448      word_length may be too big.  */
00449   if (cd->min_insn_bitsize < cd->base_insn_bitsize)
00450     {
00451       if (word_offset + word_length > total_length)
00452        word_length = total_length - word_offset;
00453     }
00454 
00455   /* Does the value reside in INSN_VALUE, and at the right alignment?  */
00456 
00457   if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
00458     {
00459       if (CGEN_INSN_LSB0_P)
00460        value = insn_value >> ((word_offset + start + 1) - length);
00461       else
00462        value = insn_value >> (total_length - ( word_offset + start + length));
00463     }
00464 
00465 #if ! CGEN_INT_INSN_P
00466 
00467   else
00468     {
00469       unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
00470 
00471       if (word_length > 32)
00472        abort ();
00473 
00474       if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
00475        return 0;
00476 
00477       value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
00478     }
00479 
00480 #endif /* ! CGEN_INT_INSN_P */
00481 
00482   /* Written this way to avoid undefined behaviour.  */
00483   mask = (((1L << (length - 1)) - 1) << 1) | 1;
00484 
00485   value &= mask;
00486   /* sign extend? */
00487   if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
00488       && (value & (1L << (length - 1))))
00489     value |= ~mask;
00490 
00491   *valuep = value;
00492 
00493   return 1;
00494 }
00495 
00496 /* Default insn extractor.
00497 
00498    INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
00499    The extracted fields are stored in FIELDS.
00500    EX_INFO is used to handle reading variable length insns.
00501    Return the length of the insn in bits, or 0 if no match,
00502    or -1 if an error occurs fetching data (memory_error_func will have
00503    been called).  */
00504 
00505 static int
00506 extract_insn_normal (CGEN_CPU_DESC cd,
00507                    const CGEN_INSN *insn,
00508                    CGEN_EXTRACT_INFO *ex_info,
00509                    CGEN_INSN_INT insn_value,
00510                    CGEN_FIELDS *fields,
00511                    bfd_vma pc)
00512 {
00513   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
00514   const CGEN_SYNTAX_CHAR_TYPE *syn;
00515 
00516   CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
00517 
00518   CGEN_INIT_EXTRACT (cd);
00519 
00520   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
00521     {
00522       int length;
00523 
00524       if (CGEN_SYNTAX_CHAR_P (*syn))
00525        continue;
00526 
00527       length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
00528                                    ex_info, insn_value, fields, pc);
00529       if (length <= 0)
00530        return length;
00531     }
00532 
00533   /* We recognized and successfully extracted this insn.  */
00534   return CGEN_INSN_BITSIZE (insn);
00535 }
00536 
00537 /* Machine generated code added here.  */
00538 
00539 const char * m32r_cgen_insert_operand
00540   (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
00541 
00542 /* Main entry point for operand insertion.
00543 
00544    This function is basically just a big switch statement.  Earlier versions
00545    used tables to look up the function to use, but
00546    - if the table contains both assembler and disassembler functions then
00547      the disassembler contains much of the assembler and vice-versa,
00548    - there's a lot of inlining possibilities as things grow,
00549    - using a switch statement avoids the function call overhead.
00550 
00551    This function could be moved into `parse_insn_normal', but keeping it
00552    separate makes clear the interface between `parse_insn_normal' and each of
00553    the handlers.  It's also needed by GAS to insert operands that couldn't be
00554    resolved during parsing.  */
00555 
00556 const char *
00557 m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
00558                           int opindex,
00559                           CGEN_FIELDS * fields,
00560                           CGEN_INSN_BYTES_PTR buffer,
00561                           bfd_vma pc ATTRIBUTE_UNUSED)
00562 {
00563   const char * errmsg = NULL;
00564   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
00565 
00566   switch (opindex)
00567     {
00568     case M32R_OPERAND_ACC :
00569       errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
00570       break;
00571     case M32R_OPERAND_ACCD :
00572       errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
00573       break;
00574     case M32R_OPERAND_ACCS :
00575       errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
00576       break;
00577     case M32R_OPERAND_DCR :
00578       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
00579       break;
00580     case M32R_OPERAND_DISP16 :
00581       {
00582         long value = fields->f_disp16;
00583         value = ((int) (((value) - (pc))) >> (2));
00584         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
00585       }
00586       break;
00587     case M32R_OPERAND_DISP24 :
00588       {
00589         long value = fields->f_disp24;
00590         value = ((int) (((value) - (pc))) >> (2));
00591         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
00592       }
00593       break;
00594     case M32R_OPERAND_DISP8 :
00595       {
00596         long value = fields->f_disp8;
00597         value = ((int) (((value) - (((pc) & (-4))))) >> (2));
00598         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
00599       }
00600       break;
00601     case M32R_OPERAND_DR :
00602       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
00603       break;
00604     case M32R_OPERAND_HASH :
00605       break;
00606     case M32R_OPERAND_HI16 :
00607       errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
00608       break;
00609     case M32R_OPERAND_IMM1 :
00610       {
00611         long value = fields->f_imm1;
00612         value = ((value) - (1));
00613         errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
00614       }
00615       break;
00616     case M32R_OPERAND_SCR :
00617       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
00618       break;
00619     case M32R_OPERAND_SIMM16 :
00620       errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
00621       break;
00622     case M32R_OPERAND_SIMM8 :
00623       errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
00624       break;
00625     case M32R_OPERAND_SLO16 :
00626       errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
00627       break;
00628     case M32R_OPERAND_SR :
00629       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
00630       break;
00631     case M32R_OPERAND_SRC1 :
00632       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
00633       break;
00634     case M32R_OPERAND_SRC2 :
00635       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
00636       break;
00637     case M32R_OPERAND_UIMM16 :
00638       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
00639       break;
00640     case M32R_OPERAND_UIMM24 :
00641       errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
00642       break;
00643     case M32R_OPERAND_UIMM3 :
00644       errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
00645       break;
00646     case M32R_OPERAND_UIMM4 :
00647       errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
00648       break;
00649     case M32R_OPERAND_UIMM5 :
00650       errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
00651       break;
00652     case M32R_OPERAND_UIMM8 :
00653       errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
00654       break;
00655     case M32R_OPERAND_ULO16 :
00656       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
00657       break;
00658 
00659     default :
00660       /* xgettext:c-format */
00661       fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
00662               opindex);
00663       abort ();
00664   }
00665 
00666   return errmsg;
00667 }
00668 
00669 int m32r_cgen_extract_operand
00670   (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
00671 
00672 /* Main entry point for operand extraction.
00673    The result is <= 0 for error, >0 for success.
00674    ??? Actual values aren't well defined right now.
00675 
00676    This function is basically just a big switch statement.  Earlier versions
00677    used tables to look up the function to use, but
00678    - if the table contains both assembler and disassembler functions then
00679      the disassembler contains much of the assembler and vice-versa,
00680    - there's a lot of inlining possibilities as things grow,
00681    - using a switch statement avoids the function call overhead.
00682 
00683    This function could be moved into `print_insn_normal', but keeping it
00684    separate makes clear the interface between `print_insn_normal' and each of
00685    the handlers.  */
00686 
00687 int
00688 m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
00689                           int opindex,
00690                           CGEN_EXTRACT_INFO *ex_info,
00691                           CGEN_INSN_INT insn_value,
00692                           CGEN_FIELDS * fields,
00693                           bfd_vma pc)
00694 {
00695   /* Assume success (for those operands that are nops).  */
00696   int length = 1;
00697   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
00698 
00699   switch (opindex)
00700     {
00701     case M32R_OPERAND_ACC :
00702       length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
00703       break;
00704     case M32R_OPERAND_ACCD :
00705       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
00706       break;
00707     case M32R_OPERAND_ACCS :
00708       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
00709       break;
00710     case M32R_OPERAND_DCR :
00711       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
00712       break;
00713     case M32R_OPERAND_DISP16 :
00714       {
00715         long value;
00716         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
00717         value = ((((value) << (2))) + (pc));
00718         fields->f_disp16 = value;
00719       }
00720       break;
00721     case M32R_OPERAND_DISP24 :
00722       {
00723         long value;
00724         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
00725         value = ((((value) << (2))) + (pc));
00726         fields->f_disp24 = value;
00727       }
00728       break;
00729     case M32R_OPERAND_DISP8 :
00730       {
00731         long value;
00732         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
00733         value = ((((value) << (2))) + (((pc) & (-4))));
00734         fields->f_disp8 = value;
00735       }
00736       break;
00737     case M32R_OPERAND_DR :
00738       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
00739       break;
00740     case M32R_OPERAND_HASH :
00741       break;
00742     case M32R_OPERAND_HI16 :
00743       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
00744       break;
00745     case M32R_OPERAND_IMM1 :
00746       {
00747         long value;
00748         length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
00749         value = ((value) + (1));
00750         fields->f_imm1 = value;
00751       }
00752       break;
00753     case M32R_OPERAND_SCR :
00754       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
00755       break;
00756     case M32R_OPERAND_SIMM16 :
00757       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
00758       break;
00759     case M32R_OPERAND_SIMM8 :
00760       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
00761       break;
00762     case M32R_OPERAND_SLO16 :
00763       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
00764       break;
00765     case M32R_OPERAND_SR :
00766       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
00767       break;
00768     case M32R_OPERAND_SRC1 :
00769       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
00770       break;
00771     case M32R_OPERAND_SRC2 :
00772       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
00773       break;
00774     case M32R_OPERAND_UIMM16 :
00775       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
00776       break;
00777     case M32R_OPERAND_UIMM24 :
00778       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
00779       break;
00780     case M32R_OPERAND_UIMM3 :
00781       length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
00782       break;
00783     case M32R_OPERAND_UIMM4 :
00784       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
00785       break;
00786     case M32R_OPERAND_UIMM5 :
00787       length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
00788       break;
00789     case M32R_OPERAND_UIMM8 :
00790       length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
00791       break;
00792     case M32R_OPERAND_ULO16 :
00793       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
00794       break;
00795 
00796     default :
00797       /* xgettext:c-format */
00798       fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
00799               opindex);
00800       abort ();
00801     }
00802 
00803   return length;
00804 }
00805 
00806 cgen_insert_fn * const m32r_cgen_insert_handlers[] = 
00807 {
00808   insert_insn_normal,
00809 };
00810 
00811 cgen_extract_fn * const m32r_cgen_extract_handlers[] = 
00812 {
00813   extract_insn_normal,
00814 };
00815 
00816 int m32r_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
00817 bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
00818 
00819 /* Getting values from cgen_fields is handled by a collection of functions.
00820    They are distinguished by the type of the VALUE argument they return.
00821    TODO: floating point, inlining support, remove cases where result type
00822    not appropriate.  */
00823 
00824 int
00825 m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00826                           int opindex,
00827                           const CGEN_FIELDS * fields)
00828 {
00829   int value;
00830 
00831   switch (opindex)
00832     {
00833     case M32R_OPERAND_ACC :
00834       value = fields->f_acc;
00835       break;
00836     case M32R_OPERAND_ACCD :
00837       value = fields->f_accd;
00838       break;
00839     case M32R_OPERAND_ACCS :
00840       value = fields->f_accs;
00841       break;
00842     case M32R_OPERAND_DCR :
00843       value = fields->f_r1;
00844       break;
00845     case M32R_OPERAND_DISP16 :
00846       value = fields->f_disp16;
00847       break;
00848     case M32R_OPERAND_DISP24 :
00849       value = fields->f_disp24;
00850       break;
00851     case M32R_OPERAND_DISP8 :
00852       value = fields->f_disp8;
00853       break;
00854     case M32R_OPERAND_DR :
00855       value = fields->f_r1;
00856       break;
00857     case M32R_OPERAND_HASH :
00858       value = 0;
00859       break;
00860     case M32R_OPERAND_HI16 :
00861       value = fields->f_hi16;
00862       break;
00863     case M32R_OPERAND_IMM1 :
00864       value = fields->f_imm1;
00865       break;
00866     case M32R_OPERAND_SCR :
00867       value = fields->f_r2;
00868       break;
00869     case M32R_OPERAND_SIMM16 :
00870       value = fields->f_simm16;
00871       break;
00872     case M32R_OPERAND_SIMM8 :
00873       value = fields->f_simm8;
00874       break;
00875     case M32R_OPERAND_SLO16 :
00876       value = fields->f_simm16;
00877       break;
00878     case M32R_OPERAND_SR :
00879       value = fields->f_r2;
00880       break;
00881     case M32R_OPERAND_SRC1 :
00882       value = fields->f_r1;
00883       break;
00884     case M32R_OPERAND_SRC2 :
00885       value = fields->f_r2;
00886       break;
00887     case M32R_OPERAND_UIMM16 :
00888       value = fields->f_uimm16;
00889       break;
00890     case M32R_OPERAND_UIMM24 :
00891       value = fields->f_uimm24;
00892       break;
00893     case M32R_OPERAND_UIMM3 :
00894       value = fields->f_uimm3;
00895       break;
00896     case M32R_OPERAND_UIMM4 :
00897       value = fields->f_uimm4;
00898       break;
00899     case M32R_OPERAND_UIMM5 :
00900       value = fields->f_uimm5;
00901       break;
00902     case M32R_OPERAND_UIMM8 :
00903       value = fields->f_uimm8;
00904       break;
00905     case M32R_OPERAND_ULO16 :
00906       value = fields->f_uimm16;
00907       break;
00908 
00909     default :
00910       /* xgettext:c-format */
00911       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
00912                      opindex);
00913       abort ();
00914   }
00915 
00916   return value;
00917 }
00918 
00919 bfd_vma
00920 m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00921                           int opindex,
00922                           const CGEN_FIELDS * fields)
00923 {
00924   bfd_vma value;
00925 
00926   switch (opindex)
00927     {
00928     case M32R_OPERAND_ACC :
00929       value = fields->f_acc;
00930       break;
00931     case M32R_OPERAND_ACCD :
00932       value = fields->f_accd;
00933       break;
00934     case M32R_OPERAND_ACCS :
00935       value = fields->f_accs;
00936       break;
00937     case M32R_OPERAND_DCR :
00938       value = fields->f_r1;
00939       break;
00940     case M32R_OPERAND_DISP16 :
00941       value = fields->f_disp16;
00942       break;
00943     case M32R_OPERAND_DISP24 :
00944       value = fields->f_disp24;
00945       break;
00946     case M32R_OPERAND_DISP8 :
00947       value = fields->f_disp8;
00948       break;
00949     case M32R_OPERAND_DR :
00950       value = fields->f_r1;
00951       break;
00952     case M32R_OPERAND_HASH :
00953       value = 0;
00954       break;
00955     case M32R_OPERAND_HI16 :
00956       value = fields->f_hi16;
00957       break;
00958     case M32R_OPERAND_IMM1 :
00959       value = fields->f_imm1;
00960       break;
00961     case M32R_OPERAND_SCR :
00962       value = fields->f_r2;
00963       break;
00964     case M32R_OPERAND_SIMM16 :
00965       value = fields->f_simm16;
00966       break;
00967     case M32R_OPERAND_SIMM8 :
00968       value = fields->f_simm8;
00969       break;
00970     case M32R_OPERAND_SLO16 :
00971       value = fields->f_simm16;
00972       break;
00973     case M32R_OPERAND_SR :
00974       value = fields->f_r2;
00975       break;
00976     case M32R_OPERAND_SRC1 :
00977       value = fields->f_r1;
00978       break;
00979     case M32R_OPERAND_SRC2 :
00980       value = fields->f_r2;
00981       break;
00982     case M32R_OPERAND_UIMM16 :
00983       value = fields->f_uimm16;
00984       break;
00985     case M32R_OPERAND_UIMM24 :
00986       value = fields->f_uimm24;
00987       break;
00988     case M32R_OPERAND_UIMM3 :
00989       value = fields->f_uimm3;
00990       break;
00991     case M32R_OPERAND_UIMM4 :
00992       value = fields->f_uimm4;
00993       break;
00994     case M32R_OPERAND_UIMM5 :
00995       value = fields->f_uimm5;
00996       break;
00997     case M32R_OPERAND_UIMM8 :
00998       value = fields->f_uimm8;
00999       break;
01000     case M32R_OPERAND_ULO16 :
01001       value = fields->f_uimm16;
01002       break;
01003 
01004     default :
01005       /* xgettext:c-format */
01006       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
01007                      opindex);
01008       abort ();
01009   }
01010 
01011   return value;
01012 }
01013 
01014 void m32r_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
01015 void m32r_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
01016 
01017 /* Stuffing values in cgen_fields is handled by a collection of functions.
01018    They are distinguished by the type of the VALUE argument they accept.
01019    TODO: floating point, inlining support, remove cases where argument type
01020    not appropriate.  */
01021 
01022 void
01023 m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
01024                           int opindex,
01025                           CGEN_FIELDS * fields,
01026                           int value)
01027 {
01028   switch (opindex)
01029     {
01030     case M32R_OPERAND_ACC :
01031       fields->f_acc = value;
01032       break;
01033     case M32R_OPERAND_ACCD :
01034       fields->f_accd = value;
01035       break;
01036     case M32R_OPERAND_ACCS :
01037       fields->f_accs = value;
01038       break;
01039     case M32R_OPERAND_DCR :
01040       fields->f_r1 = value;
01041       break;
01042     case M32R_OPERAND_DISP16 :
01043       fields->f_disp16 = value;
01044       break;
01045     case M32R_OPERAND_DISP24 :
01046       fields->f_disp24 = value;
01047       break;
01048     case M32R_OPERAND_DISP8 :
01049       fields->f_disp8 = value;
01050       break;
01051     case M32R_OPERAND_DR :
01052       fields->f_r1 = value;
01053       break;
01054     case M32R_OPERAND_HASH :
01055       break;
01056     case M32R_OPERAND_HI16 :
01057       fields->f_hi16 = value;
01058       break;
01059     case M32R_OPERAND_IMM1 :
01060       fields->f_imm1 = value;
01061       break;
01062     case M32R_OPERAND_SCR :
01063       fields->f_r2 = value;
01064       break;
01065     case M32R_OPERAND_SIMM16 :
01066       fields->f_simm16 = value;
01067       break;
01068     case M32R_OPERAND_SIMM8 :
01069       fields->f_simm8 = value;
01070       break;
01071     case M32R_OPERAND_SLO16 :
01072       fields->f_simm16 = value;
01073       break;
01074     case M32R_OPERAND_SR :
01075       fields->f_r2 = value;
01076       break;
01077     case M32R_OPERAND_SRC1 :
01078       fields->f_r1 = value;
01079       break;
01080     case M32R_OPERAND_SRC2 :
01081       fields->f_r2 = value;
01082       break;
01083     case M32R_OPERAND_UIMM16 :
01084       fields->f_uimm16 = value;
01085       break;
01086     case M32R_OPERAND_UIMM24 :
01087       fields->f_uimm24 = value;
01088       break;
01089     case M32R_OPERAND_UIMM3 :
01090       fields->f_uimm3 = value;
01091       break;
01092     case M32R_OPERAND_UIMM4 :
01093       fields->f_uimm4 = value;
01094       break;
01095     case M32R_OPERAND_UIMM5 :
01096       fields->f_uimm5 = value;
01097       break;
01098     case M32R_OPERAND_UIMM8 :
01099       fields->f_uimm8 = value;
01100       break;
01101     case M32R_OPERAND_ULO16 :
01102       fields->f_uimm16 = value;
01103       break;
01104 
01105     default :
01106       /* xgettext:c-format */
01107       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
01108                      opindex);
01109       abort ();
01110   }
01111 }
01112 
01113 void
01114 m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
01115                           int opindex,
01116                           CGEN_FIELDS * fields,
01117                           bfd_vma value)
01118 {
01119   switch (opindex)
01120     {
01121     case M32R_OPERAND_ACC :
01122       fields->f_acc = value;
01123       break;
01124     case M32R_OPERAND_ACCD :
01125       fields->f_accd = value;
01126       break;
01127     case M32R_OPERAND_ACCS :
01128       fields->f_accs = value;
01129       break;
01130     case M32R_OPERAND_DCR :
01131       fields->f_r1 = value;
01132       break;
01133     case M32R_OPERAND_DISP16 :
01134       fields->f_disp16 = value;
01135       break;
01136     case M32R_OPERAND_DISP24 :
01137       fields->f_disp24 = value;
01138       break;
01139     case M32R_OPERAND_DISP8 :
01140       fields->f_disp8 = value;
01141       break;
01142     case M32R_OPERAND_DR :
01143       fields->f_r1 = value;
01144       break;
01145     case M32R_OPERAND_HASH :
01146       break;
01147     case M32R_OPERAND_HI16 :
01148       fields->f_hi16 = value;
01149       break;
01150     case M32R_OPERAND_IMM1 :
01151       fields->f_imm1 = value;
01152       break;
01153     case M32R_OPERAND_SCR :
01154       fields->f_r2 = value;
01155       break;
01156     case M32R_OPERAND_SIMM16 :
01157       fields->f_simm16 = value;
01158       break;
01159     case M32R_OPERAND_SIMM8 :
01160       fields->f_simm8 = value;
01161       break;
01162     case M32R_OPERAND_SLO16 :
01163       fields->f_simm16 = value;
01164       break;
01165     case M32R_OPERAND_SR :
01166       fields->f_r2 = value;
01167       break;
01168     case M32R_OPERAND_SRC1 :
01169       fields->f_r1 = value;
01170       break;
01171     case M32R_OPERAND_SRC2 :
01172       fields->f_r2 = value;
01173       break;
01174     case M32R_OPERAND_UIMM16 :
01175       fields->f_uimm16 = value;
01176       break;
01177     case M32R_OPERAND_UIMM24 :
01178       fields->f_uimm24 = value;
01179       break;
01180     case M32R_OPERAND_UIMM3 :
01181       fields->f_uimm3 = value;
01182       break;
01183     case M32R_OPERAND_UIMM4 :
01184       fields->f_uimm4 = value;
01185       break;
01186     case M32R_OPERAND_UIMM5 :
01187       fields->f_uimm5 = value;
01188       break;
01189     case M32R_OPERAND_UIMM8 :
01190       fields->f_uimm8 = value;
01191       break;
01192     case M32R_OPERAND_ULO16 :
01193       fields->f_uimm16 = value;
01194       break;
01195 
01196     default :
01197       /* xgettext:c-format */
01198       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
01199                      opindex);
01200       abort ();
01201   }
01202 }
01203 
01204 /* Function to call before using the instruction builder tables.  */
01205 
01206 void
01207 m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
01208 {
01209   cd->insert_handlers = & m32r_cgen_insert_handlers[0];
01210   cd->extract_handlers = & m32r_cgen_extract_handlers[0];
01211 
01212   cd->insert_operand = m32r_cgen_insert_operand;
01213   cd->extract_operand = m32r_cgen_extract_operand;
01214 
01215   cd->get_int_operand = m32r_cgen_get_int_operand;
01216   cd->set_int_operand = m32r_cgen_set_int_operand;
01217   cd->get_vma_operand = m32r_cgen_get_vma_operand;
01218   cd->set_vma_operand = m32r_cgen_set_vma_operand;
01219 }