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cell-binutils  2.17cvs20070401
m32r-dis.c
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00001 /* Disassembler interface for targets using CGEN. -*- C -*-
00002    CGEN: Cpu tools GENerator
00003 
00004    THIS FILE IS MACHINE GENERATED WITH CGEN.
00005    - the resultant file is machine generated, cgen-dis.in isn't
00006 
00007    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
00008    Free Software Foundation, Inc.
00009 
00010    This file is part of the GNU Binutils and GDB, the GNU debugger.
00011 
00012    This program is free software; you can redistribute it and/or modify
00013    it under the terms of the GNU General Public License as published by
00014    the Free Software Foundation; either version 2, or (at your option)
00015    any later version.
00016 
00017    This program is distributed in the hope that it will be useful,
00018    but WITHOUT ANY WARRANTY; without even the implied warranty of
00019    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00020    GNU General Public License for more details.
00021 
00022    You should have received a copy of the GNU General Public License
00023    along with this program; if not, write to the Free Software Foundation, Inc.,
00024    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00025 
00026 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
00027    Keep that in mind.  */
00028 
00029 #include "sysdep.h"
00030 #include <stdio.h>
00031 #include "ansidecl.h"
00032 #include "dis-asm.h"
00033 #include "bfd.h"
00034 #include "symcat.h"
00035 #include "libiberty.h"
00036 #include "m32r-desc.h"
00037 #include "m32r-opc.h"
00038 #include "opintl.h"
00039 
00040 /* Default text to print if an instruction isn't recognized.  */
00041 #define UNKNOWN_INSN_MSG _("*unknown*")
00042 
00043 static void print_normal
00044   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
00045 static void print_address
00046   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
00047 static void print_keyword
00048   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
00049 static void print_insn_normal
00050   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
00051 static int print_insn
00052   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
00053 static int default_print_insn
00054   (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
00055 static int read_insn
00056   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
00057    unsigned long *);
00058 
00059 /* -- disassembler routines inserted here.  */
00060 
00061 /* -- dis.c */
00062 /* Immediate values are prefixed with '#'.  */
00063 
00064 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)  \
00065   do                                                    \
00066     {                                                   \
00067       if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX))  \
00068        (*info->fprintf_func) (info->stream, "#");              \
00069     }                                                   \
00070   while (0)
00071 
00072 /* Handle '#' prefixes as operands.  */
00073 
00074 static void
00075 print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00076            void * dis_info,
00077            long value ATTRIBUTE_UNUSED,
00078            unsigned int attrs ATTRIBUTE_UNUSED,
00079            bfd_vma pc ATTRIBUTE_UNUSED,
00080            int length ATTRIBUTE_UNUSED)
00081 {
00082   disassemble_info *info = (disassemble_info *) dis_info;
00083 
00084   (*info->fprintf_func) (info->stream, "#");
00085 }
00086 
00087 #undef  CGEN_PRINT_INSN
00088 #define CGEN_PRINT_INSN my_print_insn
00089 
00090 static int
00091 my_print_insn (CGEN_CPU_DESC cd,
00092               bfd_vma pc,
00093               disassemble_info *info)
00094 {
00095   bfd_byte buffer[CGEN_MAX_INSN_SIZE];
00096   bfd_byte *buf = buffer;
00097   int status;
00098   int buflen = (pc & 3) == 0 ? 4 : 2;
00099   int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
00100   bfd_byte *x;
00101 
00102   /* Read the base part of the insn.  */
00103 
00104   status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
00105                                   buf, buflen, info);
00106   if (status != 0)
00107     {
00108       (*info->memory_error_func) (status, pc, info);
00109       return -1;
00110     }
00111 
00112   /* 32 bit insn?  */
00113   x = (big_p ? &buf[0] : &buf[3]);
00114   if ((pc & 3) == 0 && (*x & 0x80) != 0)
00115     return print_insn (cd, pc, info, buf, buflen);
00116 
00117   /* Print the first insn.  */
00118   if ((pc & 3) == 0)
00119     {
00120       buf += (big_p ? 0 : 2);
00121       if (print_insn (cd, pc, info, buf, 2) == 0)
00122        (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
00123       buf += (big_p ? 2 : -2);
00124     }
00125 
00126   x = (big_p ? &buf[0] : &buf[1]);
00127   if (*x & 0x80)
00128     {
00129       /* Parallel.  */
00130       (*info->fprintf_func) (info->stream, " || ");
00131       *x &= 0x7f;
00132     }
00133   else
00134     (*info->fprintf_func) (info->stream, " -> ");
00135 
00136   /* The "& 3" is to pass a consistent address.
00137      Parallel insns arguably both begin on the word boundary.
00138      Also, branch insns are calculated relative to the word boundary.  */
00139   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
00140     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
00141 
00142   return (pc & 3) ? 2 : 4;
00143 }
00144 
00145 /* -- */
00146 
00147 void m32r_cgen_print_operand
00148   (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
00149 
00150 /* Main entry point for printing operands.
00151    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
00152    of dis-asm.h on cgen.h.
00153 
00154    This function is basically just a big switch statement.  Earlier versions
00155    used tables to look up the function to use, but
00156    - if the table contains both assembler and disassembler functions then
00157      the disassembler contains much of the assembler and vice-versa,
00158    - there's a lot of inlining possibilities as things grow,
00159    - using a switch statement avoids the function call overhead.
00160 
00161    This function could be moved into `print_insn_normal', but keeping it
00162    separate makes clear the interface between `print_insn_normal' and each of
00163    the handlers.  */
00164 
00165 void
00166 m32r_cgen_print_operand (CGEN_CPU_DESC cd,
00167                         int opindex,
00168                         void * xinfo,
00169                         CGEN_FIELDS *fields,
00170                         void const *attrs ATTRIBUTE_UNUSED,
00171                         bfd_vma pc,
00172                         int length)
00173 {
00174   disassemble_info *info = (disassemble_info *) xinfo;
00175 
00176   switch (opindex)
00177     {
00178     case M32R_OPERAND_ACC :
00179       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
00180       break;
00181     case M32R_OPERAND_ACCD :
00182       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
00183       break;
00184     case M32R_OPERAND_ACCS :
00185       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
00186       break;
00187     case M32R_OPERAND_DCR :
00188       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
00189       break;
00190     case M32R_OPERAND_DISP16 :
00191       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
00192       break;
00193     case M32R_OPERAND_DISP24 :
00194       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
00195       break;
00196     case M32R_OPERAND_DISP8 :
00197       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
00198       break;
00199     case M32R_OPERAND_DR :
00200       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
00201       break;
00202     case M32R_OPERAND_HASH :
00203       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
00204       break;
00205     case M32R_OPERAND_HI16 :
00206       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
00207       break;
00208     case M32R_OPERAND_IMM1 :
00209       print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00210       break;
00211     case M32R_OPERAND_SCR :
00212       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
00213       break;
00214     case M32R_OPERAND_SIMM16 :
00215       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00216       break;
00217     case M32R_OPERAND_SIMM8 :
00218       print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00219       break;
00220     case M32R_OPERAND_SLO16 :
00221       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
00222       break;
00223     case M32R_OPERAND_SR :
00224       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
00225       break;
00226     case M32R_OPERAND_SRC1 :
00227       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
00228       break;
00229     case M32R_OPERAND_SRC2 :
00230       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
00231       break;
00232     case M32R_OPERAND_UIMM16 :
00233       print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00234       break;
00235     case M32R_OPERAND_UIMM24 :
00236       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
00237       break;
00238     case M32R_OPERAND_UIMM3 :
00239       print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00240       break;
00241     case M32R_OPERAND_UIMM4 :
00242       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00243       break;
00244     case M32R_OPERAND_UIMM5 :
00245       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00246       break;
00247     case M32R_OPERAND_UIMM8 :
00248       print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
00249       break;
00250     case M32R_OPERAND_ULO16 :
00251       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
00252       break;
00253 
00254     default :
00255       /* xgettext:c-format */
00256       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
00257               opindex);
00258     abort ();
00259   }
00260 }
00261 
00262 cgen_print_fn * const m32r_cgen_print_handlers[] = 
00263 {
00264   print_insn_normal,
00265 };
00266 
00267 
00268 void
00269 m32r_cgen_init_dis (CGEN_CPU_DESC cd)
00270 {
00271   m32r_cgen_init_opcode_table (cd);
00272   m32r_cgen_init_ibld_table (cd);
00273   cd->print_handlers = & m32r_cgen_print_handlers[0];
00274   cd->print_operand = m32r_cgen_print_operand;
00275 }
00276 
00277 
00278 /* Default print handler.  */
00279 
00280 static void
00281 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00282              void *dis_info,
00283              long value,
00284              unsigned int attrs,
00285              bfd_vma pc ATTRIBUTE_UNUSED,
00286              int length ATTRIBUTE_UNUSED)
00287 {
00288   disassemble_info *info = (disassemble_info *) dis_info;
00289 
00290 #ifdef CGEN_PRINT_NORMAL
00291   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
00292 #endif
00293 
00294   /* Print the operand as directed by the attributes.  */
00295   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
00296     ; /* nothing to do */
00297   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
00298     (*info->fprintf_func) (info->stream, "%ld", value);
00299   else
00300     (*info->fprintf_func) (info->stream, "0x%lx", value);
00301 }
00302 
00303 /* Default address handler.  */
00304 
00305 static void
00306 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00307               void *dis_info,
00308               bfd_vma value,
00309               unsigned int attrs,
00310               bfd_vma pc ATTRIBUTE_UNUSED,
00311               int length ATTRIBUTE_UNUSED)
00312 {
00313   disassemble_info *info = (disassemble_info *) dis_info;
00314 
00315 #ifdef CGEN_PRINT_ADDRESS
00316   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
00317 #endif
00318 
00319   /* Print the operand as directed by the attributes.  */
00320   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
00321     ; /* Nothing to do.  */
00322   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
00323     (*info->print_address_func) (value, info);
00324   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
00325     (*info->print_address_func) (value, info);
00326   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
00327     (*info->fprintf_func) (info->stream, "%ld", (long) value);
00328   else
00329     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
00330 }
00331 
00332 /* Keyword print handler.  */
00333 
00334 static void
00335 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00336               void *dis_info,
00337               CGEN_KEYWORD *keyword_table,
00338               long value,
00339               unsigned int attrs ATTRIBUTE_UNUSED)
00340 {
00341   disassemble_info *info = (disassemble_info *) dis_info;
00342   const CGEN_KEYWORD_ENTRY *ke;
00343 
00344   ke = cgen_keyword_lookup_value (keyword_table, value);
00345   if (ke != NULL)
00346     (*info->fprintf_func) (info->stream, "%s", ke->name);
00347   else
00348     (*info->fprintf_func) (info->stream, "???");
00349 }
00350 
00351 /* Default insn printer.
00352 
00353    DIS_INFO is defined as `void *' so the disassembler needn't know anything
00354    about disassemble_info.  */
00355 
00356 static void
00357 print_insn_normal (CGEN_CPU_DESC cd,
00358                  void *dis_info,
00359                  const CGEN_INSN *insn,
00360                  CGEN_FIELDS *fields,
00361                  bfd_vma pc,
00362                  int length)
00363 {
00364   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
00365   disassemble_info *info = (disassemble_info *) dis_info;
00366   const CGEN_SYNTAX_CHAR_TYPE *syn;
00367 
00368   CGEN_INIT_PRINT (cd);
00369 
00370   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
00371     {
00372       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
00373        {
00374          (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
00375          continue;
00376        }
00377       if (CGEN_SYNTAX_CHAR_P (*syn))
00378        {
00379          (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
00380          continue;
00381        }
00382 
00383       /* We have an operand.  */
00384       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
00385                              fields, CGEN_INSN_ATTRS (insn), pc, length);
00386     }
00387 }
00388 
00389 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
00390    the extract info.
00391    Returns 0 if all is well, non-zero otherwise.  */
00392 
00393 static int
00394 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
00395           bfd_vma pc,
00396           disassemble_info *info,
00397           bfd_byte *buf,
00398           int buflen,
00399           CGEN_EXTRACT_INFO *ex_info,
00400           unsigned long *insn_value)
00401 {
00402   int status = (*info->read_memory_func) (pc, buf, buflen, info);
00403 
00404   if (status != 0)
00405     {
00406       (*info->memory_error_func) (status, pc, info);
00407       return -1;
00408     }
00409 
00410   ex_info->dis_info = info;
00411   ex_info->valid = (1 << buflen) - 1;
00412   ex_info->insn_bytes = buf;
00413 
00414   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
00415   return 0;
00416 }
00417 
00418 /* Utility to print an insn.
00419    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
00420    The result is the size of the insn in bytes or zero for an unknown insn
00421    or -1 if an error occurs fetching data (memory_error_func will have
00422    been called).  */
00423 
00424 static int
00425 print_insn (CGEN_CPU_DESC cd,
00426            bfd_vma pc,
00427            disassemble_info *info,
00428            bfd_byte *buf,
00429            unsigned int buflen)
00430 {
00431   CGEN_INSN_INT insn_value;
00432   const CGEN_INSN_LIST *insn_list;
00433   CGEN_EXTRACT_INFO ex_info;
00434   int basesize;
00435 
00436   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
00437   basesize = cd->base_insn_bitsize < buflen * 8 ?
00438                                      cd->base_insn_bitsize : buflen * 8;
00439   insn_value = cgen_get_insn_value (cd, buf, basesize);
00440 
00441 
00442   /* Fill in ex_info fields like read_insn would.  Don't actually call
00443      read_insn, since the incoming buffer is already read (and possibly
00444      modified a la m32r).  */
00445   ex_info.valid = (1 << buflen) - 1;
00446   ex_info.dis_info = info;
00447   ex_info.insn_bytes = buf;
00448 
00449   /* The instructions are stored in hash lists.
00450      Pick the first one and keep trying until we find the right one.  */
00451 
00452   insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
00453   while (insn_list != NULL)
00454     {
00455       const CGEN_INSN *insn = insn_list->insn;
00456       CGEN_FIELDS fields;
00457       int length;
00458       unsigned long insn_value_cropped;
00459 
00460 #ifdef CGEN_VALIDATE_INSN_SUPPORTED 
00461       /* Not needed as insn shouldn't be in hash lists if not supported.  */
00462       /* Supported by this cpu?  */
00463       if (! m32r_cgen_insn_supported (cd, insn))
00464         {
00465           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
00466          continue;
00467         }
00468 #endif
00469 
00470       /* Basic bit mask must be correct.  */
00471       /* ??? May wish to allow target to defer this check until the extract
00472         handler.  */
00473 
00474       /* Base size may exceed this instruction's size.  Extract the
00475          relevant part from the buffer. */
00476       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
00477          (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
00478        insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
00479                                       info->endian == BFD_ENDIAN_BIG);
00480       else
00481        insn_value_cropped = insn_value;
00482 
00483       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
00484          == CGEN_INSN_BASE_VALUE (insn))
00485        {
00486          /* Printing is handled in two passes.  The first pass parses the
00487             machine insn and extracts the fields.  The second pass prints
00488             them.  */
00489 
00490          /* Make sure the entire insn is loaded into insn_value, if it
00491             can fit.  */
00492          if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
00493              (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
00494            {
00495              unsigned long full_insn_value;
00496              int rc = read_insn (cd, pc, info, buf,
00497                               CGEN_INSN_BITSIZE (insn) / 8,
00498                               & ex_info, & full_insn_value);
00499              if (rc != 0)
00500               return rc;
00501              length = CGEN_EXTRACT_FN (cd, insn)
00502               (cd, insn, &ex_info, full_insn_value, &fields, pc);
00503            }
00504          else
00505            length = CGEN_EXTRACT_FN (cd, insn)
00506              (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
00507 
00508          /* Length < 0 -> error.  */
00509          if (length < 0)
00510            return length;
00511          if (length > 0)
00512            {
00513              CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
00514              /* Length is in bits, result is in bytes.  */
00515              return length / 8;
00516            }
00517        }
00518 
00519       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
00520     }
00521 
00522   return 0;
00523 }
00524 
00525 /* Default value for CGEN_PRINT_INSN.
00526    The result is the size of the insn in bytes or zero for an unknown insn
00527    or -1 if an error occured fetching bytes.  */
00528 
00529 #ifndef CGEN_PRINT_INSN
00530 #define CGEN_PRINT_INSN default_print_insn
00531 #endif
00532 
00533 static int
00534 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
00535 {
00536   bfd_byte buf[CGEN_MAX_INSN_SIZE];
00537   int buflen;
00538   int status;
00539 
00540   /* Attempt to read the base part of the insn.  */
00541   buflen = cd->base_insn_bitsize / 8;
00542   status = (*info->read_memory_func) (pc, buf, buflen, info);
00543 
00544   /* Try again with the minimum part, if min < base.  */
00545   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
00546     {
00547       buflen = cd->min_insn_bitsize / 8;
00548       status = (*info->read_memory_func) (pc, buf, buflen, info);
00549     }
00550 
00551   if (status != 0)
00552     {
00553       (*info->memory_error_func) (status, pc, info);
00554       return -1;
00555     }
00556 
00557   return print_insn (cd, pc, info, buf, buflen);
00558 }
00559 
00560 /* Main entry point.
00561    Print one instruction from PC on INFO->STREAM.
00562    Return the size of the instruction (in bytes).  */
00563 
00564 typedef struct cpu_desc_list
00565 {
00566   struct cpu_desc_list *next;
00567   CGEN_BITSET *isa;
00568   int mach;
00569   int endian;
00570   CGEN_CPU_DESC cd;
00571 } cpu_desc_list;
00572 
00573 int
00574 print_insn_m32r (bfd_vma pc, disassemble_info *info)
00575 {
00576   static cpu_desc_list *cd_list = 0;
00577   cpu_desc_list *cl = 0;
00578   static CGEN_CPU_DESC cd = 0;
00579   static CGEN_BITSET *prev_isa;
00580   static int prev_mach;
00581   static int prev_endian;
00582   int length;
00583   CGEN_BITSET *isa;
00584   int mach;
00585   int endian = (info->endian == BFD_ENDIAN_BIG
00586               ? CGEN_ENDIAN_BIG
00587               : CGEN_ENDIAN_LITTLE);
00588   enum bfd_architecture arch;
00589 
00590   /* ??? gdb will set mach but leave the architecture as "unknown" */
00591 #ifndef CGEN_BFD_ARCH
00592 #define CGEN_BFD_ARCH bfd_arch_m32r
00593 #endif
00594   arch = info->arch;
00595   if (arch == bfd_arch_unknown)
00596     arch = CGEN_BFD_ARCH;
00597    
00598   /* There's no standard way to compute the machine or isa number
00599      so we leave it to the target.  */
00600 #ifdef CGEN_COMPUTE_MACH
00601   mach = CGEN_COMPUTE_MACH (info);
00602 #else
00603   mach = info->mach;
00604 #endif
00605 
00606 #ifdef CGEN_COMPUTE_ISA
00607   {
00608     static CGEN_BITSET *permanent_isa;
00609 
00610     if (!permanent_isa)
00611       permanent_isa = cgen_bitset_create (MAX_ISAS);
00612     isa = permanent_isa;
00613     cgen_bitset_clear (isa);
00614     cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
00615   }
00616 #else
00617   isa = info->insn_sets;
00618 #endif
00619 
00620   /* If we've switched cpu's, try to find a handle we've used before */
00621   if (cd
00622       && (cgen_bitset_compare (isa, prev_isa) != 0
00623          || mach != prev_mach
00624          || endian != prev_endian))
00625     {
00626       cd = 0;
00627       for (cl = cd_list; cl; cl = cl->next)
00628        {
00629          if (cgen_bitset_compare (cl->isa, isa) == 0 &&
00630              cl->mach == mach &&
00631              cl->endian == endian)
00632            {
00633              cd = cl->cd;
00634              prev_isa = cd->isas;
00635              break;
00636            }
00637        }
00638     } 
00639 
00640   /* If we haven't initialized yet, initialize the opcode table.  */
00641   if (! cd)
00642     {
00643       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
00644       const char *mach_name;
00645 
00646       if (!arch_type)
00647        abort ();
00648       mach_name = arch_type->printable_name;
00649 
00650       prev_isa = cgen_bitset_copy (isa);
00651       prev_mach = mach;
00652       prev_endian = endian;
00653       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
00654                              CGEN_CPU_OPEN_BFDMACH, mach_name,
00655                              CGEN_CPU_OPEN_ENDIAN, prev_endian,
00656                              CGEN_CPU_OPEN_END);
00657       if (!cd)
00658        abort ();
00659 
00660       /* Save this away for future reference.  */
00661       cl = xmalloc (sizeof (struct cpu_desc_list));
00662       cl->cd = cd;
00663       cl->isa = prev_isa;
00664       cl->mach = mach;
00665       cl->endian = endian;
00666       cl->next = cd_list;
00667       cd_list = cl;
00668 
00669       m32r_cgen_init_dis (cd);
00670     }
00671 
00672   /* We try to have as much common code as possible.
00673      But at this point some targets need to take over.  */
00674   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
00675      but if not possible try to move this hook elsewhere rather than
00676      have two hooks.  */
00677   length = CGEN_PRINT_INSN (cd, pc, info);
00678   if (length > 0)
00679     return length;
00680   if (length < 0)
00681     return -1;
00682 
00683   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
00684   return cd->default_insn_bitsize / 8;
00685 }