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cell-binutils  2.17cvs20070401
m32r-desc.h
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00001 /* CPU data header for m32r.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef M32R_CPU_H
00026 #define M32R_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH m32r
00031 
00032 /* Given symbol S, return m32r_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) m32r##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) m32r_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_M32RBF
00042 #define HAVE_CPU_M32RXF
00043 #define HAVE_CPU_M32R2F
00044 
00045 #define CGEN_INSN_LSB0_P 0
00046 
00047 /* Minimum size of any insn (in bytes).  */
00048 #define CGEN_MIN_INSN_SIZE 2
00049 
00050 /* Maximum size of any insn (in bytes).  */
00051 #define CGEN_MAX_INSN_SIZE 4
00052 
00053 #define CGEN_INT_INSN_P 1
00054 
00055 /* Maximum number of syntax elements in an instruction.  */
00056 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
00057 
00058 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00059    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00060    we can't hash on everything up to the space.  */
00061 #define CGEN_MNEMONIC_OPERANDS
00062 
00063 /* Maximum number of fields in an instruction.  */
00064 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
00065 
00066 /* Enums.  */
00067 
00068 /* Enum declaration for insn format enums.  */
00069 typedef enum insn_op1 {
00070   OP1_0, OP1_1, OP1_2, OP1_3
00071  , OP1_4, OP1_5, OP1_6, OP1_7
00072  , OP1_8, OP1_9, OP1_10, OP1_11
00073  , OP1_12, OP1_13, OP1_14, OP1_15
00074 } INSN_OP1;
00075 
00076 /* Enum declaration for op2 enums.  */
00077 typedef enum insn_op2 {
00078   OP2_0, OP2_1, OP2_2, OP2_3
00079  , OP2_4, OP2_5, OP2_6, OP2_7
00080  , OP2_8, OP2_9, OP2_10, OP2_11
00081  , OP2_12, OP2_13, OP2_14, OP2_15
00082 } INSN_OP2;
00083 
00084 /* Enum declaration for .  */
00085 typedef enum gr_names {
00086   H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
00087  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
00088  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
00089  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
00090  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
00091 } GR_NAMES;
00092 
00093 /* Enum declaration for .  */
00094 typedef enum cr_names {
00095   H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
00096  , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
00097  , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
00098  , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
00099  , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
00100  , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
00101 } CR_NAMES;
00102 
00103 /* Attributes.  */
00104 
00105 /* Enum declaration for machine type selection.  */
00106 typedef enum mach_attr {
00107   MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2
00108  , MACH_MAX
00109 } MACH_ATTR;
00110 
00111 /* Enum declaration for instruction set selection.  */
00112 typedef enum isa_attr {
00113   ISA_M32R, ISA_MAX
00114 } ISA_ATTR;
00115 
00116 /* Enum declaration for parallel execution pipeline selection.  */
00117 typedef enum pipe_attr {
00118   PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
00119  , PIPE_O_OS
00120 } PIPE_ATTR;
00121 
00122 /* Number of architecture variants.  */
00123 #define MAX_ISAS  1
00124 #define MAX_MACHS ((int) MACH_MAX)
00125 
00126 /* Ifield support.  */
00127 
00128 /* Ifield attribute indices.  */
00129 
00130 /* Enum declaration for cgen_ifld attrs.  */
00131 typedef enum cgen_ifld_attr {
00132   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00133  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
00134  , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00135 } CGEN_IFLD_ATTR;
00136 
00137 /* Number of non-boolean elements in cgen_ifld_attr.  */
00138 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00139 
00140 /* cgen_ifld attribute accessor macros.  */
00141 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00142 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00143 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00144 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00145 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00146 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00147 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00148 #define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)
00149 
00150 /* Enum declaration for m32r ifield types.  */
00151 typedef enum ifield_type {
00152   M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
00153  , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
00154  , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4
00155  , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24
00156  , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24
00157  , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS
00158  , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14
00159  , M32R_F_IMM1, M32R_F_MAX
00160 } IFIELD_TYPE;
00161 
00162 #define MAX_IFLD ((int) M32R_F_MAX)
00163 
00164 /* Hardware attribute indices.  */
00165 
00166 /* Enum declaration for cgen_hw attrs.  */
00167 typedef enum cgen_hw_attr {
00168   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00169  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00170 } CGEN_HW_ATTR;
00171 
00172 /* Number of non-boolean elements in cgen_hw_attr.  */
00173 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00174 
00175 /* cgen_hw attribute accessor macros.  */
00176 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00177 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00178 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00179 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00180 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00181 
00182 /* Enum declaration for m32r hardware types.  */
00183 typedef enum cgen_hw_type {
00184   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00185  , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16
00186  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
00187  , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW
00188  , HW_H_BBPSW, HW_H_LOCK, HW_MAX
00189 } CGEN_HW_TYPE;
00190 
00191 #define MAX_HW ((int) HW_MAX)
00192 
00193 /* Operand attribute indices.  */
00194 
00195 /* Enum declaration for cgen_operand attrs.  */
00196 typedef enum cgen_operand_attr {
00197   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00198  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00199  , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31
00200  , CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00201 } CGEN_OPERAND_ATTR;
00202 
00203 /* Number of non-boolean elements in cgen_operand_attr.  */
00204 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00205 
00206 /* cgen_operand attribute accessor macros.  */
00207 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00208 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00209 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00210 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00211 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00212 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00213 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00214 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00215 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00216 #define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)
00217 #define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
00218 
00219 /* Enum declaration for m32r operand types.  */
00220 typedef enum cgen_operand_type {
00221   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
00222  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
00223  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5
00224  , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD
00225  , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16
00226  , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8
00227  , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM
00228  , M32R_OPERAND_MAX
00229 } CGEN_OPERAND_TYPE;
00230 
00231 /* Number of operands types.  */
00232 #define MAX_OPERANDS 28
00233 
00234 /* Maximum number of operands referenced by any insn.  */
00235 #define MAX_OPERAND_INSTANCES 11
00236 
00237 /* Insn attribute indices.  */
00238 
00239 /* Enum declaration for cgen_insn attrs.  */
00240 typedef enum cgen_insn_attr {
00241   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00242  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00243  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
00244  , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
00245  , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
00246 } CGEN_INSN_ATTR;
00247 
00248 /* Number of non-boolean elements in cgen_insn_attr.  */
00249 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00250 
00251 /* cgen_insn attribute accessor macros.  */
00252 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00253 #define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
00254 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00255 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00256 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00257 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00258 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00259 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00260 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00261 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00262 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00263 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00264 #define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0)
00265 #define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0)
00266 #define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0)
00267 #define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0)
00268 
00269 /* cgen.h uses things we just defined.  */
00270 #include "opcode/cgen.h"
00271 
00272 extern const struct cgen_ifld m32r_cgen_ifld_table[];
00273 
00274 /* Attributes.  */
00275 extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[];
00276 extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[];
00277 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
00278 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
00279 
00280 /* Hardware decls.  */
00281 
00282 extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
00283 extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
00284 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
00285 
00286 extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];
00287 
00288 
00289 
00290 #endif /* M32R_CPU_H */