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cell-binutils  2.17cvs20070401
Defines | Typedefs | Enumerations | Variables
m32r-desc.h File Reference
#include "opcode/cgen-bitset.h"
#include "opcode/cgen.h"
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Defines

#define CGEN_ARCH   m32r
#define CGEN_SYM(s)   m32r_cgen_s
#define HAVE_CPU_M32RBF
#define HAVE_CPU_M32RXF
#define HAVE_CPU_M32R2F
#define CGEN_INSN_LSB0_P   0
#define CGEN_MIN_INSN_SIZE   2
#define CGEN_MAX_INSN_SIZE   4
#define CGEN_INT_INSN_P   1
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS   15
#define CGEN_MNEMONIC_OPERANDS
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS   7
#define MAX_ISAS   1
#define MAX_MACHS   ((int) MACH_MAX)
#define CGEN_IFLD_NBOOL_ATTRS   (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)
#define MAX_IFLD   ((int) M32R_F_MAX)
#define CGEN_HW_NBOOL_ATTRS   (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
#define MAX_HW   ((int) HW_MAX)
#define CGEN_OPERAND_NBOOL_ATTRS   (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
#define MAX_OPERANDS   28
#define MAX_OPERAND_INSTANCES   11
#define CGEN_INSN_NBOOL_ATTRS   (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0)
#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0)

Typedefs

typedef enum insn_op1 INSN_OP1
typedef enum insn_op2 INSN_OP2
typedef enum gr_names GR_NAMES
typedef enum cr_names CR_NAMES
typedef enum mach_attr MACH_ATTR
typedef enum isa_attr ISA_ATTR
typedef enum pipe_attr PIPE_ATTR
typedef enum cgen_ifld_attr CGEN_IFLD_ATTR
typedef enum ifield_type IFIELD_TYPE
typedef enum cgen_hw_attr CGEN_HW_ATTR
typedef enum cgen_hw_type CGEN_HW_TYPE
typedef enum cgen_operand_attr CGEN_OPERAND_ATTR
typedef enum cgen_operand_type CGEN_OPERAND_TYPE
typedef enum cgen_insn_attr CGEN_INSN_ATTR

Enumerations

enum  insn_op1 {
  OP1_0, OP1_1, OP1_2, OP1_3,
  OP1_4, OP1_5, OP1_6, OP1_7,
  OP1_8, OP1_9, OP1_A, OP1_B,
  OP1_C, OP1_D, OP1_E, OP1_F,
  OP1_0, OP1_1, OP1_2, OP1_3,
  OP1_4, OP1_5, OP1_6, OP1_7,
  OP1_8, OP1_9, OP1_10, OP1_11,
  OP1_12, OP1_13, OP1_14, OP1_15,
  OP1_0, OP1_1, OP1_2, OP1_3,
  OP1_4, OP1_5, OP1_6, OP1_7,
  OP1_8, OP1_9, OP1_10, OP1_11,
  OP1_12, OP1_13, OP1_14, OP1_15,
  OP1_0, OP1_1, OP1_2, OP1_3,
  OP1_4, OP1_5, OP1_6, OP1_7,
  OP1_8, OP1_9, OP1_A, OP1_B,
  OP1_C, OP1_D, OP1_E, OP1_F
}
enum  insn_op2 {
  OP2_0, OP2_1, OP2_2, OP2_3,
  OP2_4, OP2_5, OP2_6, OP2_7,
  OP2_8, OP2_9, OP2_A, OP2_B,
  OP2_C, OP2_D, OP2_E, OP2_F,
  OP2_0, OP2_1, OP2_2, OP2_3,
  OP2_4, OP2_5, OP2_6, OP2_7,
  OP2_8, OP2_9, OP2_10, OP2_11,
  OP2_12, OP2_13, OP2_14, OP2_15,
  OP2_0, OP2_1, OP2_2, OP2_3,
  OP2_4, OP2_5, OP2_6, OP2_7,
  OP2_8, OP2_9, OP2_10, OP2_11,
  OP2_12, OP2_13, OP2_14, OP2_15,
  OP2_0, OP2_1, OP2_2, OP2_3,
  OP2_4, OP2_5, OP2_6, OP2_7,
  OP2_8, OP2_9, OP2_A, OP2_B,
  OP2_C, OP2_D, OP2_E, OP2_F
}
enum  gr_names {
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3,
  H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7,
  H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11,
  H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15,
  H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_SP = 1,
  H_GR_FP = 2, H_GR_GR0 = 0, H_GR_GR1 = 1, H_GR_GR2 = 2,
  H_GR_GR3 = 3, H_GR_GR4 = 4, H_GR_GR5 = 5, H_GR_GR6 = 6,
  H_GR_GR7 = 7, H_GR_GR8 = 8, H_GR_GR9 = 9, H_GR_GR10 = 10,
  H_GR_GR11 = 11, H_GR_GR12 = 12, H_GR_GR13 = 13, H_GR_GR14 = 14,
  H_GR_GR15 = 15, H_GR_GR16 = 16, H_GR_GR17 = 17, H_GR_GR18 = 18,
  H_GR_GR19 = 19, H_GR_GR20 = 20, H_GR_GR21 = 21, H_GR_GR22 = 22,
  H_GR_GR23 = 23, H_GR_GR24 = 24, H_GR_GR25 = 25, H_GR_GR26 = 26,
  H_GR_GR27 = 27, H_GR_GR28 = 28, H_GR_GR29 = 29, H_GR_GR30 = 30,
  H_GR_GR31 = 31, H_GR_GR32 = 32, H_GR_GR33 = 33, H_GR_GR34 = 34,
  H_GR_GR35 = 35, H_GR_GR36 = 36, H_GR_GR37 = 37, H_GR_GR38 = 38,
  H_GR_GR39 = 39, H_GR_GR40 = 40, H_GR_GR41 = 41, H_GR_GR42 = 42,
  H_GR_GR43 = 43, H_GR_GR44 = 44, H_GR_GR45 = 45, H_GR_GR46 = 46,
  H_GR_GR47 = 47, H_GR_GR48 = 48, H_GR_GR49 = 49, H_GR_GR50 = 50,
  H_GR_GR51 = 51, H_GR_GR52 = 52, H_GR_GR53 = 53, H_GR_GR54 = 54,
  H_GR_GR55 = 55, H_GR_GR56 = 56, H_GR_GR57 = 57, H_GR_GR58 = 58,
  H_GR_GR59 = 59, H_GR_GR60 = 60, H_GR_GR61 = 61, H_GR_GR62 = 62,
  H_GR_GR63 = 63, H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1,
  H_GR__1 = 1, H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3,
  H_GR__3 = 3, H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5,
  H_GR__5 = 5, H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7,
  H_GR__7 = 7, H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9,
  H_GR__9 = 9, H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11,
  H_GR__11 = 11, H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13,
  H_GR__13 = 13, H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15,
  H_GR__15 = 15, H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17,
  H_GR__17 = 17, H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19,
  H_GR__19 = 19, H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21,
  H_GR__21 = 21, H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23,
  H_GR__23 = 23, H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25,
  H_GR__25 = 25, H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27,
  H_GR__27 = 27, H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29,
  H_GR__29 = 29, H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31,
  H_GR__31 = 31, H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15,
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3,
  H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7,
  H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11,
  H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15,
  H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3,
  H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7,
  H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11,
  H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15,
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3,
  H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7,
  H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11,
  H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15,
  H_GR_PSW = 14, H_GR_SP = 15
}
enum  cr_names {
  H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3,
  H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7,
  H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11,
  H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15,
  H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3,
  H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5,
  H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3,
  H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7,
  H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11,
  H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
}
enum  mach_attr {
  MACH_BASE, MACH_FR30, MACH_MAX, MACH_BASE,
  MACH_FRV, MACH_FR550, MACH_FR500, MACH_FR450,
  MACH_FR400, MACH_TOMCAT, MACH_SIMPLE, MACH_MAX,
  MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX,
  MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX,
  MACH_BASE, MACH_M16C, MACH_M32C, MACH_MAX,
  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2,
  MACH_MAX, MACH_BASE, MACH_MEP, MACH_H1,
  MACH_MAX, MACH_BASE, MACH_MS1, MACH_MS1_003,
  MACH_MS2, MACH_MAX, MACH_BASE, MACH_OPENRISC,
  MACH_OR1300, MACH_MAX, MACH_BASE, MACH_XC16X,
  MACH_MAX, MACH_BASE, MACH_XSTORMY16, MACH_MAX
}
enum  isa_attr {
  ISA_FR30, ISA_MAX, ISA_FRV, ISA_MAX,
  ISA_IP2K, ISA_MAX, ISA_IQ2000, ISA_MAX,
  ISA_M16C, ISA_M32C, ISA_MAX, ISA_M32R,
  ISA_MAX, ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2,
  ISA_EXT_COP2_16, ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64,
  ISA_MAX, ISA_MT, ISA_MAX, ISA_OR32,
  ISA_MAX, ISA_XC16X, ISA_MAX, ISA_XSTORMY16,
  ISA_MAX
}
enum  pipe_attr {
  PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS,
  PIPE_O_OS, PIPE_NONE, PIPE_OS
}
enum  cgen_ifld_attr {
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_RL_TYPE, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS,
  CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL,
  CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT,
  CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH,
  CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH,
  CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR,
  CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS,
  CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
}
enum  ifield_type {
  FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2,
  FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC,
  FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1,
  FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ,
  FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4,
  FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4,
  FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6,
  FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10,
  FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9,
  FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST,
  FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX, FRV_F_NIL,
  FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP, FRV_F_OPE1,
  FRV_F_OPE2, FRV_F_OPE3, FRV_F_OPE4, FRV_F_GRI,
  FRV_F_GRJ, FRV_F_GRK, FRV_F_FRI, FRV_F_FRJ,
  FRV_F_FRK, FRV_F_CPRI, FRV_F_CPRJ, FRV_F_CPRK,
  FRV_F_ACCGI, FRV_F_ACCGK, FRV_F_ACC40SI, FRV_F_ACC40UI,
  FRV_F_ACC40SK, FRV_F_ACC40UK, FRV_F_CRI, FRV_F_CRJ,
  FRV_F_CRK, FRV_F_CCI, FRV_F_CRJ_INT, FRV_F_CRJ_FLOAT,
  FRV_F_ICCI_1, FRV_F_ICCI_2, FRV_F_ICCI_3, FRV_F_FCCI_1,
  FRV_F_FCCI_2, FRV_F_FCCI_3, FRV_F_FCCK, FRV_F_EIR,
  FRV_F_S10, FRV_F_S12, FRV_F_D12, FRV_F_U16,
  FRV_F_S16, FRV_F_S6, FRV_F_S6_1, FRV_F_U6,
  FRV_F_S5, FRV_F_U12_H, FRV_F_U12_L, FRV_F_U12,
  FRV_F_INT_CC, FRV_F_FLT_CC, FRV_F_COND, FRV_F_CCOND,
  FRV_F_HINT, FRV_F_LI, FRV_F_LOCK, FRV_F_DEBUG,
  FRV_F_A, FRV_F_AE, FRV_F_SPR_H, FRV_F_SPR_L,
  FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6, FRV_F_LABELL18,
  FRV_F_LABEL24, FRV_F_LRAE, FRV_F_LRAD, FRV_F_LRAS,
  FRV_F_TLBPROPX, FRV_F_TLBPRL, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL,
  FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL,
  FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL,
  FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL,
  FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL,
  FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4,
  FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8,
  FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LRA_NULL,
  FRV_F_TLBPR_NULL, FRV_F_LI_OFF, FRV_F_LI_ON, FRV_F_RELOC_ANN,
  FRV_F_MAX, IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8,
  IP2K_F_REG, IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO,
  IP2K_F_OP3, IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6,
  IP2K_F_OP8, IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3,
  IP2K_F_SKIPB, IP2K_F_PAGE3, IP2K_F_MAX, IQ2000_F_NIL,
  IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS, IQ2000_F_RT,
  IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP, IQ2000_F_CP_OP_10,
  IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM, IQ2000_F_RD_RS,
  IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG, IQ2000_F_JTARGQ10,
  IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT, IQ2000_F_INDEX,
  IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL, IQ2000_F_EXCODE,
  IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19, IQ2000_F_5,
  IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z, IQ2000_F_CAM_Y,
  IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z, IQ2000_F_CM_4Z,
  IQ2000_F_MAX, M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1,
  M32C_F_0_2, M32C_F_0_3, M32C_F_0_4, M32C_F_1_3,
  M32C_F_2_2, M32C_F_3_4, M32C_F_3_1, M32C_F_4_1,
  M32C_F_4_3, M32C_F_4_4, M32C_F_4_6, M32C_F_5_1,
  M32C_F_5_3, M32C_F_6_2, M32C_F_7_1, M32C_F_8_1,
  M32C_F_8_2, M32C_F_8_3, M32C_F_8_4, M32C_F_8_8,
  M32C_F_9_3, M32C_F_9_1, M32C_F_10_1, M32C_F_10_2,
  M32C_F_10_3, M32C_F_11_1, M32C_F_12_1, M32C_F_12_2,
  M32C_F_12_3, M32C_F_12_4, M32C_F_12_6, M32C_F_13_3,
  M32C_F_14_1, M32C_F_14_2, M32C_F_15_1, M32C_F_16_1,
  M32C_F_16_2, M32C_F_16_4, M32C_F_16_8, M32C_F_18_1,
  M32C_F_18_2, M32C_F_18_3, M32C_F_20_1, M32C_F_20_3,
  M32C_F_20_2, M32C_F_20_4, M32C_F_21_3, M32C_F_24_2,
  M32C_F_24_8, M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN,
  M32C_F_SRC32_AN_UNPREFIXED, M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI,
  M32C_F_SRC32_RN_UNPREFIXED_HI, M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI,
  M32C_F_DST32_RN_EXT_UNPREFIXED, M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S,
  M32C_F_DST16_AN, M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED,
  M32C_F_DST32_RN_UNPREFIXED_QI, M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI,
  M32C_F_DST32_RN_UNPREFIXED_SI, M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4,
  M32C_F_IMM_12_S4, M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S,
  M32C_F_IMM3_S, M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8,
  M32C_F_DSP_10_U6, M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8,
  M32C_F_DSP_24_S8, M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8,
  M32C_F_DSP_40_S8, M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8,
  M32C_F_DSP_56_S8, M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16,
  M32C_F_DSP_8_S16, M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16,
  M32C_F_DSP_24_S16, M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16,
  M32C_F_DSP_40_S16, M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16,
  M32C_F_DSP_8_S24, M32C_F_DSP_8_U24, M32C_F_DSP_16_U24, M32C_F_DSP_24_U24,
  M32C_F_DSP_32_U24, M32C_F_DSP_40_U20, M32C_F_DSP_40_U24, M32C_F_DSP_40_S32,
  M32C_F_DSP_48_U20, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32,
  M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16,
  M32C_F_DSP_64_S16, M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED, M32C_F_BITNO32_UNPREFIXED,
  M32C_F_BITBASE16_U11_S, M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED, M32C_F_BITBASE32_16_U19_UNPREFIXED,
  M32C_F_BITBASE32_16_S19_UNPREFIXED, M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED, M32C_F_BITBASE32_24_S11_PREFIXED,
  M32C_F_BITBASE32_24_U19_PREFIXED, M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED, M32C_F_LAB_5_3,
  M32C_F_LAB32_JMP_S, M32C_F_LAB_8_8, M32C_F_LAB_8_16, M32C_F_LAB_8_24,
  M32C_F_LAB_16_8, M32C_F_LAB_24_8, M32C_F_LAB_32_8, M32C_F_LAB_40_8,
  M32C_F_COND16, M32C_F_COND16J_5, M32C_F_COND32, M32C_F_COND32J,
  M32C_F_MAX, M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1,
  M32R_F_OP2, M32R_F_COND, M32R_F_R1, M32R_F_R2,
  M32R_F_SIMM8, M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3,
  M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16,
  M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16,
  M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3, M32R_F_ACC,
  M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4,
  M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX, MEP_F_NIL,
  MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN, MEP_F_RN3,
  MEP_F_RM, MEP_F_RL, MEP_F_SUB2, MEP_F_SUB3,
  MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN, MEP_F_CSRN_HI,
  MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO,
  MEP_F_CRNX, MEP_F_0, MEP_F_1, MEP_F_2,
  MEP_F_3, MEP_F_4, MEP_F_5, MEP_F_6,
  MEP_F_7, MEP_F_8, MEP_F_9, MEP_F_10,
  MEP_F_11, MEP_F_12, MEP_F_13, MEP_F_14,
  MEP_F_15, MEP_F_16, MEP_F_17, MEP_F_18,
  MEP_F_19, MEP_F_20, MEP_F_21, MEP_F_22,
  MEP_F_23, MEP_F_24, MEP_F_25, MEP_F_26,
  MEP_F_27, MEP_F_28, MEP_F_29, MEP_F_30,
  MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2,
  MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI,
  MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9,
  MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10,
  MEP_F_3U5, MEP_F_4U8, MEP_F_5U8, MEP_F_5U24,
  MEP_F_6S8, MEP_F_8S8, MEP_F_16U16, MEP_F_12U16,
  MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2, MEP_F_8S24A4,
  MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N,
  MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI,
  MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI,
  MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4, MEP_F_FMAX_4_4,
  MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4, MEP_F_FMAX_20_4,
  MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1, MEP_F_FMAX_30_1,
  MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN, MEP_F_FMAX_FRM,
  MEP_F_FMAX_RM, MEP_F_MAX, MT_F_NIL, MT_F_ANYOF,
  MT_F_MSYS, MT_F_OPC, MT_F_IMM, MT_F_UU24,
  MT_F_SR1, MT_F_SR2, MT_F_DR, MT_F_DRRR,
  MT_F_IMM16U, MT_F_IMM16S, MT_F_IMM16A, MT_F_UU4A,
  MT_F_UU4B, MT_F_UU12, MT_F_UU8, MT_F_UU16,
  MT_F_UU1, MT_F_MSOPC, MT_F_UU_26_25, MT_F_MASK,
  MT_F_BANKADDR, MT_F_RDA, MT_F_UU_2_25, MT_F_RBBC,
  MT_F_PERM, MT_F_MODE, MT_F_UU_1_24, MT_F_WR,
  MT_F_FBINCR, MT_F_UU_2_23, MT_F_XMODE, MT_F_A23,
  MT_F_MASK1, MT_F_CR, MT_F_TYPE, MT_F_INCAMT,
  MT_F_CBS, MT_F_UU_1_19, MT_F_BALL, MT_F_COLNUM,
  MT_F_BRC, MT_F_INCR, MT_F_FBDISP, MT_F_UU_4_15,
  MT_F_LENGTH, MT_F_UU_1_15, MT_F_RC, MT_F_RCNUM,
  MT_F_ROWNUM, MT_F_CBX, MT_F_ID, MT_F_SIZE,
  MT_F_ROWNUM1, MT_F_UU_3_11, MT_F_RC1, MT_F_CCB,
  MT_F_CBRB, MT_F_CDB, MT_F_ROWNUM2, MT_F_CELL,
  MT_F_UU_3_9, MT_F_CONTNUM, MT_F_UU_1_6, MT_F_DUP,
  MT_F_RC2, MT_F_CTXDISP, MT_F_IMM16L, MT_F_LOOPO,
  MT_F_CB1SEL, MT_F_CB2SEL, MT_F_CB1INCR, MT_F_CB2INCR,
  MT_F_RC3, MT_F_MSYSFRSR2, MT_F_BRC2, MT_F_BALL2,
  MT_F_MAX, OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS,
  OPENRISC_F_SUB, OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3,
  OPENRISC_F_SIMM16, OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16,
  OPENRISC_F_LO16, OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3,
  OPENRISC_F_OP4, OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7,
  OPENRISC_F_I16_1, OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26,
  OPENRISC_F_I16NC, OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1,
  OPENRISC_F_F_7_3, OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX,
  XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2,
  XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND,
  XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2,
  XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3,
  XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16,
  XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8,
  XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8,
  XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8,
  XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16,
  XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3,
  XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT,
  XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16,
  XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2,
  XC16X_F_POF, XC16X_F_MAX, XSTORMY16_F_NIL, XSTORMY16_F_ANYOF,
  XSTORMY16_F_RD, XSTORMY16_F_RDM, XSTORMY16_F_RM, XSTORMY16_F_RS,
  XSTORMY16_F_RB, XSTORMY16_F_RBJ, XSTORMY16_F_OP1, XSTORMY16_F_OP2,
  XSTORMY16_F_OP2A, XSTORMY16_F_OP2M, XSTORMY16_F_OP3, XSTORMY16_F_OP3A,
  XSTORMY16_F_OP3B, XSTORMY16_F_OP4, XSTORMY16_F_OP4M, XSTORMY16_F_OP4B,
  XSTORMY16_F_OP5, XSTORMY16_F_OP5A, XSTORMY16_F_OP, XSTORMY16_F_IMM2,
  XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B, XSTORMY16_F_IMM4, XSTORMY16_F_IMM8,
  XSTORMY16_F_IMM12, XSTORMY16_F_IMM16, XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8,
  XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4, XSTORMY16_F_REL12, XSTORMY16_F_REL12A,
  XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2, XSTORMY16_F_ABS24, XSTORMY16_F_MAX
}
enum  cgen_hw_attr {
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA,
  CGEN_HW_RL_TYPE, CGEN_HW_END_NBOOLS, CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR,
  CGEN_HW_PC, CGEN_HW_PROFILE, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31,
  CGEN_HW_MACH, CGEN_HW_END_NBOOLS, CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR,
  CGEN_HW_PC, CGEN_HW_PROFILE, CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS,
  CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
}
enum  cgen_hw_type {
  CGEN_HW_MAX, HW_H_MEMORY, HW_H_SINT, HW_H_UINT,
  HW_H_ADDR, HW_H_IADDR, HW_H_PC, HW_H_GR,
  HW_H_CR, HW_H_DR, HW_H_PS, HW_H_R13,
  HW_H_R14, HW_H_R15, HW_H_NBIT, HW_H_ZBIT,
  HW_H_VBIT, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT,
  HW_H_TBIT, HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR,
  HW_H_SCR, HW_H_ILM, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_RELOC_ANN, HW_H_PC, HW_H_PSR_IMPLE, HW_H_PSR_VER,
  HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM, HW_H_PSR_BE,
  HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM, HW_H_PSR_PIL,
  HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S, HW_H_TBR_TBA,
  HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET, HW_H_GR,
  HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO, HW_H_FR,
  HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO,
  HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3,
  HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG,
  HW_H_ACC40S, HW_H_ACC40U, HW_H_IACC0, HW_H_ICCR,
  HW_H_FCCR, HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN,
  HW_H_HINT_NOT_TAKEN, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_SPR,
  HW_H_REGISTERS, HW_H_STACK, HW_H_PABITS, HW_H_ZBIT,
  HW_H_CBIT, HW_H_DCBIT, HW_H_PC, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI,
  HW_H_GR_HI, HW_H_GR_SI, HW_H_GR_EXT_QI, HW_H_GR_EXT_HI,
  HW_H_R0L, HW_H_R0H, HW_H_R1L, HW_H_R1H,
  HW_H_R0, HW_H_R1, HW_H_R2, HW_H_R3,
  HW_H_R0L_R0H, HW_H_R2R0, HW_H_R3R1, HW_H_R1R2R0,
  HW_H_AR, HW_H_AR_QI, HW_H_AR_HI, HW_H_AR_SI,
  HW_H_A0, HW_H_A1, HW_H_SB, HW_H_FB,
  HW_H_SP, HW_H_SBIT, HW_H_ZBIT, HW_H_OBIT,
  HW_H_CBIT, HW_H_UBIT, HW_H_IBIT, HW_H_BBIT,
  HW_H_DBIT, HW_H_DCT0, HW_H_DCT1, HW_H_SVF,
  HW_H_DRC0, HW_H_DRC1, HW_H_DMD0, HW_H_DMD1,
  HW_H_INTB, HW_H_SVP, HW_H_VCT, HW_H_ISP,
  HW_H_DMA0, HW_H_DMA1, HW_H_DRA0, HW_H_DRA1,
  HW_H_DSA0, HW_H_DSA1, HW_H_COND16, HW_H_COND16C,
  HW_H_COND16J, HW_H_COND16J_5, HW_H_COND32, HW_H_CR1_32,
  HW_H_CR2_32, HW_H_CR3_32, HW_H_CR_16, HW_H_FLAGS,
  HW_H_SHIMM, HW_H_BIT_INDEX, HW_H_SRC_INDEX, HW_H_DST_INDEX,
  HW_H_SRC_INDIRECT, HW_H_DST_INDIRECT, HW_H_NONE, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16,
  HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM,
  HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW,
  HW_H_BBPSW, HW_H_LOCK, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GPR, HW_H_CSR, HW_H_CR64,
  HW_H_CR, HW_H_CCR, HW_H_CR_FMAX, HW_H_CCR_FMAX,
  HW_H_FMAX_COMPARE_I_P, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_SPR,
  HW_H_PC, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_PC,
  HW_H_GR, HW_H_SR, HW_H_HI16, HW_H_LO16,
  HW_H_CBIT, HW_H_DELAY_INSN, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GR, HW_H_EXT, HW_H_PSW,
  HW_H_GRB, HW_H_CC, HW_H_ECC, HW_H_GRB8,
  HW_H_R8, HW_H_REGMEM8, HW_H_REGDIV8, HW_H_R0,
  HW_H_R01, HW_H_REGBMEM8, HW_H_MEMGR8, HW_H_COND,
  HW_H_CBIT, HW_H_SGTDIS, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GR, HW_H_RB, HW_H_RBJ,
  HW_H_RPSW, HW_H_Z8, HW_H_Z16, HW_H_CY,
  HW_H_HC, HW_H_OV, HW_H_PT, HW_H_S,
  HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX
}
enum  cgen_operand_attr {
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT,
  CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY,
  CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH,
  CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR,
  CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX,
  CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_ISA, CGEN_OPERAND_RL_TYPE, CGEN_OPERAND_END_NBOOLS,
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT,
  CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY,
  CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS,
  CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA,
  CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX,
  CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX, CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX,
  CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH,
  CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR,
  CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX,
  CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH,
  CGEN_OPERAND_END_NBOOLS
}
enum  cgen_operand_type {
  CGEN_OPERAND_MAX, FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ,
  FR30_OPERAND_RIC, FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ,
  FR30_OPERAND_RS1, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14,
  FR30_OPERAND_R15, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C,
  FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8,
  FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10,
  FR30_OPERAND_I32, FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8,
  FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12,
  FR30_OPERAND_REGLIST_LOW_LD, FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST,
  FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT,
  FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT,
  FR30_OPERAND_TBIT, FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR,
  FR30_OPERAND_SCR, FR30_OPERAND_ILM, FR30_OPERAND_MAX, FRV_OPERAND_PC,
  FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ, FRV_OPERAND_GRK,
  FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK, FRV_OPERAND_ACC40SI,
  FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK, FRV_OPERAND_ACCGI,
  FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ, FRV_OPERAND_CPRK,
  FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ, FRV_OPERAND_FRINTK,
  FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK, FRV_OPERAND_FRKHI,
  FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ, FRV_OPERAND_FRDOUBLEK,
  FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT, FRV_OPERAND_CRJ_FLOAT,
  FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1, FRV_OPERAND_ICCI_2,
  FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2, FRV_OPERAND_FCCI_3,
  FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10, FRV_OPERAND_U16,
  FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1, FRV_OPERAND_U6,
  FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND, FRV_OPERAND_HINT,
  FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI, FRV_OPERAND_LOCK,
  FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16, FRV_OPERAND_LRAE,
  FRV_OPERAND_LRAD, FRV_OPERAND_LRAS, FRV_OPERAND_TLBPROPX, FRV_OPERAND_TLBPRL,
  FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN,
  FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12,
  FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16,
  FRV_OPERAND_LABEL24, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS,
  FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA,
  FRV_OPERAND_TBR_TT, FRV_OPERAND_LDANN, FRV_OPERAND_LDDANN, FRV_OPERAND_CALLANN,
  FRV_OPERAND_MAX, IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR,
  IP2K_OPERAND_LIT8, IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H,
  IP2K_OPERAND_ADDR16L, IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT,
  IP2K_OPERAND_CBIT, IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX, IQ2000_OPERAND_PC,
  IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD, IQ2000_OPERAND_RD_RS,
  IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT, IQ2000_OPERAND_IMM,
  IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG, IQ2000_OPERAND_MASK,
  IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT, IQ2000_OPERAND__INDEX,
  IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y, IQ2000_OPERAND_CAM_Z,
  IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z, IQ2000_OPERAND_CM_4Z,
  IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM, IQ2000_OPERAND_HI16,
  IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10, IQ2000_OPERAND_MAX,
  M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI,
  M32C_OPERAND_SRC32RNUNPREFIXEDHI, M32C_OPERAND_SRC32RNUNPREFIXEDSI, M32C_OPERAND_SRC32RNPREFIXEDQI, M32C_OPERAND_SRC32RNPREFIXEDHI,
  M32C_OPERAND_SRC32RNPREFIXEDSI, M32C_OPERAND_SRC16AN, M32C_OPERAND_SRC16ANQI, M32C_OPERAND_SRC16ANHI,
  M32C_OPERAND_SRC32ANUNPREFIXED, M32C_OPERAND_SRC32ANUNPREFIXEDQI, M32C_OPERAND_SRC32ANUNPREFIXEDHI, M32C_OPERAND_SRC32ANUNPREFIXEDSI,
  M32C_OPERAND_SRC32ANPREFIXED, M32C_OPERAND_SRC32ANPREFIXEDQI, M32C_OPERAND_SRC32ANPREFIXEDHI, M32C_OPERAND_SRC32ANPREFIXEDSI,
  M32C_OPERAND_DST16RNQI, M32C_OPERAND_DST16RNHI, M32C_OPERAND_DST16RNSI, M32C_OPERAND_DST16RNEXTQI,
  M32C_OPERAND_DST32R0QI_S, M32C_OPERAND_DST32R0HI_S, M32C_OPERAND_DST32RNUNPREFIXEDQI, M32C_OPERAND_DST32RNUNPREFIXEDHI,
  M32C_OPERAND_DST32RNUNPREFIXEDSI, M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDQI,
  M32C_OPERAND_DST32RNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDSI, M32C_OPERAND_DST16RNQI_S, M32C_OPERAND_DST16ANQI_S,
  M32C_OPERAND_BIT16RN, M32C_OPERAND_BIT32RNPREFIXED, M32C_OPERAND_BIT32RNUNPREFIXED, M32C_OPERAND_R0,
  M32C_OPERAND_R1, M32C_OPERAND_R2, M32C_OPERAND_R3, M32C_OPERAND_R0L,
  M32C_OPERAND_R0H, M32C_OPERAND_R2R0, M32C_OPERAND_R3R1, M32C_OPERAND_R1R2R0,
  M32C_OPERAND_DST16AN, M32C_OPERAND_DST16ANQI, M32C_OPERAND_DST16ANHI, M32C_OPERAND_DST16ANSI,
  M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI,
  M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI,
  M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED,
  M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB,
  M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP,
  M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6,
  M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_S24,
  M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16,
  M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16,
  M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24,
  M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16,
  M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16,
  M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16,
  M32C_OPERAND_DSP_40_U20, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8,
  M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U20, M32C_OPERAND_DSP_48_U24,
  M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI,
  M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4,
  M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI,
  M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI,
  M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI,
  M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI,
  M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI,
  M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BIT3_S,
  M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8,
  M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED,
  M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED,
  M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED,
  M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8,
  M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8,
  M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT,
  M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT,
  M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24,
  M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32,
  M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5,
  M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16,
  M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32,
  M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z,
  M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G, M32C_OPERAND_X,
  M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX,
  M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI,
  M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI,
  M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI,
  M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_20_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI,
  M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI,
  M32C_OPERAND_SRC16_16_20_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI,
  M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI,
  M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI,
  M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI,
  M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI,
  M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI,
  M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI,
  M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI,
  M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI,
  M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI,
  M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI,
  M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI,
  M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI,
  M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI,
  M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI,
  M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI,
  M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI,
  M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED,
  M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT,
  M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE,
  M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED,
  M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED,
  M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED,
  M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED,
  M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED,
  M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED,
  M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI,
  M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI,
  M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI,
  M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI,
  M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI,
  M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI,
  M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI,
  M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI,
  M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI,
  M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI,
  M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_16SA_QI, M32C_OPERAND_DST16_16_20AR_QI,
  M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_16SA_HI,
  M32C_OPERAND_DST16_16_20AR_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI,
  M32C_OPERAND_DST16_16_16SA_SI, M32C_OPERAND_DST16_16_20AR_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI,
  M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI,
  M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI,
  M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI,
  M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI,
  M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI,
  M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI,
  M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI,
  M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC,
  M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED,
  M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED,
  M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8,
  M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI,
  M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI,
  M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S,
  M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX, M32R_OPERAND_PC,
  M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1, M32R_OPERAND_SRC2,
  M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8, M32R_OPERAND_SIMM16,
  M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM8,
  M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS,
  M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16,
  M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16,
  M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX,
  MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM,
  MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC,
  MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL,
  MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S,
  MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP,
  MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0,
  MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW,
  MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG,
  MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP,
  MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN,
  MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64,
  MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2,
  MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2,
  MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16,
  MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8,
  MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3,
  MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2,
  MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4,
  MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4,
  MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD,
  MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT,
  MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR,
  MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX, MT_OPERAND_PC,
  MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR, MT_OPERAND_FRDRRR,
  MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O, MT_OPERAND_RC,
  MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC, MT_OPERAND_COLNUM,
  MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2, MT_OPERAND_RC1,
  MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL, MT_OPERAND_DUP,
  MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE, MT_OPERAND_MASK,
  MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE, MT_OPERAND_MASK1,
  MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA, MT_OPERAND_WR,
  MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM, MT_OPERAND_A23,
  MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR, MT_OPERAND_LENGTH,
  MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB, MT_OPERAND_MODE,
  MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR, MT_OPERAND_LOOPSIZE,
  MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL, MT_OPERAND_CB2SEL,
  MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX, OPENRISC_OPERAND_PC,
  OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16, OPENRISC_OPERAND_UIMM_16,
  OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5, OPENRISC_OPERAND_RD,
  OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23, OPENRISC_OPERAND_OP_F_3,
  OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC, OPENRISC_OPERAND_MAX,
  XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI,
  XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1,
  XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2,
  XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8,
  XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8,
  XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8,
  XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR,
  XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1,
  XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2,
  XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01,
  XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY,
  XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT,
  XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM,
  XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16,
  XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH,
  XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF,
  XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX, XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8,
  XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY, XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV,
  XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S, XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM,
  XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS, XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ,
  XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2, XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2,
  XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B, XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8,
  XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12, XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8,
  XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2, XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12,
  XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24, XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW,
  XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0, XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2,
  XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX
}
enum  cgen_insn_attr {
  CGEN_INSN_ALIAS = 0, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT,
  CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS,
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI,
  CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED,
  CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING,
  CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO,
  CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT,
  CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN,
  CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN,
  CGEN_INSN_LOAD_DELAY, CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD,
  CGEN_INSN_USES_RS, CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS,
  CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS,
  CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI,
  CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS,
  CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_ISA, CGEN_INSN_RL_TYPE, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS,
  CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI,
  CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS,
  CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL, CGEN_INSN_SPECIAL_M32R,
  CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL,
  CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT,
  CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB,
  CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN, CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN,
  CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN,
  CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN,
  CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP,
  CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP,
  CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY,
  CGEN_INSN_MEMORY_ACCESS, CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN,
  CGEN_INSN_JAL_HAZARD, CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1,
  CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL,
  CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT,
  CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB,
  CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS,
  CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS,
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI,
  CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED,
  CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
}

Variables

const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table []
const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table []
const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table []
const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table []
CGEN_KEYWORD m32r_cgen_opval_gr_names
CGEN_KEYWORD m32r_cgen_opval_cr_names
CGEN_KEYWORD m32r_cgen_opval_h_accums
const CGEN_HW_ENTRY m32r_cgen_hw_table []

Define Documentation

Definition at line 64 of file m32r-desc.h.

Definition at line 56 of file m32r-desc.h.

#define CGEN_ARCH   m32r

Definition at line 30 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)

Definition at line 178 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_HW_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)

Definition at line 176 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_HW_PC_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)

Definition at line 179 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)

Definition at line 180 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)

Definition at line 177 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)

Definition at line 144 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)

Definition at line 141 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)

Definition at line 143 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)

Definition at line 148 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)

Definition at line 145 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)

Definition at line 146 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)

Definition at line 147 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)

Definition at line 142 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)

Definition at line 254 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)

Definition at line 257 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)

Definition at line 259 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0)

Definition at line 264 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 252 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)

Definition at line 262 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_PBB_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)

Definition at line 263 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 253 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)

Definition at line 260 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)

Definition at line 261 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)

Definition at line 258 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0)

Definition at line 267 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0)

Definition at line 266 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0)

Definition at line 265 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)

Definition at line 256 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)

Definition at line 255 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)

Definition at line 210 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)

Definition at line 217 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)

Definition at line 207 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)

Definition at line 213 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)

Definition at line 209 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)

Definition at line 214 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)

Definition at line 216 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)

Definition at line 215 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)

Definition at line 211 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)

Definition at line 212 of file m32r-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)

Definition at line 208 of file m32r-desc.h.

Definition at line 173 of file m32r-desc.h.

Definition at line 138 of file m32r-desc.h.

#define CGEN_INSN_LSB0_P   0

Definition at line 45 of file m32r-desc.h.

Definition at line 249 of file m32r-desc.h.

#define CGEN_INT_INSN_P   1

Definition at line 53 of file m32r-desc.h.

#define CGEN_MAX_INSN_SIZE   4

Definition at line 51 of file m32r-desc.h.

#define CGEN_MIN_INSN_SIZE   2

Definition at line 48 of file m32r-desc.h.

Definition at line 61 of file m32r-desc.h.

Definition at line 204 of file m32r-desc.h.

#define CGEN_SYM (   s)    m32r_cgen_s

Definition at line 36 of file m32r-desc.h.

#define HAVE_CPU_M32R2F

Definition at line 43 of file m32r-desc.h.

#define HAVE_CPU_M32RBF

Definition at line 41 of file m32r-desc.h.

#define HAVE_CPU_M32RXF

Definition at line 42 of file m32r-desc.h.

#define MAX_HW   ((int) HW_MAX)

Definition at line 191 of file m32r-desc.h.

#define MAX_IFLD   ((int) M32R_F_MAX)

Definition at line 162 of file m32r-desc.h.

#define MAX_ISAS   1

Definition at line 123 of file m32r-desc.h.

#define MAX_MACHS   ((int) MACH_MAX)

Definition at line 124 of file m32r-desc.h.

#define MAX_OPERAND_INSTANCES   11

Definition at line 235 of file m32r-desc.h.

#define MAX_OPERANDS   28

Definition at line 232 of file m32r-desc.h.


Typedef Documentation

typedef enum cgen_hw_attr CGEN_HW_ATTR
typedef enum cgen_hw_type CGEN_HW_TYPE
typedef enum cr_names CR_NAMES
typedef enum gr_names GR_NAMES
typedef enum ifield_type IFIELD_TYPE
typedef enum insn_op1 INSN_OP1
typedef enum insn_op2 INSN_OP2
typedef enum isa_attr ISA_ATTR
typedef enum mach_attr MACH_ATTR
typedef enum pipe_attr PIPE_ATTR

Enumeration Type Documentation

Enumerator:
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_ISA 
CGEN_HW_RL_TYPE 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_IS_FLOAT 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_ISA 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 

Definition at line 167 of file m32r-desc.h.

Enumerator:
CGEN_HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_CR 
HW_H_DR 
HW_H_PS 
HW_H_R13 
HW_H_R14 
HW_H_R15 
HW_H_NBIT 
HW_H_ZBIT 
HW_H_VBIT 
HW_H_CBIT 
HW_H_IBIT 
HW_H_SBIT 
HW_H_TBIT 
HW_H_D0BIT 
HW_H_D1BIT 
HW_H_CCR 
HW_H_SCR 
HW_H_ILM 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_RELOC_ANN 
HW_H_PC 
HW_H_PSR_IMPLE 
HW_H_PSR_VER 
HW_H_PSR_ICE 
HW_H_PSR_NEM 
HW_H_PSR_CM 
HW_H_PSR_BE 
HW_H_PSR_ESR 
HW_H_PSR_EF 
HW_H_PSR_EM 
HW_H_PSR_PIL 
HW_H_PSR_PS 
HW_H_PSR_ET 
HW_H_PSR_S 
HW_H_TBR_TBA 
HW_H_TBR_TT 
HW_H_BPSR_BS 
HW_H_BPSR_BET 
HW_H_GR 
HW_H_GR_DOUBLE 
HW_H_GR_HI 
HW_H_GR_LO 
HW_H_FR 
HW_H_FR_DOUBLE 
HW_H_FR_INT 
HW_H_FR_HI 
HW_H_FR_LO 
HW_H_FR_0 
HW_H_FR_1 
HW_H_FR_2 
HW_H_FR_3 
HW_H_CPR 
HW_H_CPR_DOUBLE 
HW_H_SPR 
HW_H_ACCG 
HW_H_ACC40S 
HW_H_ACC40U 
HW_H_IACC0 
HW_H_ICCR 
HW_H_FCCR 
HW_H_CCCR 
HW_H_PACK 
HW_H_HINT_TAKEN 
HW_H_HINT_NOT_TAKEN 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_SPR 
HW_H_REGISTERS 
HW_H_STACK 
HW_H_PABITS 
HW_H_ZBIT 
HW_H_CBIT 
HW_H_DCBIT 
HW_H_PC 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_GR_QI 
HW_H_GR_HI 
HW_H_GR_SI 
HW_H_GR_EXT_QI 
HW_H_GR_EXT_HI 
HW_H_R0L 
HW_H_R0H 
HW_H_R1L 
HW_H_R1H 
HW_H_R0 
HW_H_R1 
HW_H_R2 
HW_H_R3 
HW_H_R0L_R0H 
HW_H_R2R0 
HW_H_R3R1 
HW_H_R1R2R0 
HW_H_AR 
HW_H_AR_QI 
HW_H_AR_HI 
HW_H_AR_SI 
HW_H_A0 
HW_H_A1 
HW_H_SB 
HW_H_FB 
HW_H_SP 
HW_H_SBIT 
HW_H_ZBIT 
HW_H_OBIT 
HW_H_CBIT 
HW_H_UBIT 
HW_H_IBIT 
HW_H_BBIT 
HW_H_DBIT 
HW_H_DCT0 
HW_H_DCT1 
HW_H_SVF 
HW_H_DRC0 
HW_H_DRC1 
HW_H_DMD0 
HW_H_DMD1 
HW_H_INTB 
HW_H_SVP 
HW_H_VCT 
HW_H_ISP 
HW_H_DMA0 
HW_H_DMA1 
HW_H_DRA0 
HW_H_DRA1 
HW_H_DSA0 
HW_H_DSA1 
HW_H_COND16 
HW_H_COND16C 
HW_H_COND16J 
HW_H_COND16J_5 
HW_H_COND32 
HW_H_CR1_32 
HW_H_CR2_32 
HW_H_CR3_32 
HW_H_CR_16 
HW_H_FLAGS 
HW_H_SHIMM 
HW_H_BIT_INDEX 
HW_H_SRC_INDEX 
HW_H_DST_INDEX 
HW_H_SRC_INDIRECT 
HW_H_DST_INDIRECT 
HW_H_NONE 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_HI16 
HW_H_SLO16 
HW_H_ULO16 
HW_H_GR 
HW_H_CR 
HW_H_ACCUM 
HW_H_ACCUMS 
HW_H_COND 
HW_H_PSW 
HW_H_BPSW 
HW_H_BBPSW 
HW_H_LOCK 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GPR 
HW_H_CSR 
HW_H_CR64 
HW_H_CR 
HW_H_CCR 
HW_H_CR_FMAX 
HW_H_CCR_FMAX 
HW_H_FMAX_COMPARE_I_P 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_SPR 
HW_H_PC 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_SR 
HW_H_HI16 
HW_H_LO16 
HW_H_CBIT 
HW_H_DELAY_INSN 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_EXT 
HW_H_PSW 
HW_H_GRB 
HW_H_CC 
HW_H_ECC 
HW_H_GRB8 
HW_H_R8 
HW_H_REGMEM8 
HW_H_REGDIV8 
HW_H_R0 
HW_H_R01 
HW_H_REGBMEM8 
HW_H_MEMGR8 
HW_H_COND 
HW_H_CBIT 
HW_H_SGTDIS 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_RB 
HW_H_RBJ 
HW_H_RPSW 
HW_H_Z8 
HW_H_Z16 
HW_H_CY 
HW_H_HC 
HW_H_OV 
HW_H_PT 
HW_H_S 
HW_H_BRANCHCOND 
HW_H_WORDSIZE 
HW_MAX 

Definition at line 183 of file m32r-desc.h.

Enumerator:
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_ISA 
CGEN_IFLD_RL_TYPE 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_RELOC 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_ISA 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_RELOC 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 

Definition at line 131 of file m32r-desc.h.

Enumerator:
CGEN_INSN_ALIAS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_NOT_IN_DELAY_SLOT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_PRIVILEGED 
CGEN_INSN_NON_EXCEPTING 
CGEN_INSN_CONDITIONAL 
CGEN_INSN_FR_ACCESS 
CGEN_INSN_PRESERVE_OVF 
CGEN_INSN_AUDIO 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_UNIT 
CGEN_INSN_FR400_MAJOR 
CGEN_INSN_FR450_MAJOR 
CGEN_INSN_FR500_MAJOR 
CGEN_INSN_FR550_MAJOR 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_EXT_SKIP_INSN 
CGEN_INSN_SKIPA 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_YIELD_INSN 
CGEN_INSN_LOAD_DELAY 
CGEN_INSN_EVEN_REG_NUM 
CGEN_INSN_UNSUPPORTED 
CGEN_INSN_USES_RD 
CGEN_INSN_USES_RS 
CGEN_INSN_USES_RT 
CGEN_INSN_USES_R31 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_ISA 
CGEN_INSN_RL_TYPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_FILL_SLOT 
CGEN_INSN_SPECIAL 
CGEN_INSN_SPECIAL_M32R 
CGEN_INSN_SPECIAL_FLOAT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_PIPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_OPTIONAL_BIT_INSN 
CGEN_INSN_OPTIONAL_MUL_INSN 
CGEN_INSN_OPTIONAL_DIV_INSN 
CGEN_INSN_OPTIONAL_DEBUG_INSN 
CGEN_INSN_OPTIONAL_LDZ_INSN 
CGEN_INSN_OPTIONAL_ABS_INSN 
CGEN_INSN_OPTIONAL_AVE_INSN 
CGEN_INSN_OPTIONAL_MINMAX_INSN 
CGEN_INSN_OPTIONAL_CLIP_INSN 
CGEN_INSN_OPTIONAL_SAT_INSN 
CGEN_INSN_OPTIONAL_UCI_INSN 
CGEN_INSN_OPTIONAL_DSP_INSN 
CGEN_INSN_OPTIONAL_CP_INSN 
CGEN_INSN_OPTIONAL_CP64_INSN 
CGEN_INSN_OPTIONAL_VLIW64 
CGEN_INSN_MAY_TRAP 
CGEN_INSN_VLIW_ALONE 
CGEN_INSN_VLIW_NO_CORE_NOP 
CGEN_INSN_VLIW_NO_COP_NOP 
CGEN_INSN_VLIW64_NO_MATCHING_NOP 
CGEN_INSN_VLIW32_NO_MATCHING_NOP 
CGEN_INSN_VOLATILE 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_ISA 
CGEN_INSN_LATENCY 
CGEN_INSN_CONFIG 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_LOAD_DELAY 
CGEN_INSN_MEMORY_ACCESS 
CGEN_INSN_AL_INSN 
CGEN_INSN_IO_INSN 
CGEN_INSN_BR_INSN 
CGEN_INSN_JAL_HAZARD 
CGEN_INSN_USES_FRDR 
CGEN_INSN_USES_FRDRRR 
CGEN_INSN_USES_FRSR1 
CGEN_INSN_USES_FRSR2 
CGEN_INSN_SKIPA 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_NOT_IN_DELAY_SLOT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_PIPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 

Definition at line 240 of file m32r-desc.h.

Enumerator:
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_ISA 
CGEN_OPERAND_RL_TYPE 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_RELOC 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_ISA 
CGEN_OPERAND_CDATA 
CGEN_OPERAND_ALIGN 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_RELOC 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_DOT_PREFIX 
CGEN_OPERAND_POF_PREFIX 
CGEN_OPERAND_PAG_PREFIX 
CGEN_OPERAND_SOF_PREFIX 
CGEN_OPERAND_SEG_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 

Definition at line 196 of file m32r-desc.h.

Enumerator:
CGEN_OPERAND_MAX 
FR30_OPERAND_PC 
FR30_OPERAND_RI 
FR30_OPERAND_RJ 
FR30_OPERAND_RIC 
FR30_OPERAND_RJC 
FR30_OPERAND_CRI 
FR30_OPERAND_CRJ 
FR30_OPERAND_RS1 
FR30_OPERAND_RS2 
FR30_OPERAND_R13 
FR30_OPERAND_R14 
FR30_OPERAND_R15 
FR30_OPERAND_PS 
FR30_OPERAND_U4 
FR30_OPERAND_U4C 
FR30_OPERAND_U8 
FR30_OPERAND_I8 
FR30_OPERAND_UDISP6 
FR30_OPERAND_DISP8 
FR30_OPERAND_DISP9 
FR30_OPERAND_DISP10 
FR30_OPERAND_S10 
FR30_OPERAND_U10 
FR30_OPERAND_I32 
FR30_OPERAND_M4 
FR30_OPERAND_I20 
FR30_OPERAND_DIR8 
FR30_OPERAND_DIR9 
FR30_OPERAND_DIR10 
FR30_OPERAND_LABEL9 
FR30_OPERAND_LABEL12 
FR30_OPERAND_REGLIST_LOW_LD 
FR30_OPERAND_REGLIST_HI_LD 
FR30_OPERAND_REGLIST_LOW_ST 
FR30_OPERAND_REGLIST_HI_ST 
FR30_OPERAND_CC 
FR30_OPERAND_CCC 
FR30_OPERAND_NBIT 
FR30_OPERAND_VBIT 
FR30_OPERAND_ZBIT 
FR30_OPERAND_CBIT 
FR30_OPERAND_IBIT 
FR30_OPERAND_SBIT 
FR30_OPERAND_TBIT 
FR30_OPERAND_D0BIT 
FR30_OPERAND_D1BIT 
FR30_OPERAND_CCR 
FR30_OPERAND_SCR 
FR30_OPERAND_ILM 
FR30_OPERAND_MAX 
FRV_OPERAND_PC 
FRV_OPERAND_PACK 
FRV_OPERAND_GRI 
FRV_OPERAND_GRJ 
FRV_OPERAND_GRK 
FRV_OPERAND_GRKHI 
FRV_OPERAND_GRKLO 
FRV_OPERAND_GRDOUBLEK 
FRV_OPERAND_ACC40SI 
FRV_OPERAND_ACC40UI 
FRV_OPERAND_ACC40SK 
FRV_OPERAND_ACC40UK 
FRV_OPERAND_ACCGI 
FRV_OPERAND_ACCGK 
FRV_OPERAND_CPRI 
FRV_OPERAND_CPRJ 
FRV_OPERAND_CPRK 
FRV_OPERAND_CPRDOUBLEK 
FRV_OPERAND_FRINTI 
FRV_OPERAND_FRINTJ 
FRV_OPERAND_FRINTK 
FRV_OPERAND_FRI 
FRV_OPERAND_FRJ 
FRV_OPERAND_FRK 
FRV_OPERAND_FRKHI 
FRV_OPERAND_FRKLO 
FRV_OPERAND_FRDOUBLEI 
FRV_OPERAND_FRDOUBLEJ 
FRV_OPERAND_FRDOUBLEK 
FRV_OPERAND_CRI 
FRV_OPERAND_CRJ 
FRV_OPERAND_CRJ_INT 
FRV_OPERAND_CRJ_FLOAT 
FRV_OPERAND_CRK 
FRV_OPERAND_CCI 
FRV_OPERAND_ICCI_1 
FRV_OPERAND_ICCI_2 
FRV_OPERAND_ICCI_3 
FRV_OPERAND_FCCI_1 
FRV_OPERAND_FCCI_2 
FRV_OPERAND_FCCI_3 
FRV_OPERAND_FCCK 
FRV_OPERAND_EIR 
FRV_OPERAND_S10 
FRV_OPERAND_U16 
FRV_OPERAND_S16 
FRV_OPERAND_S6 
FRV_OPERAND_S6_1 
FRV_OPERAND_U6 
FRV_OPERAND_S5 
FRV_OPERAND_COND 
FRV_OPERAND_CCOND 
FRV_OPERAND_HINT 
FRV_OPERAND_HINT_TAKEN 
FRV_OPERAND_HINT_NOT_TAKEN 
FRV_OPERAND_LI 
FRV_OPERAND_LOCK 
FRV_OPERAND_DEBUG 
FRV_OPERAND_AE 
FRV_OPERAND_LABEL16 
FRV_OPERAND_LRAE 
FRV_OPERAND_LRAD 
FRV_OPERAND_LRAS 
FRV_OPERAND_TLBPROPX 
FRV_OPERAND_TLBPRL 
FRV_OPERAND_A0 
FRV_OPERAND_A1 
FRV_OPERAND_FRINTIEVEN 
FRV_OPERAND_FRINTJEVEN 
FRV_OPERAND_FRINTKEVEN 
FRV_OPERAND_D12 
FRV_OPERAND_S12 
FRV_OPERAND_U12 
FRV_OPERAND_SPR 
FRV_OPERAND_ULO16 
FRV_OPERAND_SLO16 
FRV_OPERAND_UHI16 
FRV_OPERAND_LABEL24 
FRV_OPERAND_PSR_ESR 
FRV_OPERAND_PSR_S 
FRV_OPERAND_PSR_PS 
FRV_OPERAND_PSR_ET 
FRV_OPERAND_BPSR_BS 
FRV_OPERAND_BPSR_BET 
FRV_OPERAND_TBR_TBA 
FRV_OPERAND_TBR_TT 
FRV_OPERAND_LDANN 
FRV_OPERAND_LDDANN 
FRV_OPERAND_CALLANN 
FRV_OPERAND_MAX 
IP2K_OPERAND_PC 
IP2K_OPERAND_ADDR16CJP 
IP2K_OPERAND_FR 
IP2K_OPERAND_LIT8 
IP2K_OPERAND_BITNO 
IP2K_OPERAND_ADDR16P 
IP2K_OPERAND_ADDR16H 
IP2K_OPERAND_ADDR16L 
IP2K_OPERAND_RETI3 
IP2K_OPERAND_PABITS 
IP2K_OPERAND_ZBIT 
IP2K_OPERAND_CBIT 
IP2K_OPERAND_DCBIT 
IP2K_OPERAND_MAX 
IQ2000_OPERAND_PC 
IQ2000_OPERAND_RS 
IQ2000_OPERAND_RT 
IQ2000_OPERAND_RD 
IQ2000_OPERAND_RD_RS 
IQ2000_OPERAND_RD_RT 
IQ2000_OPERAND_RT_RS 
IQ2000_OPERAND_SHAMT 
IQ2000_OPERAND_IMM 
IQ2000_OPERAND_OFFSET 
IQ2000_OPERAND_BASEOFF 
IQ2000_OPERAND_JMPTARG 
IQ2000_OPERAND_MASK 
IQ2000_OPERAND_MASKQ10 
IQ2000_OPERAND_MASKL 
IQ2000_OPERAND_COUNT 
IQ2000_OPERAND__INDEX 
IQ2000_OPERAND_EXECODE 
IQ2000_OPERAND_BYTECOUNT 
IQ2000_OPERAND_CAM_Y 
IQ2000_OPERAND_CAM_Z 
IQ2000_OPERAND_CM_3FUNC 
IQ2000_OPERAND_CM_4FUNC 
IQ2000_OPERAND_CM_3Z 
IQ2000_OPERAND_CM_4Z 
IQ2000_OPERAND_BASE 
IQ2000_OPERAND_MASKR 
IQ2000_OPERAND_BITNUM 
IQ2000_OPERAND_HI16 
IQ2000_OPERAND_LO16 
IQ2000_OPERAND_MLO16 
IQ2000_OPERAND_JMPTARGQ10 
IQ2000_OPERAND_MAX 
M32C_OPERAND_PC 
M32C_OPERAND_SRC16RNQI 
M32C_OPERAND_SRC16RNHI 
M32C_OPERAND_SRC32RNUNPREFIXEDQI 
M32C_OPERAND_SRC32RNUNPREFIXEDHI 
M32C_OPERAND_SRC32RNUNPREFIXEDSI 
M32C_OPERAND_SRC32RNPREFIXEDQI 
M32C_OPERAND_SRC32RNPREFIXEDHI 
M32C_OPERAND_SRC32RNPREFIXEDSI 
M32C_OPERAND_SRC16AN 
M32C_OPERAND_SRC16ANQI 
M32C_OPERAND_SRC16ANHI 
M32C_OPERAND_SRC32ANUNPREFIXED 
M32C_OPERAND_SRC32ANUNPREFIXEDQI 
M32C_OPERAND_SRC32ANUNPREFIXEDHI 
M32C_OPERAND_SRC32ANUNPREFIXEDSI 
M32C_OPERAND_SRC32ANPREFIXED 
M32C_OPERAND_SRC32ANPREFIXEDQI 
M32C_OPERAND_SRC32ANPREFIXEDHI 
M32C_OPERAND_SRC32ANPREFIXEDSI 
M32C_OPERAND_DST16RNQI 
M32C_OPERAND_DST16RNHI 
M32C_OPERAND_DST16RNSI 
M32C_OPERAND_DST16RNEXTQI 
M32C_OPERAND_DST32R0QI_S 
M32C_OPERAND_DST32R0HI_S 
M32C_OPERAND_DST32RNUNPREFIXEDQI 
M32C_OPERAND_DST32RNUNPREFIXEDHI 
M32C_OPERAND_DST32RNUNPREFIXEDSI 
M32C_OPERAND_DST32RNEXTUNPREFIXEDQI 
M32C_OPERAND_DST32RNEXTUNPREFIXEDHI 
M32C_OPERAND_DST32RNPREFIXEDQI 
M32C_OPERAND_DST32RNPREFIXEDHI 
M32C_OPERAND_DST32RNPREFIXEDSI 
M32C_OPERAND_DST16RNQI_S 
M32C_OPERAND_DST16ANQI_S 
M32C_OPERAND_BIT16RN 
M32C_OPERAND_BIT32RNPREFIXED 
M32C_OPERAND_BIT32RNUNPREFIXED 
M32C_OPERAND_R0 
M32C_OPERAND_R1 
M32C_OPERAND_R2 
M32C_OPERAND_R3 
M32C_OPERAND_R0L 
M32C_OPERAND_R0H 
M32C_OPERAND_R2R0 
M32C_OPERAND_R3R1 
M32C_OPERAND_R1R2R0 
M32C_OPERAND_DST16AN 
M32C_OPERAND_DST16ANQI 
M32C_OPERAND_DST16ANHI 
M32C_OPERAND_DST16ANSI 
M32C_OPERAND_DST16AN_S 
M32C_OPERAND_DST32ANUNPREFIXED 
M32C_OPERAND_DST32ANUNPREFIXEDQI 
M32C_OPERAND_DST32ANUNPREFIXEDHI 
M32C_OPERAND_DST32ANUNPREFIXEDSI 
M32C_OPERAND_DST32ANEXTUNPREFIXED 
M32C_OPERAND_DST32ANPREFIXED 
M32C_OPERAND_DST32ANPREFIXEDQI 
M32C_OPERAND_DST32ANPREFIXEDHI 
M32C_OPERAND_DST32ANPREFIXEDSI 
M32C_OPERAND_BIT16AN 
M32C_OPERAND_BIT32ANPREFIXED 
M32C_OPERAND_BIT32ANUNPREFIXED 
M32C_OPERAND_A0 
M32C_OPERAND_A1 
M32C_OPERAND_SB 
M32C_OPERAND_FB 
M32C_OPERAND_SP 
M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL 
M32C_OPERAND_REGSETPOP 
M32C_OPERAND_REGSETPUSH 
M32C_OPERAND_RN16_PUSH_S 
M32C_OPERAND_AN16_PUSH_S 
M32C_OPERAND_DSP_8_U6 
M32C_OPERAND_DSP_8_U8 
M32C_OPERAND_DSP_8_U16 
M32C_OPERAND_DSP_8_S8 
M32C_OPERAND_DSP_8_S24 
M32C_OPERAND_DSP_8_U24 
M32C_OPERAND_DSP_10_U6 
M32C_OPERAND_DSP_16_U8 
M32C_OPERAND_DSP_16_U16 
M32C_OPERAND_DSP_16_U20 
M32C_OPERAND_DSP_16_U24 
M32C_OPERAND_DSP_16_S8 
M32C_OPERAND_DSP_16_S16 
M32C_OPERAND_DSP_24_U8 
M32C_OPERAND_DSP_24_U16 
M32C_OPERAND_DSP_24_U20 
M32C_OPERAND_DSP_24_U24 
M32C_OPERAND_DSP_24_S8 
M32C_OPERAND_DSP_24_S16 
M32C_OPERAND_DSP_32_U8 
M32C_OPERAND_DSP_32_U16 
M32C_OPERAND_DSP_32_U24 
M32C_OPERAND_DSP_32_U20 
M32C_OPERAND_DSP_32_S8 
M32C_OPERAND_DSP_32_S16 
M32C_OPERAND_DSP_40_U8 
M32C_OPERAND_DSP_40_S8 
M32C_OPERAND_DSP_40_U16 
M32C_OPERAND_DSP_40_S16 
M32C_OPERAND_DSP_40_U20 
M32C_OPERAND_DSP_40_U24 
M32C_OPERAND_DSP_48_U8 
M32C_OPERAND_DSP_48_S8 
M32C_OPERAND_DSP_48_U16 
M32C_OPERAND_DSP_48_S16 
M32C_OPERAND_DSP_48_U20 
M32C_OPERAND_DSP_48_U24 
M32C_OPERAND_IMM_8_S4 
M32C_OPERAND_IMM_8_S4N 
M32C_OPERAND_IMM_SH_8_S4 
M32C_OPERAND_IMM_8_QI 
M32C_OPERAND_IMM_8_HI 
M32C_OPERAND_IMM_12_S4 
M32C_OPERAND_IMM_12_S4N 
M32C_OPERAND_IMM_SH_12_S4 
M32C_OPERAND_IMM_13_U3 
M32C_OPERAND_IMM_20_S4 
M32C_OPERAND_IMM_SH_20_S4 
M32C_OPERAND_IMM_16_QI 
M32C_OPERAND_IMM_16_HI 
M32C_OPERAND_IMM_16_SI 
M32C_OPERAND_IMM_24_QI 
M32C_OPERAND_IMM_24_HI 
M32C_OPERAND_IMM_24_SI 
M32C_OPERAND_IMM_32_QI 
M32C_OPERAND_IMM_32_SI 
M32C_OPERAND_IMM_32_HI 
M32C_OPERAND_IMM_40_QI 
M32C_OPERAND_IMM_40_HI 
M32C_OPERAND_IMM_40_SI 
M32C_OPERAND_IMM_48_QI 
M32C_OPERAND_IMM_48_HI 
M32C_OPERAND_IMM_48_SI 
M32C_OPERAND_IMM_56_QI 
M32C_OPERAND_IMM_56_HI 
M32C_OPERAND_IMM_64_HI 
M32C_OPERAND_IMM1_S 
M32C_OPERAND_IMM3_S 
M32C_OPERAND_BIT3_S 
M32C_OPERAND_BITNO16R 
M32C_OPERAND_BITNO32PREFIXED 
M32C_OPERAND_BITNO32UNPREFIXED 
M32C_OPERAND_BITBASE16_16_U8 
M32C_OPERAND_BITBASE16_16_S8 
M32C_OPERAND_BITBASE16_16_U16 
M32C_OPERAND_BITBASE16_8_U11_S 
M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED 
M32C_OPERAND_BITBASE32_24_U11_PREFIXED 
M32C_OPERAND_BITBASE32_24_S11_PREFIXED 
M32C_OPERAND_BITBASE32_24_U19_PREFIXED 
M32C_OPERAND_BITBASE32_24_S19_PREFIXED 
M32C_OPERAND_BITBASE32_24_U27_PREFIXED 
M32C_OPERAND_LAB_5_3 
M32C_OPERAND_LAB32_JMP_S 
M32C_OPERAND_LAB_8_8 
M32C_OPERAND_LAB_8_16 
M32C_OPERAND_LAB_8_24 
M32C_OPERAND_LAB_16_8 
M32C_OPERAND_LAB_24_8 
M32C_OPERAND_LAB_32_8 
M32C_OPERAND_LAB_40_8 
M32C_OPERAND_SBIT 
M32C_OPERAND_OBIT 
M32C_OPERAND_ZBIT 
M32C_OPERAND_CBIT 
M32C_OPERAND_UBIT 
M32C_OPERAND_IBIT 
M32C_OPERAND_BBIT 
M32C_OPERAND_DBIT 
M32C_OPERAND_COND16_16 
M32C_OPERAND_COND16_24 
M32C_OPERAND_COND16_32 
M32C_OPERAND_COND32_16 
M32C_OPERAND_COND32_24 
M32C_OPERAND_COND32_32 
M32C_OPERAND_COND32_40 
M32C_OPERAND_COND16C 
M32C_OPERAND_COND16J 
M32C_OPERAND_COND16J5 
M32C_OPERAND_COND32 
M32C_OPERAND_COND32J 
M32C_OPERAND_SCCOND32 
M32C_OPERAND_FLAGS16 
M32C_OPERAND_FLAGS32 
M32C_OPERAND_CR16 
M32C_OPERAND_CR1_UNPREFIXED_32 
M32C_OPERAND_CR1_PREFIXED_32 
M32C_OPERAND_CR2_32 
M32C_OPERAND_CR3_UNPREFIXED_32 
M32C_OPERAND_CR3_PREFIXED_32 
M32C_OPERAND_Z 
M32C_OPERAND_S 
M32C_OPERAND_Q 
M32C_OPERAND_G 
M32C_OPERAND_X 
M32C_OPERAND_SIZE 
M32C_OPERAND_BITINDEX 
M32C_OPERAND_SRCINDEX 
M32C_OPERAND_DSTINDEX 
M32C_OPERAND_NOREMAINDER 
M32C_OPERAND_SRC16_RN_DIRECT_QI 
M32C_OPERAND_SRC16_RN_DIRECT_HI 
M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI 
M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI 
M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI 
M32C_OPERAND_SRC16_AN_DIRECT_QI 
M32C_OPERAND_SRC16_AN_DIRECT_HI 
M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI 
M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI 
M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI 
M32C_OPERAND_SRC16_AN_INDIRECT_QI 
M32C_OPERAND_SRC16_AN_INDIRECT_HI 
M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI 
M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI 
M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI 
M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI 
M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI 
M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI 
M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI 
M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI 
M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI 
M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI 
M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI 
M32C_OPERAND_SRC16_16_20_AN_RELATIVE_QI 
M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI 
M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI 
M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI 
M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI 
M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI 
M32C_OPERAND_SRC16_16_20_AN_RELATIVE_HI 
M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI 
M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI 
M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI 
M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI 
M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI 
M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI 
M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI 
M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI 
M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI 
M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI 
M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_RN_DIRECT_QI 
M32C_OPERAND_DST16_RN_DIRECT_HI 
M32C_OPERAND_DST16_RN_DIRECT_SI 
M32C_OPERAND_DST16_RN_DIRECT_EXT_QI 
M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI 
M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI 
M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI 
M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST16_AN_DIRECT_QI 
M32C_OPERAND_DST16_AN_DIRECT_HI 
M32C_OPERAND_DST16_AN_DIRECT_SI 
M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI 
M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI 
M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI 
M32C_OPERAND_DST16_AN_INDIRECT_QI 
M32C_OPERAND_DST16_AN_INDIRECT_HI 
M32C_OPERAND_DST16_AN_INDIRECT_SI 
M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI 
M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI 
M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI 
M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_16_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_24_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_32_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_40_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_48_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_16_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_24_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_32_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_40_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_48_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_16_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_24_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_32_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_40_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_48_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_24_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_32_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_40_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_48_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_24_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_32_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_40_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_48_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_24_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_32_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_40_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_48_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI 
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M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI 
M32C_OPERAND_BIT16_RN_DIRECT 
M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED 
M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED 
M32C_OPERAND_BIT16_AN_DIRECT 
M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED 
M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED 
M32C_OPERAND_BIT16_AN_INDIRECT 
M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED 
M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED 
M32C_OPERAND_BIT16_16_8_SB_RELATIVE 
M32C_OPERAND_BIT16_16_16_SB_RELATIVE 
M32C_OPERAND_BIT16_16_8_FB_RELATIVE 
M32C_OPERAND_BIT16_16_8_AN_RELATIVE 
M32C_OPERAND_BIT16_16_16_AN_RELATIVE 
M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED 
M32C_OPERAND_BIT16_11_SB_RELATIVE_S 
M32C_OPERAND_RN16_PUSH_S_DERIVED 
M32C_OPERAND_AN16_PUSH_S_DERIVED 
M32C_OPERAND_BIT16_16_16_ABSOLUTE 
M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED 
M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED 
M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED 
M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED 
M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI 
M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI 
M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI 
M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED 
M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI 
M32C_OPERAND_DST32_2_S_R0_DIRECT_HI 
M32C_OPERAND_DST32_1_S_A0_DIRECT_HI 
M32C_OPERAND_DST32_1_S_A1_DIRECT_HI 
M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI 
M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI 
M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI 
M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI 
M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI 
M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI 
M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI 
M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI 
M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI 
M32C_OPERAND_SRC16_BASIC_QI 
M32C_OPERAND_SRC16_BASIC_HI 
M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI 
M32C_OPERAND_SRC32_BASIC_PREFIXED_QI 
M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI 
M32C_OPERAND_SRC32_BASIC_PREFIXED_HI 
M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI 
M32C_OPERAND_SRC32_BASIC_PREFIXED_SI 
M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI 
M32C_OPERAND_SRC16_16_8_QI 
M32C_OPERAND_SRC16_16_16_QI 
M32C_OPERAND_SRC16_16_8_HI 
M32C_OPERAND_SRC16_16_16_HI 
M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI 
M32C_OPERAND_SRC32_24_8_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_PREFIXED_QI 
M32C_OPERAND_SRC32_24_24_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_PREFIXED_HI 
M32C_OPERAND_SRC32_24_24_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_PREFIXED_SI 
M32C_OPERAND_SRC32_24_24_PREFIXED_SI 
M32C_OPERAND_DST16_BASIC_QI 
M32C_OPERAND_DST16_BASIC_HI 
M32C_OPERAND_DST16_BASIC_SI 
M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI 
M32C_OPERAND_DST32_BASIC_PREFIXED_QI 
M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI 
M32C_OPERAND_DST32_BASIC_PREFIXED_HI 
M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI 
M32C_OPERAND_DST32_BASIC_PREFIXED_SI 
M32C_OPERAND_DST16_16_QI 
M32C_OPERAND_DST16_16_8_QI 
M32C_OPERAND_DST16_16_16_QI 
M32C_OPERAND_DST16_16_16SA_QI 
M32C_OPERAND_DST16_16_20AR_QI 
M32C_OPERAND_DST16_16_HI 
M32C_OPERAND_DST16_16_8_HI 
M32C_OPERAND_DST16_16_16_HI 
M32C_OPERAND_DST16_16_16SA_HI 
M32C_OPERAND_DST16_16_20AR_HI 
M32C_OPERAND_DST16_16_SI 
M32C_OPERAND_DST16_16_8_SI 
M32C_OPERAND_DST16_16_16_SI 
M32C_OPERAND_DST16_16_16SA_SI 
M32C_OPERAND_DST16_16_20AR_SI 
M32C_OPERAND_DST16_16_EXT_QI 
M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI 
M32C_OPERAND_DST16_16_MOVA_HI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16SA_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16SA_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_8_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16SA_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_24_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI 
M32C_OPERAND_DST16_24_QI 
M32C_OPERAND_DST16_24_HI 
M32C_OPERAND_DST32_24_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_PREFIXED_QI 
M32C_OPERAND_DST32_24_24_PREFIXED_QI 
M32C_OPERAND_DST32_24_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_PREFIXED_HI 
M32C_OPERAND_DST32_24_24_PREFIXED_HI 
M32C_OPERAND_DST32_24_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_PREFIXED_SI 
M32C_OPERAND_DST32_24_8_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_PREFIXED_SI 
M32C_OPERAND_DST32_24_24_PREFIXED_SI 
M32C_OPERAND_DST16_32_QI 
M32C_OPERAND_DST16_32_HI 
M32C_OPERAND_DST32_32_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_PREFIXED_QI 
M32C_OPERAND_DST32_32_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_PREFIXED_HI 
M32C_OPERAND_DST32_32_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_PREFIXED_SI 
M32C_OPERAND_DST32_40_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_PREFIXED_QI 
M32C_OPERAND_DST32_40_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_PREFIXED_HI 
M32C_OPERAND_DST32_40_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_PREFIXED_SI 
M32C_OPERAND_DST32_48_PREFIXED_QI 
M32C_OPERAND_DST32_48_PREFIXED_HI 
M32C_OPERAND_DST32_48_PREFIXED_SI 
M32C_OPERAND_BIT16_16 
M32C_OPERAND_BIT16_16_BASIC 
M32C_OPERAND_BIT16_16_8 
M32C_OPERAND_BIT16_16_16 
M32C_OPERAND_BIT32_16_UNPREFIXED 
M32C_OPERAND_BIT32_24_PREFIXED 
M32C_OPERAND_BIT32_BASIC_UNPREFIXED 
M32C_OPERAND_BIT32_16_8_UNPREFIXED 
M32C_OPERAND_BIT32_16_16_UNPREFIXED 
M32C_OPERAND_BIT32_16_24_UNPREFIXED 
M32C_OPERAND_SRC16_2_S 
M32C_OPERAND_SRC32_2_S_QI 
M32C_OPERAND_SRC32_2_S_HI 
M32C_OPERAND_DST16_3_S_8 
M32C_OPERAND_DST16_3_S_16 
M32C_OPERAND_SRCDST16_R0L_R0H_S 
M32C_OPERAND_DST32_2_S_BASIC_QI 
M32C_OPERAND_DST32_2_S_BASIC_HI 
M32C_OPERAND_DST32_2_S_8_QI 
M32C_OPERAND_DST32_2_S_16_QI 
M32C_OPERAND_DST32_2_S_8_HI 
M32C_OPERAND_DST32_2_S_16_HI 
M32C_OPERAND_DST32_2_S_8_SI 
M32C_OPERAND_DST32_2_S_16_SI 
M32C_OPERAND_DST32_AN_S 
M32C_OPERAND_BIT16_11_S 
M32C_OPERAND_RN16_PUSH_S_ANYOF 
M32C_OPERAND_AN16_PUSH_S_ANYOF 
M32C_OPERAND_MAX 
M32R_OPERAND_PC 
M32R_OPERAND_SR 
M32R_OPERAND_DR 
M32R_OPERAND_SRC1 
M32R_OPERAND_SRC2 
M32R_OPERAND_SCR 
M32R_OPERAND_DCR 
M32R_OPERAND_SIMM8 
M32R_OPERAND_SIMM16 
M32R_OPERAND_UIMM3 
M32R_OPERAND_UIMM4 
M32R_OPERAND_UIMM5 
M32R_OPERAND_UIMM8 
M32R_OPERAND_UIMM16 
M32R_OPERAND_IMM1 
M32R_OPERAND_ACCD 
M32R_OPERAND_ACCS 
M32R_OPERAND_ACC 
M32R_OPERAND_HASH 
M32R_OPERAND_HI16 
M32R_OPERAND_SLO16 
M32R_OPERAND_ULO16 
M32R_OPERAND_UIMM24 
M32R_OPERAND_DISP8 
M32R_OPERAND_DISP16 
M32R_OPERAND_DISP24 
M32R_OPERAND_CONDBIT 
M32R_OPERAND_ACCUM 
M32R_OPERAND_MAX 
MEP_OPERAND_PC 
MEP_OPERAND_R0 
MEP_OPERAND_RN 
MEP_OPERAND_RM 
MEP_OPERAND_RL 
MEP_OPERAND_RN3 
MEP_OPERAND_RMA 
MEP_OPERAND_RNC 
MEP_OPERAND_RNUC 
MEP_OPERAND_RNS 
MEP_OPERAND_RNUS 
MEP_OPERAND_RNL 
MEP_OPERAND_RNUL 
MEP_OPERAND_RN3C 
MEP_OPERAND_RN3UC 
MEP_OPERAND_RN3S 
MEP_OPERAND_RN3US 
MEP_OPERAND_RN3L 
MEP_OPERAND_RN3UL 
MEP_OPERAND_LP 
MEP_OPERAND_SAR 
MEP_OPERAND_HI 
MEP_OPERAND_LO 
MEP_OPERAND_MB0 
MEP_OPERAND_ME0 
MEP_OPERAND_MB1 
MEP_OPERAND_ME1 
MEP_OPERAND_PSW 
MEP_OPERAND_EPC 
MEP_OPERAND_EXC 
MEP_OPERAND_NPC 
MEP_OPERAND_DBG 
MEP_OPERAND_DEPC 
MEP_OPERAND_OPT 
MEP_OPERAND_R1 
MEP_OPERAND_TP 
MEP_OPERAND_SP 
MEP_OPERAND_TPR 
MEP_OPERAND_SPR 
MEP_OPERAND_CSRN 
MEP_OPERAND_CSRN_IDX 
MEP_OPERAND_CRN64 
MEP_OPERAND_CRN 
MEP_OPERAND_CRNX64 
MEP_OPERAND_CRNX 
MEP_OPERAND_CCRN 
MEP_OPERAND_CCCC 
MEP_OPERAND_PCREL8A2 
MEP_OPERAND_PCREL12A2 
MEP_OPERAND_PCREL17A2 
MEP_OPERAND_PCREL24A2 
MEP_OPERAND_PCABS24A2 
MEP_OPERAND_SDISP16 
MEP_OPERAND_SIMM16 
MEP_OPERAND_UIMM16 
MEP_OPERAND_CODE16 
MEP_OPERAND_UDISP2 
MEP_OPERAND_UIMM2 
MEP_OPERAND_SIMM6 
MEP_OPERAND_SIMM8 
MEP_OPERAND_ADDR24A4 
MEP_OPERAND_CODE24 
MEP_OPERAND_CALLNUM 
MEP_OPERAND_UIMM3 
MEP_OPERAND_UIMM4 
MEP_OPERAND_UIMM5 
MEP_OPERAND_UDISP7 
MEP_OPERAND_UDISP7A2 
MEP_OPERAND_UDISP7A4 
MEP_OPERAND_UIMM7A4 
MEP_OPERAND_UIMM24 
MEP_OPERAND_CIMM4 
MEP_OPERAND_CIMM5 
MEP_OPERAND_CDISP8 
MEP_OPERAND_CDISP8A2 
MEP_OPERAND_CDISP8A4 
MEP_OPERAND_CDISP8A8 
MEP_OPERAND_ZERO 
MEP_OPERAND_CP_FLAG 
MEP_OPERAND_FMAX_FRD 
MEP_OPERAND_FMAX_FRN 
MEP_OPERAND_FMAX_FRM 
MEP_OPERAND_FMAX_FRD_INT 
MEP_OPERAND_FMAX_FRN_INT 
MEP_OPERAND_FMAX_CCRN 
MEP_OPERAND_FMAX_CIRR 
MEP_OPERAND_FMAX_CBCR 
MEP_OPERAND_FMAX_CERR 
MEP_OPERAND_FMAX_RM 
MEP_OPERAND_FMAX_COMPARE_I_P 
MEP_OPERAND_MAX 
MT_OPERAND_PC 
MT_OPERAND_FRSR1 
MT_OPERAND_FRSR2 
MT_OPERAND_FRDR 
MT_OPERAND_FRDRRR 
MT_OPERAND_IMM16 
MT_OPERAND_IMM16Z 
MT_OPERAND_IMM16O 
MT_OPERAND_RC 
MT_OPERAND_RCNUM 
MT_OPERAND_CONTNUM 
MT_OPERAND_RBBC 
MT_OPERAND_COLNUM 
MT_OPERAND_ROWNUM 
MT_OPERAND_ROWNUM1 
MT_OPERAND_ROWNUM2 
MT_OPERAND_RC1 
MT_OPERAND_RC2 
MT_OPERAND_CBRB 
MT_OPERAND_CELL 
MT_OPERAND_DUP 
MT_OPERAND_CTXDISP 
MT_OPERAND_FBDISP 
MT_OPERAND_TYPE 
MT_OPERAND_MASK 
MT_OPERAND_BANKADDR 
MT_OPERAND_INCAMT 
MT_OPERAND_XMODE 
MT_OPERAND_MASK1 
MT_OPERAND_BALL 
MT_OPERAND_BRC 
MT_OPERAND_RDA 
MT_OPERAND_WR 
MT_OPERAND_BALL2 
MT_OPERAND_BRC2 
MT_OPERAND_PERM 
MT_OPERAND_A23 
MT_OPERAND_CR 
MT_OPERAND_CBS 
MT_OPERAND_INCR 
MT_OPERAND_LENGTH 
MT_OPERAND_CBX 
MT_OPERAND_CCB 
MT_OPERAND_CDB 
MT_OPERAND_MODE 
MT_OPERAND_ID 
MT_OPERAND_SIZE 
MT_OPERAND_FBINCR 
MT_OPERAND_LOOPSIZE 
MT_OPERAND_IMM16L 
MT_OPERAND_RC3 
MT_OPERAND_CB1SEL 
MT_OPERAND_CB2SEL 
MT_OPERAND_CB1INCR 
MT_OPERAND_CB2INCR 
MT_OPERAND_MAX 
OPENRISC_OPERAND_PC 
OPENRISC_OPERAND_SR 
OPENRISC_OPERAND_CBIT 
OPENRISC_OPERAND_SIMM_16 
OPENRISC_OPERAND_UIMM_16 
OPENRISC_OPERAND_DISP_26 
OPENRISC_OPERAND_ABS_26 
OPENRISC_OPERAND_UIMM_5 
OPENRISC_OPERAND_RD 
OPENRISC_OPERAND_RA 
OPENRISC_OPERAND_RB 
OPENRISC_OPERAND_OP_F_23 
OPENRISC_OPERAND_OP_F_3 
OPENRISC_OPERAND_HI16 
OPENRISC_OPERAND_LO16 
OPENRISC_OPERAND_UI16NC 
OPENRISC_OPERAND_MAX 
XC16X_OPERAND_PC 
XC16X_OPERAND_SR 
XC16X_OPERAND_DR 
XC16X_OPERAND_DRI 
XC16X_OPERAND_SRB 
XC16X_OPERAND_DRB 
XC16X_OPERAND_SR2 
XC16X_OPERAND_SRC1 
XC16X_OPERAND_SRC2 
XC16X_OPERAND_SRDIV 
XC16X_OPERAND_REGNAM 
XC16X_OPERAND_UIMM2 
XC16X_OPERAND_UIMM3 
XC16X_OPERAND_UIMM4 
XC16X_OPERAND_UIMM7 
XC16X_OPERAND_UIMM8 
XC16X_OPERAND_UIMM16 
XC16X_OPERAND_UPOF16 
XC16X_OPERAND_REG8 
XC16X_OPERAND_REGMEM8 
XC16X_OPERAND_REGBMEM8 
XC16X_OPERAND_REGOFF8 
XC16X_OPERAND_REGHI8 
XC16X_OPERAND_REGB8 
XC16X_OPERAND_GENREG 
XC16X_OPERAND_SEG 
XC16X_OPERAND_SEGHI8 
XC16X_OPERAND_CADDR 
XC16X_OPERAND_REL 
XC16X_OPERAND_RELHI 
XC16X_OPERAND_CONDBIT 
XC16X_OPERAND_BIT1 
XC16X_OPERAND_BIT2 
XC16X_OPERAND_BIT4 
XC16X_OPERAND_LBIT4 
XC16X_OPERAND_LBIT2 
XC16X_OPERAND_BIT8 
XC16X_OPERAND_U4 
XC16X_OPERAND_BITONE 
XC16X_OPERAND_BIT01 
XC16X_OPERAND_COND 
XC16X_OPERAND_ICOND 
XC16X_OPERAND_EXTCOND 
XC16X_OPERAND_MEMORY 
XC16X_OPERAND_MEMGR8 
XC16X_OPERAND_CBIT 
XC16X_OPERAND_QBIT 
XC16X_OPERAND_QLOBIT 
XC16X_OPERAND_QHIBIT 
XC16X_OPERAND_MASK8 
XC16X_OPERAND_MASKLO8 
XC16X_OPERAND_PAGENUM 
XC16X_OPERAND_DATA8 
XC16X_OPERAND_DATAHI8 
XC16X_OPERAND_SGTDISBIT 
XC16X_OPERAND_UPAG16 
XC16X_OPERAND_USEG8 
XC16X_OPERAND_USEG16 
XC16X_OPERAND_USOF16 
XC16X_OPERAND_HASH 
XC16X_OPERAND_DOT 
XC16X_OPERAND_POF 
XC16X_OPERAND_PAG 
XC16X_OPERAND_SOF 
XC16X_OPERAND_SEGM 
XC16X_OPERAND_MAX 
XSTORMY16_OPERAND_PC 
XSTORMY16_OPERAND_PSW_Z8 
XSTORMY16_OPERAND_PSW_Z16 
XSTORMY16_OPERAND_PSW_CY 
XSTORMY16_OPERAND_PSW_HC 
XSTORMY16_OPERAND_PSW_OV 
XSTORMY16_OPERAND_PSW_PT 
XSTORMY16_OPERAND_PSW_S 
XSTORMY16_OPERAND_RD 
XSTORMY16_OPERAND_RDM 
XSTORMY16_OPERAND_RM 
XSTORMY16_OPERAND_RS 
XSTORMY16_OPERAND_RB 
XSTORMY16_OPERAND_RBJ 
XSTORMY16_OPERAND_BCOND2 
XSTORMY16_OPERAND_WS2 
XSTORMY16_OPERAND_BCOND5 
XSTORMY16_OPERAND_IMM2 
XSTORMY16_OPERAND_IMM3 
XSTORMY16_OPERAND_IMM3B 
XSTORMY16_OPERAND_IMM4 
XSTORMY16_OPERAND_IMM8 
XSTORMY16_OPERAND_IMM8SMALL 
XSTORMY16_OPERAND_IMM12 
XSTORMY16_OPERAND_IMM16 
XSTORMY16_OPERAND_LMEM8 
XSTORMY16_OPERAND_HMEM8 
XSTORMY16_OPERAND_REL8_2 
XSTORMY16_OPERAND_REL8_4 
XSTORMY16_OPERAND_REL12 
XSTORMY16_OPERAND_REL12A 
XSTORMY16_OPERAND_ABS24 
XSTORMY16_OPERAND_PSW 
XSTORMY16_OPERAND_RPSW 
XSTORMY16_OPERAND_SP 
XSTORMY16_OPERAND_R0 
XSTORMY16_OPERAND_R1 
XSTORMY16_OPERAND_R2 
XSTORMY16_OPERAND_R8 
XSTORMY16_OPERAND_MAX 

Definition at line 220 of file m32r-desc.h.

enum cr_names
Enumerator:
H_CR_CR0 
H_CR_CR1 
H_CR_CR2 
H_CR_CR3 
H_CR_CR4 
H_CR_CR5 
H_CR_CR6 
H_CR_CR7 
H_CR_CR8 
H_CR_CR9 
H_CR_CR10 
H_CR_CR11 
H_CR_CR12 
H_CR_CR13 
H_CR_CR14 
H_CR_CR15 
H_CR_PSW 
H_CR_CBR 
H_CR_SPI 
H_CR_SPU 
H_CR_BPC 
H_CR_BBPSW 
H_CR_BBPC 
H_CR_EVB 
H_CR_CR0 
H_CR_CR1 
H_CR_CR2 
H_CR_CR3 
H_CR_CR4 
H_CR_CR5 
H_CR_CR6 
H_CR_CR7 
H_CR_CR8 
H_CR_CR9 
H_CR_CR10 
H_CR_CR11 
H_CR_CR12 
H_CR_CR13 
H_CR_CR14 
H_CR_CR15 

Definition at line 94 of file m32r-desc.h.

                      {
  H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
 , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
 , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
 , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
 , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
 , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
} CR_NAMES;
enum gr_names
Enumerator:
H_GR_R0 
H_GR_R1 
H_GR_R2 
H_GR_R3 
H_GR_R4 
H_GR_R5 
H_GR_R6 
H_GR_R7 
H_GR_R8 
H_GR_R9 
H_GR_R10 
H_GR_R11 
H_GR_R12 
H_GR_R13 
H_GR_R14 
H_GR_R15 
H_GR_AC 
H_GR_FP 
H_GR_SP 
H_GR_SP 
H_GR_FP 
H_GR_GR0 
H_GR_GR1 
H_GR_GR2 
H_GR_GR3 
H_GR_GR4 
H_GR_GR5 
H_GR_GR6 
H_GR_GR7 
H_GR_GR8 
H_GR_GR9 
H_GR_GR10 
H_GR_GR11 
H_GR_GR12 
H_GR_GR13 
H_GR_GR14 
H_GR_GR15 
H_GR_GR16 
H_GR_GR17 
H_GR_GR18 
H_GR_GR19 
H_GR_GR20 
H_GR_GR21 
H_GR_GR22 
H_GR_GR23 
H_GR_GR24 
H_GR_GR25 
H_GR_GR26 
H_GR_GR27 
H_GR_GR28 
H_GR_GR29 
H_GR_GR30 
H_GR_GR31 
H_GR_GR32 
H_GR_GR33 
H_GR_GR34 
H_GR_GR35 
H_GR_GR36 
H_GR_GR37 
H_GR_GR38 
H_GR_GR39 
H_GR_GR40 
H_GR_GR41 
H_GR_GR42 
H_GR_GR43 
H_GR_GR44 
H_GR_GR45 
H_GR_GR46 
H_GR_GR47 
H_GR_GR48 
H_GR_GR49 
H_GR_GR50 
H_GR_GR51 
H_GR_GR52 
H_GR_GR53 
H_GR_GR54 
H_GR_GR55 
H_GR_GR56 
H_GR_GR57 
H_GR_GR58 
H_GR_GR59 
H_GR_GR60 
H_GR_GR61 
H_GR_GR62 
H_GR_GR63 
H_GR_R0 
H_GR__0 
H_GR_R1 
H_GR__1 
H_GR_R2 
H_GR__2 
H_GR_R3 
H_GR__3 
H_GR_R4 
H_GR__4 
H_GR_R5 
H_GR__5 
H_GR_R6 
H_GR__6 
H_GR_R7 
H_GR__7 
H_GR_R8 
H_GR__8 
H_GR_R9 
H_GR__9 
H_GR_R10 
H_GR__10 
H_GR_R11 
H_GR__11 
H_GR_R12 
H_GR__12 
H_GR_R13 
H_GR__13 
H_GR_R14 
H_GR__14 
H_GR_R15 
H_GR__15 
H_GR_R16 
H_GR__16 
H_GR_R17 
H_GR__17 
H_GR_R18 
H_GR__18 
H_GR_R19 
H_GR__19 
H_GR_R20 
H_GR__20 
H_GR_R21 
H_GR__21 
H_GR_R22 
H_GR__22 
H_GR_R23 
H_GR__23 
H_GR_R24 
H_GR__24 
H_GR_R25 
H_GR__25 
H_GR_R26 
H_GR__26 
H_GR_R27 
H_GR__27 
H_GR_R28 
H_GR__28 
H_GR_R29 
H_GR__29 
H_GR_R30 
H_GR__30 
H_GR_R31 
H_GR__31 
H_GR_FP 
H_GR_LR 
H_GR_SP 
H_GR_R0 
H_GR_R1 
H_GR_R2 
H_GR_R3 
H_GR_R4 
H_GR_R5 
H_GR_R6 
H_GR_R7 
H_GR_R8 
H_GR_R9 
H_GR_R10 
H_GR_R11 
H_GR_R12 
H_GR_R13 
H_GR_R14 
H_GR_R15 
H_GR_R0 
H_GR_R1 
H_GR_R2 
H_GR_R3 
H_GR_R4 
H_GR_R5 
H_GR_R6 
H_GR_R7 
H_GR_R8 
H_GR_R9 
H_GR_R10 
H_GR_R11 
H_GR_R12 
H_GR_R13 
H_GR_R14 
H_GR_R15 
H_GR_R0 
H_GR_R1 
H_GR_R2 
H_GR_R3 
H_GR_R4 
H_GR_R5 
H_GR_R6 
H_GR_R7 
H_GR_R8 
H_GR_R9 
H_GR_R10 
H_GR_R11 
H_GR_R12 
H_GR_R13 
H_GR_R14 
H_GR_R15 
H_GR_PSW 
H_GR_SP 

Definition at line 85 of file m32r-desc.h.

                      {
  H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
} GR_NAMES;
Enumerator:
FR30_F_NIL 
FR30_F_ANYOF 
FR30_F_OP1 
FR30_F_OP2 
FR30_F_OP3 
FR30_F_OP4 
FR30_F_OP5 
FR30_F_CC 
FR30_F_CCC 
FR30_F_RJ 
FR30_F_RI 
FR30_F_RS1 
FR30_F_RS2 
FR30_F_RJC 
FR30_F_RIC 
FR30_F_CRJ 
FR30_F_CRI 
FR30_F_U4 
FR30_F_U4C 
FR30_F_I4 
FR30_F_M4 
FR30_F_U8 
FR30_F_I8 
FR30_F_I20_4 
FR30_F_I20_16 
FR30_F_I20 
FR30_F_I32 
FR30_F_UDISP6 
FR30_F_DISP8 
FR30_F_DISP9 
FR30_F_DISP10 
FR30_F_S10 
FR30_F_U10 
FR30_F_REL9 
FR30_F_DIR8 
FR30_F_DIR9 
FR30_F_DIR10 
FR30_F_REL12 
FR30_F_REGLIST_HI_ST 
FR30_F_REGLIST_LOW_ST 
FR30_F_REGLIST_HI_LD 
FR30_F_REGLIST_LOW_LD 
FR30_F_MAX 
FRV_F_NIL 
FRV_F_ANYOF 
FRV_F_PACK 
FRV_F_OP 
FRV_F_OPE1 
FRV_F_OPE2 
FRV_F_OPE3 
FRV_F_OPE4 
FRV_F_GRI 
FRV_F_GRJ 
FRV_F_GRK 
FRV_F_FRI 
FRV_F_FRJ 
FRV_F_FRK 
FRV_F_CPRI 
FRV_F_CPRJ 
FRV_F_CPRK 
FRV_F_ACCGI 
FRV_F_ACCGK 
FRV_F_ACC40SI 
FRV_F_ACC40UI 
FRV_F_ACC40SK 
FRV_F_ACC40UK 
FRV_F_CRI 
FRV_F_CRJ 
FRV_F_CRK 
FRV_F_CCI 
FRV_F_CRJ_INT 
FRV_F_CRJ_FLOAT 
FRV_F_ICCI_1 
FRV_F_ICCI_2 
FRV_F_ICCI_3 
FRV_F_FCCI_1 
FRV_F_FCCI_2 
FRV_F_FCCI_3 
FRV_F_FCCK 
FRV_F_EIR 
FRV_F_S10 
FRV_F_S12 
FRV_F_D12 
FRV_F_U16 
FRV_F_S16 
FRV_F_S6 
FRV_F_S6_1 
FRV_F_U6 
FRV_F_S5 
FRV_F_U12_H 
FRV_F_U12_L 
FRV_F_U12 
FRV_F_INT_CC 
FRV_F_FLT_CC 
FRV_F_COND 
FRV_F_CCOND 
FRV_F_HINT 
FRV_F_LI 
FRV_F_LOCK 
FRV_F_DEBUG 
FRV_F_A 
FRV_F_AE 
FRV_F_SPR_H 
FRV_F_SPR_L 
FRV_F_SPR