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cell-binutils  2.17cvs20070401
m32r-desc.c
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00001 /* CPU data for m32r.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "m32r-desc.h"
00032 #include "m32r-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "m32r", MACH_M32R },
00050   { "m32rx", MACH_M32RX },
00051   { "m32r2", MACH_M32R2 },
00052   { "max", MACH_MAX },
00053   { 0, 0 }
00054 };
00055 
00056 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00057 {
00058   { "m32r", ISA_M32R },
00059   { "max", ISA_MAX },
00060   { 0, 0 }
00061 };
00062 
00063 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
00064 {
00065   { "NONE", PIPE_NONE },
00066   { "O", PIPE_O },
00067   { "S", PIPE_S },
00068   { "OS", PIPE_OS },
00069   { "O_OS", PIPE_O_OS },
00070   { 0, 0 }
00071 };
00072 
00073 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
00074 {
00075   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00076   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00077   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00078   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00079   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00080   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00081   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00082   { "RELOC", &bool_attr[0], &bool_attr[0] },
00083   { 0, 0, 0 }
00084 };
00085 
00086 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
00087 {
00088   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00089   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00090   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00091   { "PC", &bool_attr[0], &bool_attr[0] },
00092   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00093   { 0, 0, 0 }
00094 };
00095 
00096 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
00097 {
00098   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00099   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00100   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00101   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00102   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00103   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00104   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00105   { "RELAX", &bool_attr[0], &bool_attr[0] },
00106   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00107   { "RELOC", &bool_attr[0], &bool_attr[0] },
00108   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
00109   { 0, 0, 0 }
00110 };
00111 
00112 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
00113 {
00114   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00115   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
00116   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00117   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00118   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00119   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00120   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00121   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00122   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00123   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00124   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00125   { "PBB", &bool_attr[0], &bool_attr[0] },
00126   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
00127   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
00128   { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
00129   { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
00130   { 0, 0, 0 }
00131 };
00132 
00133 /* Instruction set variants.  */
00134 
00135 static const CGEN_ISA m32r_cgen_isa_table[] = {
00136   { "m32r", 32, 32, 16, 32 },
00137   { 0, 0, 0, 0, 0 }
00138 };
00139 
00140 /* Machine variants.  */
00141 
00142 static const CGEN_MACH m32r_cgen_mach_table[] = {
00143   { "m32r", "m32r", MACH_M32R, 0 },
00144   { "m32rx", "m32rx", MACH_M32RX, 0 },
00145   { "m32r2", "m32r2", MACH_M32R2, 0 },
00146   { 0, 0, 0, 0 }
00147 };
00148 
00149 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
00150 {
00151   { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
00152   { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
00153   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
00154   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00155   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
00156   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
00157   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
00158   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
00159   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
00160   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
00161   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
00162   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
00163   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
00164   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
00165   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
00166   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
00167   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
00168   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
00169   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
00170 };
00171 
00172 CGEN_KEYWORD m32r_cgen_opval_gr_names =
00173 {
00174   & m32r_cgen_opval_gr_names_entries[0],
00175   19,
00176   0, 0, 0, 0, ""
00177 };
00178 
00179 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
00180 {
00181   { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
00182   { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
00183   { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
00184   { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
00185   { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
00186   { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
00187   { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
00188   { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
00189   { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
00190   { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
00191   { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
00192   { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
00193   { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
00194   { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
00195   { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
00196   { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
00197   { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
00198   { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
00199   { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
00200   { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
00201   { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
00202   { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
00203   { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
00204   { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
00205 };
00206 
00207 CGEN_KEYWORD m32r_cgen_opval_cr_names =
00208 {
00209   & m32r_cgen_opval_cr_names_entries[0],
00210   24,
00211   0, 0, 0, 0, ""
00212 };
00213 
00214 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
00215 {
00216   { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
00217   { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
00218 };
00219 
00220 CGEN_KEYWORD m32r_cgen_opval_h_accums =
00221 {
00222   & m32r_cgen_opval_h_accums_entries[0],
00223   2,
00224   0, 0, 0, 0, ""
00225 };
00226 
00227 
00228 /* The hardware table.  */
00229 
00230 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00231 #define A(a) (1 << CGEN_HW_##a)
00232 #else
00233 #define A(a) (1 << CGEN_HW_a)
00234 #endif
00235 
00236 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
00237 {
00238   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00239   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00240   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00241   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00242   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00243   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00244   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00245   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00246   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00247   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00248   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00249   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00250   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
00251   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00252   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00253   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00254   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00255   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00256   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00257 };
00258 
00259 #undef A
00260 
00261 
00262 /* The instruction field table.  */
00263 
00264 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00265 #define A(a) (1 << CGEN_IFLD_##a)
00266 #else
00267 #define A(a) (1 << CGEN_IFLD_a)
00268 #endif
00269 
00270 const CGEN_IFLD m32r_cgen_ifld_table[] =
00271 {
00272   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00273   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00274   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00275   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00276   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00277   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00278   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00279   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00280   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00281   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00282   { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00283   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00284   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00285   { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00286   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00287   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00288   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00289   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00290   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00291   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00292   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00293   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00294   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00295   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00296   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00297   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00298   { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00299   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00300   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00301   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00302 };
00303 
00304 #undef A
00305 
00306 
00307 
00308 /* multi ifield declarations */
00309 
00310 
00311 
00312 /* multi ifield definitions */
00313 
00314 
00315 /* The operand table.  */
00316 
00317 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00318 #define A(a) (1 << CGEN_OPERAND_##a)
00319 #else
00320 #define A(a) (1 << CGEN_OPERAND_a)
00321 #endif
00322 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00323 #define OPERAND(op) M32R_OPERAND_##op
00324 #else
00325 #define OPERAND(op) M32R_OPERAND_op
00326 #endif
00327 
00328 const CGEN_OPERAND m32r_cgen_operand_table[] =
00329 {
00330 /* pc: program counter */
00331   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
00332     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } }, 
00333     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00334 /* sr: source register */
00335   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
00336     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
00337     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00338 /* dr: destination register */
00339   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
00340     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
00341     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00342 /* src1: source register 1 */
00343   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
00344     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
00345     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00346 /* src2: source register 2 */
00347   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
00348     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
00349     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00350 /* scr: source control register */
00351   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
00352     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
00353     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00354 /* dcr: destination control register */
00355   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
00356     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
00357     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00358 /* simm8: 8 bit signed immediate */
00359   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
00360     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } }, 
00361     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00362 /* simm16: 16 bit signed immediate */
00363   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
00364     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
00365     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00366 /* uimm3: 3 bit unsigned number */
00367   { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
00368     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, 
00369     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00370 /* uimm4: 4 bit trap number */
00371   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
00372     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, 
00373     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00374 /* uimm5: 5 bit shift count */
00375   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
00376     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, 
00377     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00378 /* uimm8: 8 bit unsigned immediate */
00379   { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
00380     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, 
00381     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00382 /* uimm16: 16 bit unsigned immediate */
00383   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
00384     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
00385     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00386 /* imm1: 1 bit immediate */
00387   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
00388     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, 
00389     { 0|A(HASH_PREFIX), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
00390 /* accd: accumulator destination register */
00391   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
00392     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, 
00393     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
00394 /* accs: accumulator source register */
00395   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
00396     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, 
00397     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
00398 /* acc: accumulator reg (d) */
00399   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
00400     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, 
00401     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
00402 /* hash: # prefix */
00403   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
00404     { 0, { (const PTR) 0 } }, 
00405     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00406 /* hi16: high 16 bit immediate, sign optional */
00407   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
00408     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } }, 
00409     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00410 /* slo16: 16 bit signed immediate, for low() */
00411   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
00412     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
00413     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00414 /* ulo16: 16 bit unsigned immediate, for low() */
00415   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
00416     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
00417     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00418 /* uimm24: 24 bit address */
00419   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
00420     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } }, 
00421     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00422 /* disp8: 8 bit displacement */
00423   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
00424     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } }, 
00425     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00426 /* disp16: 16 bit displacement */
00427   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
00428     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } }, 
00429     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00430 /* disp24: 24 bit displacement */
00431   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
00432     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } }, 
00433     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00434 /* condbit: condition bit */
00435   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
00436     { 0, { (const PTR) 0 } }, 
00437     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00438 /* accum: accumulator */
00439   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
00440     { 0, { (const PTR) 0 } }, 
00441     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00442 /* sentinel */
00443   { 0, 0, 0, 0, 0,
00444     { 0, { (const PTR) 0 } },
00445     { 0, { { { (1<<MACH_BASE), 0 } } } } }
00446 };
00447 
00448 #undef A
00449 
00450 
00451 /* The instruction table.  */
00452 
00453 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00454 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00455 #define A(a) (1 << CGEN_INSN_##a)
00456 #else
00457 #define A(a) (1 << CGEN_INSN_a)
00458 #endif
00459 
00460 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
00461 {
00462   /* Special null first entry.
00463      A `num' value of zero is thus invalid.
00464      Also, the special `invalid' insn resides here.  */
00465   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
00466 /* add $dr,$sr */
00467   {
00468     M32R_INSN_ADD, "add", "add", 16,
00469     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00470   },
00471 /* add3 $dr,$sr,$hash$slo16 */
00472   {
00473     M32R_INSN_ADD3, "add3", "add3", 32,
00474     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00475   },
00476 /* and $dr,$sr */
00477   {
00478     M32R_INSN_AND, "and", "and", 16,
00479     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00480   },
00481 /* and3 $dr,$sr,$uimm16 */
00482   {
00483     M32R_INSN_AND3, "and3", "and3", 32,
00484     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00485   },
00486 /* or $dr,$sr */
00487   {
00488     M32R_INSN_OR, "or", "or", 16,
00489     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00490   },
00491 /* or3 $dr,$sr,$hash$ulo16 */
00492   {
00493     M32R_INSN_OR3, "or3", "or3", 32,
00494     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00495   },
00496 /* xor $dr,$sr */
00497   {
00498     M32R_INSN_XOR, "xor", "xor", 16,
00499     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00500   },
00501 /* xor3 $dr,$sr,$uimm16 */
00502   {
00503     M32R_INSN_XOR3, "xor3", "xor3", 32,
00504     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00505   },
00506 /* addi $dr,$simm8 */
00507   {
00508     M32R_INSN_ADDI, "addi", "addi", 16,
00509     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00510   },
00511 /* addv $dr,$sr */
00512   {
00513     M32R_INSN_ADDV, "addv", "addv", 16,
00514     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00515   },
00516 /* addv3 $dr,$sr,$simm16 */
00517   {
00518     M32R_INSN_ADDV3, "addv3", "addv3", 32,
00519     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00520   },
00521 /* addx $dr,$sr */
00522   {
00523     M32R_INSN_ADDX, "addx", "addx", 16,
00524     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00525   },
00526 /* bc.s $disp8 */
00527   {
00528     M32R_INSN_BC8, "bc8", "bc.s", 16,
00529     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00530   },
00531 /* bc.l $disp24 */
00532   {
00533     M32R_INSN_BC24, "bc24", "bc.l", 32,
00534     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00535   },
00536 /* beq $src1,$src2,$disp16 */
00537   {
00538     M32R_INSN_BEQ, "beq", "beq", 32,
00539     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00540   },
00541 /* beqz $src2,$disp16 */
00542   {
00543     M32R_INSN_BEQZ, "beqz", "beqz", 32,
00544     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00545   },
00546 /* bgez $src2,$disp16 */
00547   {
00548     M32R_INSN_BGEZ, "bgez", "bgez", 32,
00549     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00550   },
00551 /* bgtz $src2,$disp16 */
00552   {
00553     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
00554     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00555   },
00556 /* blez $src2,$disp16 */
00557   {
00558     M32R_INSN_BLEZ, "blez", "blez", 32,
00559     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00560   },
00561 /* bltz $src2,$disp16 */
00562   {
00563     M32R_INSN_BLTZ, "bltz", "bltz", 32,
00564     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00565   },
00566 /* bnez $src2,$disp16 */
00567   {
00568     M32R_INSN_BNEZ, "bnez", "bnez", 32,
00569     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00570   },
00571 /* bl.s $disp8 */
00572   {
00573     M32R_INSN_BL8, "bl8", "bl.s", 16,
00574     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00575   },
00576 /* bl.l $disp24 */
00577   {
00578     M32R_INSN_BL24, "bl24", "bl.l", 32,
00579     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00580   },
00581 /* bcl.s $disp8 */
00582   {
00583     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
00584     { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
00585   },
00586 /* bcl.l $disp24 */
00587   {
00588     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
00589     { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00590   },
00591 /* bnc.s $disp8 */
00592   {
00593     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
00594     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00595   },
00596 /* bnc.l $disp24 */
00597   {
00598     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
00599     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00600   },
00601 /* bne $src1,$src2,$disp16 */
00602   {
00603     M32R_INSN_BNE, "bne", "bne", 32,
00604     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00605   },
00606 /* bra.s $disp8 */
00607   {
00608     M32R_INSN_BRA8, "bra8", "bra.s", 16,
00609     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00610   },
00611 /* bra.l $disp24 */
00612   {
00613     M32R_INSN_BRA24, "bra24", "bra.l", 32,
00614     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00615   },
00616 /* bncl.s $disp8 */
00617   {
00618     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
00619     { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
00620   },
00621 /* bncl.l $disp24 */
00622   {
00623     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
00624     { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00625   },
00626 /* cmp $src1,$src2 */
00627   {
00628     M32R_INSN_CMP, "cmp", "cmp", 16,
00629     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00630   },
00631 /* cmpi $src2,$simm16 */
00632   {
00633     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
00634     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00635   },
00636 /* cmpu $src1,$src2 */
00637   {
00638     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
00639     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00640   },
00641 /* cmpui $src2,$simm16 */
00642   {
00643     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
00644     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00645   },
00646 /* cmpeq $src1,$src2 */
00647   {
00648     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
00649     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
00650   },
00651 /* cmpz $src2 */
00652   {
00653     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
00654     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
00655   },
00656 /* div $dr,$sr */
00657   {
00658     M32R_INSN_DIV, "div", "div", 32,
00659     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00660   },
00661 /* divu $dr,$sr */
00662   {
00663     M32R_INSN_DIVU, "divu", "divu", 32,
00664     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00665   },
00666 /* rem $dr,$sr */
00667   {
00668     M32R_INSN_REM, "rem", "rem", 32,
00669     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00670   },
00671 /* remu $dr,$sr */
00672   {
00673     M32R_INSN_REMU, "remu", "remu", 32,
00674     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00675   },
00676 /* remh $dr,$sr */
00677   {
00678     M32R_INSN_REMH, "remh", "remh", 32,
00679     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00680   },
00681 /* remuh $dr,$sr */
00682   {
00683     M32R_INSN_REMUH, "remuh", "remuh", 32,
00684     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00685   },
00686 /* remb $dr,$sr */
00687   {
00688     M32R_INSN_REMB, "remb", "remb", 32,
00689     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00690   },
00691 /* remub $dr,$sr */
00692   {
00693     M32R_INSN_REMUB, "remub", "remub", 32,
00694     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00695   },
00696 /* divuh $dr,$sr */
00697   {
00698     M32R_INSN_DIVUH, "divuh", "divuh", 32,
00699     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00700   },
00701 /* divb $dr,$sr */
00702   {
00703     M32R_INSN_DIVB, "divb", "divb", 32,
00704     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00705   },
00706 /* divub $dr,$sr */
00707   {
00708     M32R_INSN_DIVUB, "divub", "divub", 32,
00709     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00710   },
00711 /* divh $dr,$sr */
00712   {
00713     M32R_INSN_DIVH, "divh", "divh", 32,
00714     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
00715   },
00716 /* jc $sr */
00717   {
00718     M32R_INSN_JC, "jc", "jc", 16,
00719     { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
00720   },
00721 /* jnc $sr */
00722   {
00723     M32R_INSN_JNC, "jnc", "jnc", 16,
00724     { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
00725   },
00726 /* jl $sr */
00727   {
00728     M32R_INSN_JL, "jl", "jl", 16,
00729     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00730   },
00731 /* jmp $sr */
00732   {
00733     M32R_INSN_JMP, "jmp", "jmp", 16,
00734     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00735   },
00736 /* ld $dr,@$sr */
00737   {
00738     M32R_INSN_LD, "ld", "ld", 16,
00739     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00740   },
00741 /* ld $dr,@($slo16,$sr) */
00742   {
00743     M32R_INSN_LD_D, "ld-d", "ld", 32,
00744     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00745   },
00746 /* ldb $dr,@$sr */
00747   {
00748     M32R_INSN_LDB, "ldb", "ldb", 16,
00749     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00750   },
00751 /* ldb $dr,@($slo16,$sr) */
00752   {
00753     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
00754     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00755   },
00756 /* ldh $dr,@$sr */
00757   {
00758     M32R_INSN_LDH, "ldh", "ldh", 16,
00759     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00760   },
00761 /* ldh $dr,@($slo16,$sr) */
00762   {
00763     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
00764     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00765   },
00766 /* ldub $dr,@$sr */
00767   {
00768     M32R_INSN_LDUB, "ldub", "ldub", 16,
00769     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00770   },
00771 /* ldub $dr,@($slo16,$sr) */
00772   {
00773     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
00774     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00775   },
00776 /* lduh $dr,@$sr */
00777   {
00778     M32R_INSN_LDUH, "lduh", "lduh", 16,
00779     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00780   },
00781 /* lduh $dr,@($slo16,$sr) */
00782   {
00783     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
00784     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00785   },
00786 /* ld $dr,@$sr+ */
00787   {
00788     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
00789     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00790   },
00791 /* ld24 $dr,$uimm24 */
00792   {
00793     M32R_INSN_LD24, "ld24", "ld24", 32,
00794     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00795   },
00796 /* ldi8 $dr,$simm8 */
00797   {
00798     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
00799     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00800   },
00801 /* ldi16 $dr,$hash$slo16 */
00802   {
00803     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
00804     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
00805   },
00806 /* lock $dr,@$sr */
00807   {
00808     M32R_INSN_LOCK, "lock", "lock", 16,
00809     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00810   },
00811 /* machi $src1,$src2 */
00812   {
00813     M32R_INSN_MACHI, "machi", "machi", 16,
00814     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00815   },
00816 /* machi $src1,$src2,$acc */
00817   {
00818     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
00819     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00820   },
00821 /* maclo $src1,$src2 */
00822   {
00823     M32R_INSN_MACLO, "maclo", "maclo", 16,
00824     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00825   },
00826 /* maclo $src1,$src2,$acc */
00827   {
00828     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
00829     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00830   },
00831 /* macwhi $src1,$src2 */
00832   {
00833     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
00834     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00835   },
00836 /* macwhi $src1,$src2,$acc */
00837   {
00838     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
00839     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00840   },
00841 /* macwlo $src1,$src2 */
00842   {
00843     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
00844     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00845   },
00846 /* macwlo $src1,$src2,$acc */
00847   {
00848     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
00849     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00850   },
00851 /* mul $dr,$sr */
00852   {
00853     M32R_INSN_MUL, "mul", "mul", 16,
00854     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
00855   },
00856 /* mulhi $src1,$src2 */
00857   {
00858     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
00859     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00860   },
00861 /* mulhi $src1,$src2,$acc */
00862   {
00863     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
00864     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00865   },
00866 /* mullo $src1,$src2 */
00867   {
00868     M32R_INSN_MULLO, "mullo", "mullo", 16,
00869     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00870   },
00871 /* mullo $src1,$src2,$acc */
00872   {
00873     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
00874     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00875   },
00876 /* mulwhi $src1,$src2 */
00877   {
00878     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
00879     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00880   },
00881 /* mulwhi $src1,$src2,$acc */
00882   {
00883     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
00884     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00885   },
00886 /* mulwlo $src1,$src2 */
00887   {
00888     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
00889     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00890   },
00891 /* mulwlo $src1,$src2,$acc */
00892   {
00893     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
00894     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00895   },
00896 /* mv $dr,$sr */
00897   {
00898     M32R_INSN_MV, "mv", "mv", 16,
00899     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00900   },
00901 /* mvfachi $dr */
00902   {
00903     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
00904     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00905   },
00906 /* mvfachi $dr,$accs */
00907   {
00908     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
00909     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00910   },
00911 /* mvfaclo $dr */
00912   {
00913     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
00914     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00915   },
00916 /* mvfaclo $dr,$accs */
00917   {
00918     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
00919     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00920   },
00921 /* mvfacmi $dr */
00922   {
00923     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
00924     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00925   },
00926 /* mvfacmi $dr,$accs */
00927   {
00928     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
00929     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00930   },
00931 /* mvfc $dr,$scr */
00932   {
00933     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
00934     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00935   },
00936 /* mvtachi $src1 */
00937   {
00938     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
00939     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00940   },
00941 /* mvtachi $src1,$accs */
00942   {
00943     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
00944     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00945   },
00946 /* mvtaclo $src1 */
00947   {
00948     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
00949     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00950   },
00951 /* mvtaclo $src1,$accs */
00952   {
00953     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
00954     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00955   },
00956 /* mvtc $sr,$dcr */
00957   {
00958     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
00959     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
00960   },
00961 /* neg $dr,$sr */
00962   {
00963     M32R_INSN_NEG, "neg", "neg", 16,
00964     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00965   },
00966 /* nop */
00967   {
00968     M32R_INSN_NOP, "nop", "nop", 16,
00969     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00970   },
00971 /* not $dr,$sr */
00972   {
00973     M32R_INSN_NOT, "not", "not", 16,
00974     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
00975   },
00976 /* rac */
00977   {
00978     M32R_INSN_RAC, "rac", "rac", 16,
00979     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00980   },
00981 /* rac $accd,$accs,$imm1 */
00982   {
00983     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
00984     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00985   },
00986 /* rach */
00987   {
00988     M32R_INSN_RACH, "rach", "rach", 16,
00989     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
00990   },
00991 /* rach $accd,$accs,$imm1 */
00992   {
00993     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
00994     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
00995   },
00996 /* rte */
00997   {
00998     M32R_INSN_RTE, "rte", "rte", 16,
00999     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01000   },
01001 /* seth $dr,$hash$hi16 */
01002   {
01003     M32R_INSN_SETH, "seth", "seth", 32,
01004     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01005   },
01006 /* sll $dr,$sr */
01007   {
01008     M32R_INSN_SLL, "sll", "sll", 16,
01009     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
01010   },
01011 /* sll3 $dr,$sr,$simm16 */
01012   {
01013     M32R_INSN_SLL3, "sll3", "sll3", 32,
01014     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01015   },
01016 /* slli $dr,$uimm5 */
01017   {
01018     M32R_INSN_SLLI, "slli", "slli", 16,
01019     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
01020   },
01021 /* sra $dr,$sr */
01022   {
01023     M32R_INSN_SRA, "sra", "sra", 16,
01024     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
01025   },
01026 /* sra3 $dr,$sr,$simm16 */
01027   {
01028     M32R_INSN_SRA3, "sra3", "sra3", 32,
01029     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01030   },
01031 /* srai $dr,$uimm5 */
01032   {
01033     M32R_INSN_SRAI, "srai", "srai", 16,
01034     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
01035   },
01036 /* srl $dr,$sr */
01037   {
01038     M32R_INSN_SRL, "srl", "srl", 16,
01039     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
01040   },
01041 /* srl3 $dr,$sr,$simm16 */
01042   {
01043     M32R_INSN_SRL3, "srl3", "srl3", 32,
01044     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01045   },
01046 /* srli $dr,$uimm5 */
01047   {
01048     M32R_INSN_SRLI, "srli", "srli", 16,
01049     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
01050   },
01051 /* st $src1,@$src2 */
01052   {
01053     M32R_INSN_ST, "st", "st", 16,
01054     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01055   },
01056 /* st $src1,@($slo16,$src2) */
01057   {
01058     M32R_INSN_ST_D, "st-d", "st", 32,
01059     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01060   },
01061 /* stb $src1,@$src2 */
01062   {
01063     M32R_INSN_STB, "stb", "stb", 16,
01064     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01065   },
01066 /* stb $src1,@($slo16,$src2) */
01067   {
01068     M32R_INSN_STB_D, "stb-d", "stb", 32,
01069     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01070   },
01071 /* sth $src1,@$src2 */
01072   {
01073     M32R_INSN_STH, "sth", "sth", 16,
01074     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01075   },
01076 /* sth $src1,@($slo16,$src2) */
01077   {
01078     M32R_INSN_STH_D, "sth-d", "sth", 32,
01079     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01080   },
01081 /* st $src1,@+$src2 */
01082   {
01083     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
01084     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01085   },
01086 /* sth $src1,@$src2+ */
01087   {
01088     M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
01089     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
01090   },
01091 /* stb $src1,@$src2+ */
01092   {
01093     M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
01094     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
01095   },
01096 /* st $src1,@-$src2 */
01097   {
01098     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
01099     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01100   },
01101 /* sub $dr,$sr */
01102   {
01103     M32R_INSN_SUB, "sub", "sub", 16,
01104     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01105   },
01106 /* subv $dr,$sr */
01107   {
01108     M32R_INSN_SUBV, "subv", "subv", 16,
01109     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01110   },
01111 /* subx $dr,$sr */
01112   {
01113     M32R_INSN_SUBX, "subx", "subx", 16,
01114     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01115   },
01116 /* trap $uimm4 */
01117   {
01118     M32R_INSN_TRAP, "trap", "trap", 16,
01119     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01120   },
01121 /* unlock $src1,@$src2 */
01122   {
01123     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
01124     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01125   },
01126 /* satb $dr,$sr */
01127   {
01128     M32R_INSN_SATB, "satb", "satb", 32,
01129     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
01130   },
01131 /* sath $dr,$sr */
01132   {
01133     M32R_INSN_SATH, "sath", "sath", 32,
01134     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
01135   },
01136 /* sat $dr,$sr */
01137   {
01138     M32R_INSN_SAT, "sat", "sat", 32,
01139     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
01140   },
01141 /* pcmpbz $src2 */
01142   {
01143     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
01144     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
01145   },
01146 /* sadd */
01147   {
01148     M32R_INSN_SADD, "sadd", "sadd", 16,
01149     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01150   },
01151 /* macwu1 $src1,$src2 */
01152   {
01153     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
01154     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01155   },
01156 /* msblo $src1,$src2 */
01157   {
01158     M32R_INSN_MSBLO, "msblo", "msblo", 16,
01159     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01160   },
01161 /* mulwu1 $src1,$src2 */
01162   {
01163     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
01164     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01165   },
01166 /* maclh1 $src1,$src2 */
01167   {
01168     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
01169     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
01170   },
01171 /* sc */
01172   {
01173     M32R_INSN_SC, "sc", "sc", 16,
01174     { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
01175   },
01176 /* snc */
01177   {
01178     M32R_INSN_SNC, "snc", "snc", 16,
01179     { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
01180   },
01181 /* clrpsw $uimm8 */
01182   {
01183     M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
01184     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01185   },
01186 /* setpsw $uimm8 */
01187   {
01188     M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
01189     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01190   },
01191 /* bset $uimm3,@($slo16,$sr) */
01192   {
01193     M32R_INSN_BSET, "bset", "bset", 32,
01194     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01195   },
01196 /* bclr $uimm3,@($slo16,$sr) */
01197   {
01198     M32R_INSN_BCLR, "bclr", "bclr", 32,
01199     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
01200   },
01201 /* btst $uimm3,$sr */
01202   {
01203     M32R_INSN_BTST, "btst", "btst", 16,
01204     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
01205   },
01206 };
01207 
01208 #undef OP
01209 #undef A
01210 
01211 /* Initialize anything needed to be done once, before any cpu_open call.  */
01212 
01213 static void
01214 init_tables (void)
01215 {
01216 }
01217 
01218 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
01219 static void build_hw_table      (CGEN_CPU_TABLE *);
01220 static void build_ifield_table  (CGEN_CPU_TABLE *);
01221 static void build_operand_table (CGEN_CPU_TABLE *);
01222 static void build_insn_table    (CGEN_CPU_TABLE *);
01223 static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
01224 
01225 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
01226 
01227 static const CGEN_MACH *
01228 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
01229 {
01230   while (table->name)
01231     {
01232       if (strcmp (name, table->bfd_name) == 0)
01233        return table;
01234       ++table;
01235     }
01236   abort ();
01237 }
01238 
01239 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
01240 
01241 static void
01242 build_hw_table (CGEN_CPU_TABLE *cd)
01243 {
01244   int i;
01245   int machs = cd->machs;
01246   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
01247   /* MAX_HW is only an upper bound on the number of selected entries.
01248      However each entry is indexed by it's enum so there can be holes in
01249      the table.  */
01250   const CGEN_HW_ENTRY **selected =
01251     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01252 
01253   cd->hw_table.init_entries = init;
01254   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01255   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01256   /* ??? For now we just use machs to determine which ones we want.  */
01257   for (i = 0; init[i].name != NULL; ++i)
01258     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01259        & machs)
01260       selected[init[i].type] = &init[i];
01261   cd->hw_table.entries = selected;
01262   cd->hw_table.num_entries = MAX_HW;
01263 }
01264 
01265 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
01266 
01267 static void
01268 build_ifield_table (CGEN_CPU_TABLE *cd)
01269 {
01270   cd->ifld_table = & m32r_cgen_ifld_table[0];
01271 }
01272 
01273 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
01274 
01275 static void
01276 build_operand_table (CGEN_CPU_TABLE *cd)
01277 {
01278   int i;
01279   int machs = cd->machs;
01280   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
01281   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01282      However each entry is indexed by it's enum so there can be holes in
01283      the table.  */
01284   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
01285 
01286   cd->operand_table.init_entries = init;
01287   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01288   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01289   /* ??? For now we just use mach to determine which ones we want.  */
01290   for (i = 0; init[i].name != NULL; ++i)
01291     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01292        & machs)
01293       selected[init[i].type] = &init[i];
01294   cd->operand_table.entries = selected;
01295   cd->operand_table.num_entries = MAX_OPERANDS;
01296 }
01297 
01298 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
01299    ??? This could leave out insns not supported by the specified mach/isa,
01300    but that would cause errors like "foo only supported by bar" to become
01301    "unknown insn", so for now we include all insns and require the app to
01302    do the checking later.
01303    ??? On the other hand, parsing of such insns may require their hardware or
01304    operand elements to be in the table [which they mightn't be].  */
01305 
01306 static void
01307 build_insn_table (CGEN_CPU_TABLE *cd)
01308 {
01309   int i;
01310   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
01311   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01312 
01313   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01314   for (i = 0; i < MAX_INSNS; ++i)
01315     insns[i].base = &ib[i];
01316   cd->insn_table.init_entries = insns;
01317   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01318   cd->insn_table.num_init_entries = MAX_INSNS;
01319 }
01320 
01321 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
01322 
01323 static void
01324 m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
01325 {
01326   int i;
01327   CGEN_BITSET *isas = cd->isas;
01328   unsigned int machs = cd->machs;
01329 
01330   cd->int_insn_p = CGEN_INT_INSN_P;
01331 
01332   /* Data derived from the isa spec.  */
01333 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01334   cd->default_insn_bitsize = UNSET;
01335   cd->base_insn_bitsize = UNSET;
01336   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
01337   cd->max_insn_bitsize = 0;
01338   for (i = 0; i < MAX_ISAS; ++i)
01339     if (cgen_bitset_contains (isas, i))
01340       {
01341        const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
01342 
01343        /* Default insn sizes of all selected isas must be
01344           equal or we set the result to 0, meaning "unknown".  */
01345        if (cd->default_insn_bitsize == UNSET)
01346          cd->default_insn_bitsize = isa->default_insn_bitsize;
01347        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
01348          ; /* This is ok.  */
01349        else
01350          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
01351 
01352        /* Base insn sizes of all selected isas must be equal
01353           or we set the result to 0, meaning "unknown".  */
01354        if (cd->base_insn_bitsize == UNSET)
01355          cd->base_insn_bitsize = isa->base_insn_bitsize;
01356        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
01357          ; /* This is ok.  */
01358        else
01359          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
01360 
01361        /* Set min,max insn sizes.  */
01362        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
01363          cd->min_insn_bitsize = isa->min_insn_bitsize;
01364        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
01365          cd->max_insn_bitsize = isa->max_insn_bitsize;
01366       }
01367 
01368   /* Data derived from the mach spec.  */
01369   for (i = 0; i < MAX_MACHS; ++i)
01370     if (((1 << i) & machs) != 0)
01371       {
01372        const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
01373 
01374        if (mach->insn_chunk_bitsize != 0)
01375        {
01376          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
01377            {
01378              fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
01379                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
01380              abort ();
01381            }
01382 
01383          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
01384        }
01385       }
01386 
01387   /* Determine which hw elements are used by MACH.  */
01388   build_hw_table (cd);
01389 
01390   /* Build the ifield table.  */
01391   build_ifield_table (cd);
01392 
01393   /* Determine which operands are used by MACH/ISA.  */
01394   build_operand_table (cd);
01395 
01396   /* Build the instruction table.  */
01397   build_insn_table (cd);
01398 }
01399 
01400 /* Initialize a cpu table and return a descriptor.
01401    It's much like opening a file, and must be the first function called.
01402    The arguments are a set of (type/value) pairs, terminated with
01403    CGEN_CPU_OPEN_END.
01404 
01405    Currently supported values:
01406    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
01407    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
01408    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
01409    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
01410    CGEN_CPU_OPEN_END:     terminates arguments
01411 
01412    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
01413    precluded.
01414 
01415    ??? We only support ISO C stdargs here, not K&R.
01416    Laziness, plus experiment to see if anything requires K&R - eventually
01417    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01418 
01419 CGEN_CPU_DESC
01420 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
01421 {
01422   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
01423   static int init_p;
01424   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
01425   unsigned int machs = 0; /* 0 = "unspecified" */
01426   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
01427   va_list ap;
01428 
01429   if (! init_p)
01430     {
01431       init_tables ();
01432       init_p = 1;
01433     }
01434 
01435   memset (cd, 0, sizeof (*cd));
01436 
01437   va_start (ap, arg_type);
01438   while (arg_type != CGEN_CPU_OPEN_END)
01439     {
01440       switch (arg_type)
01441        {
01442        case CGEN_CPU_OPEN_ISAS :
01443          isas = va_arg (ap, CGEN_BITSET *);
01444          break;
01445        case CGEN_CPU_OPEN_MACHS :
01446          machs = va_arg (ap, unsigned int);
01447          break;
01448        case CGEN_CPU_OPEN_BFDMACH :
01449          {
01450            const char *name = va_arg (ap, const char *);
01451            const CGEN_MACH *mach =
01452              lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
01453 
01454            machs |= 1 << mach->num;
01455            break;
01456          }
01457        case CGEN_CPU_OPEN_ENDIAN :
01458          endian = va_arg (ap, enum cgen_endian);
01459          break;
01460        default :
01461          fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
01462                  arg_type);
01463          abort (); /* ??? return NULL? */
01464        }
01465       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
01466     }
01467   va_end (ap);
01468 
01469   /* Mach unspecified means "all".  */
01470   if (machs == 0)
01471     machs = (1 << MAX_MACHS) - 1;
01472   /* Base mach is always selected.  */
01473   machs |= 1;
01474   if (endian == CGEN_ENDIAN_UNKNOWN)
01475     {
01476       /* ??? If target has only one, could have a default.  */
01477       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
01478       abort ();
01479     }
01480 
01481   cd->isas = cgen_bitset_copy (isas);
01482   cd->machs = machs;
01483   cd->endian = endian;
01484   /* FIXME: for the sparc case we can determine insn-endianness statically.
01485      The worry here is where both data and insn endian can be independently
01486      chosen, in which case this function will need another argument.
01487      Actually, will want to allow for more arguments in the future anyway.  */
01488   cd->insn_endian = endian;
01489 
01490   /* Table (re)builder.  */
01491   cd->rebuild_tables = m32r_cgen_rebuild_tables;
01492   m32r_cgen_rebuild_tables (cd);
01493 
01494   /* Default to not allowing signed overflow.  */
01495   cd->signed_overflow_ok_p = 0;
01496   
01497   return (CGEN_CPU_DESC) cd;
01498 }
01499 
01500 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01501    MACH_NAME is the bfd name of the mach.  */
01502 
01503 CGEN_CPU_DESC
01504 m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
01505 {
01506   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01507                             CGEN_CPU_OPEN_ENDIAN, endian,
01508                             CGEN_CPU_OPEN_END);
01509 }
01510 
01511 /* Close a cpu table.
01512    ??? This can live in a machine independent file, but there's currently
01513    no place to put this file (there's no libcgen).  libopcodes is the wrong
01514    place as some simulator ports use this but they don't use libopcodes.  */
01515 
01516 void
01517 m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
01518 {
01519   unsigned int i;
01520   const CGEN_INSN *insns;
01521 
01522   if (cd->macro_insn_table.init_entries)
01523     {
01524       insns = cd->macro_insn_table.init_entries;
01525       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01526        if (CGEN_INSN_RX ((insns)))
01527          regfree (CGEN_INSN_RX (insns));
01528     }
01529 
01530   if (cd->insn_table.init_entries)
01531     {
01532       insns = cd->insn_table.init_entries;
01533       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01534        if (CGEN_INSN_RX (insns))
01535          regfree (CGEN_INSN_RX (insns));
01536     }  
01537 
01538   if (cd->macro_insn_table.init_entries)
01539     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01540 
01541   if (cd->insn_table.init_entries)
01542     free ((CGEN_INSN *) cd->insn_table.init_entries);
01543 
01544   if (cd->hw_table.entries)
01545     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01546 
01547   if (cd->operand_table.entries)
01548     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01549 
01550   free (cd);
01551 }
01552