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cell-binutils  2.17cvs20070401
Defines | Functions | Variables
m32c-desc.c File Reference
#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "m32c-desc.h"
#include "m32c-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"

Go to the source code of this file.

Defines

#define A(a)   (1 << CGEN_HW_a)
#define A(a)   (1 << CGEN_IFLD_a)
#define A(a)   (1 << CGEN_OPERAND_a)
#define OPERAND(op)   M32C_OPERAND_op
#define OP(field)   CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#define A(a)   (1 << CGEN_INSN_a)
#define UNSET   (CGEN_SIZE_UNKNOWN + 1)

Functions

static void init_tables (void)
static const CGEN_MACHlookup_mach_via_bfd_name (const CGEN_MACH *, const char *)
static void build_hw_table (CGEN_CPU_TABLE *)
static void build_ifield_table (CGEN_CPU_TABLE *)
static void build_operand_table (CGEN_CPU_TABLE *)
static void build_insn_table (CGEN_CPU_TABLE *)
static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *)
CGEN_CPU_DESC m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type,...)
CGEN_CPU_DESC m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
void m32c_cgen_cpu_close (CGEN_CPU_DESC cd)

Variables

static const CGEN_ATTR_ENTRY bool_attr []
static const CGEN_ATTR_ENTRY
MACH_attr[] 
ATTRIBUTE_UNUSED
const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table []
const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table []
const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table []
const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table []
static const CGEN_ISA m32c_cgen_isa_table []
static const CGEN_MACH m32c_cgen_mach_table []
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries []
CGEN_KEYWORD m32c_cgen_opval_h_gr
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_gr_QI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_gr_HI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_gr_SI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r0l
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r0h
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r1l
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r1h
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r0
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r1
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r2
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r3
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r2r0
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r3r1
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries []
CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries []
CGEN_KEYWORD m32c_cgen_opval_h_ar
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_ar_QI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_ar_HI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries []
CGEN_KEYWORD m32c_cgen_opval_h_ar_SI
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries []
CGEN_KEYWORD m32c_cgen_opval_h_a0
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries []
CGEN_KEYWORD m32c_cgen_opval_h_a1
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cond16
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cond16c
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cond16j
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cond32
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cr1_32
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cr2_32
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cr3_32
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries []
CGEN_KEYWORD m32c_cgen_opval_h_cr_16
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries []
CGEN_KEYWORD m32c_cgen_opval_h_flags
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries []
CGEN_KEYWORD m32c_cgen_opval_h_shimm
const CGEN_HW_ENTRY m32c_cgen_hw_table []
const CGEN_IFLD m32c_cgen_ifld_table []
const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U20_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD []
const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD []
const CGEN_OPERAND m32c_cgen_operand_table []
static const CGEN_IBASE m32c_cgen_insn_table [MAX_INSNS]

Define Documentation

#define A (   a)    (1 << CGEN_HW_a)

Definition at line 2724 of file m32c-desc.c.

#define A (   a)    (1 << CGEN_IFLD_a)

Definition at line 2724 of file m32c-desc.c.

#define A (   a)    (1 << CGEN_OPERAND_a)

Definition at line 2724 of file m32c-desc.c.

#define A (   a)    (1 << CGEN_INSN_a)

Definition at line 2724 of file m32c-desc.c.

#define OP (   field)    CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))

Definition at line 2720 of file m32c-desc.c.

#define OPERAND (   op)    M32C_OPERAND_op

Definition at line 1175 of file m32c-desc.c.

#define UNSET   (CGEN_SIZE_UNKNOWN + 1)

Function Documentation

static void build_hw_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 62909 of file m32c-desc.c.

{
  int i;
  int machs = cd->machs;
  const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
  /* MAX_HW is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_HW_ENTRY **selected =
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));

  cd->hw_table.init_entries = init;
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
  /* ??? For now we just use machs to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
       & machs)
      selected[init[i].type] = &init[i];
  cd->hw_table.entries = selected;
  cd->hw_table.num_entries = MAX_HW;
}

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static void build_ifield_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 62935 of file m32c-desc.c.

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static void build_insn_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 62974 of file m32c-desc.c.

{
  int i;
  const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));

  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
  for (i = 0; i < MAX_INSNS; ++i)
    insns[i].base = &ib[i];
  cd->insn_table.init_entries = insns;
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
  cd->insn_table.num_init_entries = MAX_INSNS;
}

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static void build_operand_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 62943 of file m32c-desc.c.

{
  int i;
  int machs = cd->machs;
  const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));

  cd->operand_table.init_entries = init;
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
  /* ??? For now we just use mach to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
       & machs)
      selected[init[i].type] = &init[i];
  cd->operand_table.entries = selected;
  cd->operand_table.num_entries = MAX_OPERANDS;
}

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static void init_tables ( void  ) [static]

Definition at line 62881 of file m32c-desc.c.

{
}

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static const CGEN_MACH * lookup_mach_via_bfd_name ( const CGEN_MACH table,
const char *  name 
) [static]

Definition at line 62895 of file m32c-desc.c.

{
  while (table->name)
    {
      if (strcmp (name, table->bfd_name) == 0)
       return table;
      ++table;
    }
  abort ();
}

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Definition at line 63184 of file m32c-desc.c.

{
  unsigned int i;
  const CGEN_INSN *insns;

  if (cd->macro_insn_table.init_entries)
    {
      insns = cd->macro_insn_table.init_entries;
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
       if (CGEN_INSN_RX ((insns)))
         regfree (CGEN_INSN_RX (insns));
    }

  if (cd->insn_table.init_entries)
    {
      insns = cd->insn_table.init_entries;
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
       if (CGEN_INSN_RX (insns))
         regfree (CGEN_INSN_RX (insns));
    }  

  if (cd->macro_insn_table.init_entries)
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

  if (cd->insn_table.init_entries)
    free ((CGEN_INSN *) cd->insn_table.init_entries);

  if (cd->hw_table.entries)
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);

  if (cd->operand_table.entries)
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);

  free (cd);
}

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CGEN_CPU_DESC m32c_cgen_cpu_open ( enum cgen_cpu_open_arg  arg_type,
  ... 
)

Definition at line 63087 of file m32c-desc.c.

{
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
  static int init_p;
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
  unsigned int machs = 0; /* 0 = "unspecified" */
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
  va_list ap;

  if (! init_p)
    {
      init_tables ();
      init_p = 1;
    }

  memset (cd, 0, sizeof (*cd));

  va_start (ap, arg_type);
  while (arg_type != CGEN_CPU_OPEN_END)
    {
      switch (arg_type)
       {
       case CGEN_CPU_OPEN_ISAS :
         isas = va_arg (ap, CGEN_BITSET *);
         break;
       case CGEN_CPU_OPEN_MACHS :
         machs = va_arg (ap, unsigned int);
         break;
       case CGEN_CPU_OPEN_BFDMACH :
         {
           const char *name = va_arg (ap, const char *);
           const CGEN_MACH *mach =
             lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);

           machs |= 1 << mach->num;
           break;
         }
       case CGEN_CPU_OPEN_ENDIAN :
         endian = va_arg (ap, enum cgen_endian);
         break;
       default :
         fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
                 arg_type);
         abort (); /* ??? return NULL? */
       }
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
    }
  va_end (ap);

  /* Mach unspecified means "all".  */
  if (machs == 0)
    machs = (1 << MAX_MACHS) - 1;
  /* Base mach is always selected.  */
  machs |= 1;
  if (endian == CGEN_ENDIAN_UNKNOWN)
    {
      /* ??? If target has only one, could have a default.  */
      fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
      abort ();
    }

  cd->isas = cgen_bitset_copy (isas);
  cd->machs = machs;
  cd->endian = endian;
  /* FIXME: for the sparc case we can determine insn-endianness statically.
     The worry here is where both data and insn endian can be independently
     chosen, in which case this function will need another argument.
     Actually, will want to allow for more arguments in the future anyway.  */
  cd->insn_endian = endian;

  /* Table (re)builder.  */
  cd->rebuild_tables = m32c_cgen_rebuild_tables;
  m32c_cgen_rebuild_tables (cd);

  /* Default to not allowing signed overflow.  */
  cd->signed_overflow_ok_p = 0;
  
  return (CGEN_CPU_DESC) cd;
}

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CGEN_CPU_DESC m32c_cgen_cpu_open_1 ( const char *  mach_name,
enum cgen_endian  endian 
)

Definition at line 63171 of file m32c-desc.c.

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static void m32c_cgen_rebuild_tables ( CGEN_CPU_TABLE cd) [static]

Definition at line 62991 of file m32c-desc.c.

{
  int i;
  CGEN_BITSET *isas = cd->isas;
  unsigned int machs = cd->machs;

  cd->int_insn_p = CGEN_INT_INSN_P;

  /* Data derived from the isa spec.  */
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
  cd->default_insn_bitsize = UNSET;
  cd->base_insn_bitsize = UNSET;
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
  cd->max_insn_bitsize = 0;
  for (i = 0; i < MAX_ISAS; ++i)
    if (cgen_bitset_contains (isas, i))
      {
       const CGEN_ISA *isa = & m32c_cgen_isa_table[i];

       /* Default insn sizes of all selected isas must be
          equal or we set the result to 0, meaning "unknown".  */
       if (cd->default_insn_bitsize == UNSET)
         cd->default_insn_bitsize = isa->default_insn_bitsize;
       else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
         ; /* This is ok.  */
       else
         cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;

       /* Base insn sizes of all selected isas must be equal
          or we set the result to 0, meaning "unknown".  */
       if (cd->base_insn_bitsize == UNSET)
         cd->base_insn_bitsize = isa->base_insn_bitsize;
       else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
         ; /* This is ok.  */
       else
         cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;

       /* Set min,max insn sizes.  */
       if (isa->min_insn_bitsize < cd->min_insn_bitsize)
         cd->min_insn_bitsize = isa->min_insn_bitsize;
       if (isa->max_insn_bitsize > cd->max_insn_bitsize)
         cd->max_insn_bitsize = isa->max_insn_bitsize;
      }

  /* Data derived from the mach spec.  */
  for (i = 0; i < MAX_MACHS; ++i)
    if (((1 << i) & machs) != 0)
      {
       const CGEN_MACH *mach = & m32c_cgen_mach_table[i];

       if (mach->insn_chunk_bitsize != 0)
       {
         if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
           {
             fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
                     cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
             abort ();
           }

         cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
       }
      }

  /* Determine which hw elements are used by MACH.  */
  build_hw_table (cd);

  /* Build the ifield table.  */
  build_ifield_table (cd);

  /* Determine which operands are used by MACH/ISA.  */
  build_operand_table (cd);

  /* Build the instruction table.  */
  build_insn_table (cd);
}

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Variable Documentation

const CGEN_ATTR_ENTRY RL_TYPE_attr [] ATTRIBUTE_UNUSED [static]
Initial value:
{
  { "base", MACH_BASE },
  { "m16c", MACH_M16C },
  { "m32c", MACH_M32C },
  { "max", MACH_MAX },
  { 0, 0 }
}

Definition at line 46 of file m32c-desc.c.

Initial value:
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
}

Definition at line 39 of file m32c-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "ISA", & ISA_attr[0], & ISA_attr[0] },
  { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 86 of file m32c-desc.c.

Definition at line 706 of file m32c-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "ISA", & ISA_attr[0], & ISA_attr[0] },
  { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 72 of file m32c-desc.c.

Definition at line 797 of file m32c-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "ISA", & ISA_attr[0], & ISA_attr[0] },
  { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 114 of file m32c-desc.c.

Definition at line 2727 of file m32c-desc.c.

Initial value:
 {
  { "m16c", 32, 32, 8, 56 },
  { "m32c", 32, 32, 8, 80 },
  { 0, 0, 0, 0, 0 }
}

Definition at line 134 of file m32c-desc.c.

Initial value:
 {
  { "m16c", "m16c", MACH_M16C, 0 },
  { "m32c", "m32c", MACH_M32C, 0 },
  { 0, 0, 0, 0 }
}

Definition at line 142 of file m32c-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "ISA", & ISA_attr[0], & ISA_attr[0] },
  { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 98 of file m32c-desc.c.

Definition at line 1178 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_a0_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 433 of file m32c-desc.c.

Initial value:
{
  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 428 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_a1_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 445 of file m32c-desc.c.

Initial value:
{
  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 440 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_ar_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 383 of file m32c-desc.c.

Initial value:
{
  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 377 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_ar_HI_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 409 of file m32c-desc.c.

Initial value:
{
  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 403 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_ar_QI_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 396 of file m32c-desc.c.

Initial value:
{
  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 390 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_ar_SI_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 421 of file m32c-desc.c.

Initial value:
{
  { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 416 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cond16_entries[0],
  18,
  0, 0, 0, 0, ""
}

Definition at line 474 of file m32c-desc.c.

Initial value:
{
  { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "le", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "nc", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "leu", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "ne", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "nz", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "pz", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "gt", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "no", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "lt", 254, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 452 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cond16c_entries[0],
  18,
  0, 0, 0, 0, ""
}

Definition at line 503 of file m32c-desc.c.

Initial value:
{
  { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "pz", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 481 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cond16j_entries[0],
  6,
  0, 0, 0, 0, ""
}

Definition at line 520 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cond16j_5_entries[0],
  12,
  0, 0, 0, 0, ""
}

Definition at line 543 of file m32c-desc.c.

Initial value:
{
  { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 527 of file m32c-desc.c.

Initial value:
{
  { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 510 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cond32_entries[0],
  18,
  0, 0, 0, 0, ""
}

Definition at line 572 of file m32c-desc.c.

Initial value:
{
  { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "nc", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "leu", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "pz", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "no", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "gt", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "geu", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "c", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "eq", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "z", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "n", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "o", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "le", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 550 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cr1_32_entries[0],
  8,
  0, 0, 0, 0, ""
}

Definition at line 591 of file m32c-desc.c.

Initial value:
{
  { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "flg", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "svf", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 579 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cr2_32_entries[0],
  7,
  0, 0, 0, 0, ""
}

Definition at line 609 of file m32c-desc.c.

Initial value:
{
  { "intb", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "sb", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "fb", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "svp", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "vct", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "isp", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 598 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cr3_32_entries[0],
  6,
  0, 0, 0, 0, ""
}

Definition at line 626 of file m32c-desc.c.

Initial value:
{
  { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 616 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_cr_16_entries[0],
  7,
  0, 0, 0, 0, ""
}

Definition at line 644 of file m32c-desc.c.

Initial value:
{
  { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "flg", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "isp", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "sb", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "fb", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 633 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_flags_entries[0],
  8,
  0, 0, 0, 0, ""
}

Definition at line 663 of file m32c-desc.c.

Initial value:
{
  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "d", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "s", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "b", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "i", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "u", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 651 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_gr_entries[0],
  4,
  0, 0, 0, 0, ""
}

Definition at line 156 of file m32c-desc.c.

Initial value:
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 148 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_gr_ext_HI_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 225 of file m32c-desc.c.

Initial value:
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 219 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_gr_ext_QI_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 212 of file m32c-desc.c.

Initial value:
{
  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 206 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_gr_HI_entries[0],
  4,
  0, 0, 0, 0, ""
}

Definition at line 186 of file m32c-desc.c.

Initial value:
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 178 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_gr_QI_entries[0],
  4,
  0, 0, 0, 0, ""
}

Definition at line 171 of file m32c-desc.c.

Initial value:
{
  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 163 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_gr_SI_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 199 of file m32c-desc.c.

Initial value:
{
  { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 193 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r0_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 285 of file m32c-desc.c.

Initial value:
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 280 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r0h_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 249 of file m32c-desc.c.

Initial value:
{
  { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 244 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r0l_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 237 of file m32c-desc.c.

Initial value:
{
  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 232 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r0l_r0h_entries[0],
  2,
  0, 0, 0, 0, ""
}

Definition at line 334 of file m32c-desc.c.

Initial value:
{
  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 328 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r1_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 297 of file m32c-desc.c.

Initial value:
{
  { "r1", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 292 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r1h_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 273 of file m32c-desc.c.

Initial value:
{
  { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 268 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r1l_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 261 of file m32c-desc.c.

Initial value:
{
  { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 256 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r1r2r0_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 370 of file m32c-desc.c.

Initial value:
{
  { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 365 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r2_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 309 of file m32c-desc.c.

Initial value:
{
  { "r2", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 304 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r2r0_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 346 of file m32c-desc.c.

Initial value:
{
  { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 341 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r3_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 321 of file m32c-desc.c.

Initial value:
{
  { "r3", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 316 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_r3r1_entries[0],
  1,
  0, 0, 0, 0, ""
}

Definition at line 358 of file m32c-desc.c.

Initial value:
{
  { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 353 of file m32c-desc.c.

Initial value:
{
  & m32c_cgen_opval_h_shimm_entries[0],
  16,
  0, 0, 0, 0, ""
}

Definition at line 690 of file m32c-desc.c.

Initial value:
{
  { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "4", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "5", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "6", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "7", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "8", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "-1", -8, {0, {{{0, 0}}}}, 0, 0 },
  { "-2", -7, {0, {{{0, 0}}}}, 0, 0 },
  { "-3", -6, {0, {{{0, 0}}}}, 0, 0 },
  { "-4", -5, {0, {{{0, 0}}}}, 0, 0 },
  { "-5", -4, {0, {{{0, 0}}}}, 0, 0 },
  { "-6", -3, {0, {{{0, 0}}}}, 0, 0 },
  { "-7", -2, {0, {{{0, 0}}}}, 0, 0 },
  { "-8", -1, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 670 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 980 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 982 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 984 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 981 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 983 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 985 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 987 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 989 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 986 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 988 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 990 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 992 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 993 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 975 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 970 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 969 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 976 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 968 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 971 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 972 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 978 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 973 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 974 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 977 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 979 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 967 of file m32c-desc.c.

Initial value:
{
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
    { 0, { (const PTR) 0 } }
}

Definition at line 991 of file m32c-desc.c.