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cell-binutils  2.17cvs20070401
m10300-opc.c
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00001 /* Assemble Matsushita MN10300 instructions.
00002    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004
00003    Free Software Foundation, Inc.
00004 
00005 This program is free software; you can redistribute it and/or modify
00006 it under the terms of the GNU General Public License as published by
00007 the Free Software Foundation; either version 2 of the License, or
00008 (at your option) any later version.
00009 
00010 This program is distributed in the hope that it will be useful,
00011 but WITHOUT ANY WARRANTY; without even the implied warranty of
00012 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013 GNU General Public License for more details.
00014 
00015 You should have received a copy of the GNU General Public License
00016 along with this program; if not, write to the Free Software
00017 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00018 
00019 /* This file is formatted at > 80 columns.  Attempting to read it on a
00020    screeen with less than 80 columns will be difficult.  */
00021 #include "sysdep.h"
00022 #include "opcode/mn10300.h"
00023 
00024 
00025 const struct mn10300_operand mn10300_operands[] = {
00026 #define UNUSED       0
00027   {0, 0, 0}, 
00028 
00029 /* dn register in the first register operand position.  */
00030 #define DN0      (UNUSED+1)
00031   {2, 0, MN10300_OPERAND_DREG},
00032 
00033 /* dn register in the second register operand position.  */
00034 #define DN1      (DN0+1)
00035   {2, 2, MN10300_OPERAND_DREG},
00036 
00037 /* dn register in the third register operand position.  */
00038 #define DN2      (DN1+1)
00039   {2, 4, MN10300_OPERAND_DREG},
00040 
00041 /* dm register in the first register operand position.  */
00042 #define DM0      (DN2+1)
00043   {2, 0, MN10300_OPERAND_DREG},
00044 
00045 /* dm register in the second register operand position.  */
00046 #define DM1      (DM0+1)
00047   {2, 2, MN10300_OPERAND_DREG},
00048 
00049 /* dm register in the third register operand position.  */
00050 #define DM2      (DM1+1)
00051   {2, 4, MN10300_OPERAND_DREG},
00052 
00053 /* an register in the first register operand position.  */
00054 #define AN0      (DM2+1)
00055   {2, 0, MN10300_OPERAND_AREG},
00056 
00057 /* an register in the second register operand position.  */
00058 #define AN1      (AN0+1)
00059   {2, 2, MN10300_OPERAND_AREG},
00060 
00061 /* an register in the third register operand position.  */
00062 #define AN2      (AN1+1)
00063   {2, 4, MN10300_OPERAND_AREG},
00064 
00065 /* am register in the first register operand position.  */
00066 #define AM0      (AN2+1)
00067   {2, 0, MN10300_OPERAND_AREG},
00068 
00069 /* am register in the second register operand position.  */
00070 #define AM1      (AM0+1)
00071   {2, 2, MN10300_OPERAND_AREG},
00072 
00073 /* am register in the third register operand position.  */
00074 #define AM2      (AM1+1)
00075   {2, 4, MN10300_OPERAND_AREG},
00076 
00077 /* 8 bit unsigned immediate which may promote to a 16bit
00078    unsigned immediate.  */
00079 #define IMM8    (AM2+1)
00080   {8, 0, MN10300_OPERAND_PROMOTE},
00081 
00082 /* 16 bit unsigned immediate which may promote to a 32bit
00083    unsigned immediate.  */
00084 #define IMM16    (IMM8+1)
00085   {16, 0, MN10300_OPERAND_PROMOTE},
00086 
00087 /* 16 bit pc-relative immediate which may promote to a 16bit
00088    pc-relative immediate.  */
00089 #define IMM16_PCREL    (IMM16+1)
00090   {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
00091 
00092 /* 16bit unsigned displacement in a memory operation which
00093    may promote to a 32bit displacement.  */
00094 #define IMM16_MEM    (IMM16_PCREL+1)
00095   {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
00096 
00097 /* 32bit immediate, high 16 bits in the main instruction
00098    word, 16bits in the extension word. 
00099 
00100    The "bits" field indicates how many bits are in the
00101    main instruction word for MN10300_OPERAND_SPLIT!  */
00102 #define IMM32    (IMM16_MEM+1)
00103   {16, 0, MN10300_OPERAND_SPLIT},
00104 
00105 /* 32bit pc-relative offset.  */
00106 #define IMM32_PCREL    (IMM32+1)
00107   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
00108 
00109 /* 32bit memory offset.  */
00110 #define IMM32_MEM    (IMM32_PCREL+1)
00111   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
00112 
00113 /* 32bit immediate, high 16 bits in the main instruction
00114    word, 16bits in the extension word, low 16bits are left
00115    shifted 8 places. 
00116 
00117    The "bits" field indicates how many bits are in the
00118    main instruction word for MN10300_OPERAND_SPLIT!  */
00119 #define IMM32_LOWSHIFT8    (IMM32_MEM+1)
00120   {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
00121 
00122 /* 32bit immediate, high 24 bits in the main instruction
00123    word, 8 in the extension word.
00124 
00125    The "bits" field indicates how many bits are in the
00126    main instruction word for MN10300_OPERAND_SPLIT!  */
00127 #define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
00128   {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
00129 
00130 /* 32bit immediate, high 24 bits in the main instruction
00131    word, 8 in the extension word, low 8 bits are left
00132    shifted 16 places. 
00133 
00134    The "bits" field indicates how many bits are in the
00135    main instruction word for MN10300_OPERAND_SPLIT!  */
00136 #define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
00137   {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
00138 
00139 /* Stack pointer.  */
00140 #define SP    (IMM32_HIGH24_LOWSHIFT16+1)
00141   {8, 0, MN10300_OPERAND_SP},
00142 
00143 /* Processor status word.  */
00144 #define PSW    (SP+1)
00145   {0, 0, MN10300_OPERAND_PSW},
00146 
00147 /* MDR register.  */
00148 #define MDR    (PSW+1)
00149   {0, 0, MN10300_OPERAND_MDR},
00150 
00151 /* Index register.  */
00152 #define DI (MDR+1)
00153   {2, 2, MN10300_OPERAND_DREG},
00154 
00155 /* 8 bit signed displacement, may promote to 16bit signed displacement.  */
00156 #define SD8    (DI+1)
00157   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
00158 
00159 /* 16 bit signed displacement, may promote to 32bit displacement.  */
00160 #define SD16    (SD8+1)
00161   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
00162 
00163 /* 8 bit signed displacement that can not promote.  */
00164 #define SD8N    (SD16+1)
00165   {8, 0, MN10300_OPERAND_SIGNED},
00166 
00167 /* 8 bit pc-relative displacement.  */
00168 #define SD8N_PCREL    (SD8N+1)
00169   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
00170 
00171 /* 8 bit signed displacement shifted left 8 bits in the instruction.  */
00172 #define SD8N_SHIFT8    (SD8N_PCREL+1)
00173   {8, 8, MN10300_OPERAND_SIGNED},
00174 
00175 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
00176 #define SIMM8    (SD8N_SHIFT8+1)
00177   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
00178 
00179 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
00180 #define SIMM16    (SIMM8+1)
00181   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
00182 
00183 /* Either an open paren or close paren.  */
00184 #define PAREN (SIMM16+1)
00185   {0, 0, MN10300_OPERAND_PAREN}, 
00186 
00187 /* dn register that appears in the first and second register positions.  */
00188 #define DN01     (PAREN+1)
00189   {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
00190 
00191 /* an register that appears in the first and second register positions.  */
00192 #define AN01     (DN01+1)
00193   {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
00194 
00195 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
00196    displacement.  */
00197 #define D16_SHIFT (AN01+1)
00198   {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
00199 
00200 /* 8 bit immediate found in the extension word.  */
00201 #define IMM8E    (D16_SHIFT+1)
00202   {8, 0, MN10300_OPERAND_EXTENDED},
00203 
00204 /* Register list found in the extension word shifted 8 bits left.  */
00205 #define REGSE_SHIFT8    (IMM8E+1)
00206   {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
00207 
00208 /* Register list shifted 8 bits left.  */
00209 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
00210   {8, 8, MN10300_OPERAND_REG_LIST},
00211 
00212 /* Reigster list.  */
00213 #define REGS    (REGS_SHIFT8+1)
00214   {8, 0, MN10300_OPERAND_REG_LIST},
00215 
00216 /* UStack pointer.  */
00217 #define USP    (REGS+1)
00218   {0, 0, MN10300_OPERAND_USP},
00219 
00220 /* SStack pointer.  */
00221 #define SSP    (USP+1)
00222   {0, 0, MN10300_OPERAND_SSP},
00223 
00224 /* MStack pointer.  */
00225 #define MSP    (SSP+1)
00226   {0, 0, MN10300_OPERAND_MSP},
00227 
00228 /* PC .  */
00229 #define PC    (MSP+1)
00230   {0, 0, MN10300_OPERAND_PC},
00231 
00232 /* 4 bit immediate for syscall.  */
00233 #define IMM4    (PC+1)
00234   {4, 0, 0},
00235 
00236 /* Processor status word.  */
00237 #define EPSW    (IMM4+1)
00238   {0, 0, MN10300_OPERAND_EPSW},
00239 
00240 /* rn register in the first register operand position.  */
00241 #define RN0      (EPSW+1)
00242   {4, 0, MN10300_OPERAND_RREG},
00243 
00244 /* rn register in the fourth register operand position.  */
00245 #define RN2      (RN0+1)
00246   {4, 4, MN10300_OPERAND_RREG},
00247 
00248 /* rm register in the first register operand position.  */
00249 #define RM0      (RN2+1)
00250   {4, 0, MN10300_OPERAND_RREG},
00251 
00252 /* rm register in the second register operand position.  */
00253 #define RM1      (RM0+1)
00254   {4, 2, MN10300_OPERAND_RREG},
00255 
00256 /* rm register in the third register operand position.  */
00257 #define RM2      (RM1+1)
00258   {4, 4, MN10300_OPERAND_RREG},
00259 
00260 #define RN02      (RM2+1)
00261   {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
00262 
00263 #define XRN0      (RN02+1)
00264   {4, 0, MN10300_OPERAND_XRREG},
00265 
00266 #define XRM2      (XRN0+1)
00267   {4, 4, MN10300_OPERAND_XRREG},
00268 
00269 /* + for autoincrement */
00270 #define PLUS  (XRM2+1)
00271   {0, 0, MN10300_OPERAND_PLUS}, 
00272 
00273 #define XRN02      (PLUS+1)
00274   {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
00275 
00276 /* Ick */
00277 #define RD0      (XRN02+1)
00278   {4, -8, MN10300_OPERAND_RREG},
00279 
00280 #define RD2      (RD0+1)
00281   {4, -4, MN10300_OPERAND_RREG},
00282 
00283 /* 8 unsigned displacement in a memory operation which
00284    may promote to a 32bit displacement.  */
00285 #define IMM8_MEM    (RD2+1)
00286   {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
00287 
00288 /* Index register.  */
00289 #define RI (IMM8_MEM+1)
00290   {4, 4, MN10300_OPERAND_RREG},
00291 
00292 /* 24 bit signed displacement, may promote to 32bit displacement.  */
00293 #define SD24    (RI+1)
00294   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
00295 
00296 /* 24 bit unsigned immediate which may promote to a 32bit
00297    unsigned immediate.  */
00298 #define IMM24    (SD24+1)
00299   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
00300 
00301 /* 24 bit signed immediate which may promote to a 32bit
00302    signed immediate.  */
00303 #define SIMM24    (IMM24+1)
00304   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
00305 
00306 /* 24bit unsigned displacement in a memory operation which
00307    may promote to a 32bit displacement.  */
00308 #define IMM24_MEM    (SIMM24+1)
00309   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
00310 /* 32bit immediate, high 8 bits in the main instruction
00311    word, 24 in the extension word.
00312 
00313    The "bits" field indicates how many bits are in the
00314    main instruction word for MN10300_OPERAND_SPLIT!  */
00315 #define IMM32_HIGH8    (IMM24_MEM+1)
00316   {8, 0, MN10300_OPERAND_SPLIT},
00317 
00318 /* Similarly, but a memory address.  */
00319 #define IMM32_HIGH8_MEM  (IMM32_HIGH8+1)
00320   {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
00321 
00322 /* rm register in the seventh register operand position.  */
00323 #define RM6      (IMM32_HIGH8_MEM+1)
00324   {4, 12, MN10300_OPERAND_RREG},
00325 
00326 /* rm register in the fifth register operand position.  */
00327 #define RN4      (RM6+1)
00328   {4, 8, MN10300_OPERAND_RREG},
00329 
00330 /* 4 bit immediate for dsp instructions.  */
00331 #define IMM4_2    (RN4+1)
00332   {4, 4, 0},
00333 
00334 /* 4 bit immediate for dsp instructions.  */
00335 #define SIMM4_2    (IMM4_2+1)
00336   {4, 4, MN10300_OPERAND_SIGNED},
00337 
00338 /* 4 bit immediate for dsp instructions.  */
00339 #define SIMM4_6    (SIMM4_2+1)
00340   {4, 12, MN10300_OPERAND_SIGNED},
00341 
00342 #define FPCR      (SIMM4_6+1)
00343   {0, 0, MN10300_OPERAND_FPCR},
00344 
00345 /* We call f[sd]m registers those whose most significant bit is stored
00346  * within the opcode half-word, i.e., in a bit on the left of the 4
00347  * least significant bits, and f[sd]n registers those whose most
00348  * significant bit is stored at the end of the full word, after the 4
00349  * least significant bits.  They're not numbered after their position
00350  * in the mnemonic asm instruction, but after their position in the
00351  * opcode word, i.e., depending on the amount of shift they need.
00352  *
00353  * The additional bit is shifted as follows: for `n' registers, it
00354  * will be shifted by (|shift|/4); for `m' registers, it will be
00355  * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose
00356  * specifications are only 3-bits long, the two least-significant bits
00357  * are shifted by 16, and the most-significant bit is shifted by -2
00358  * (i.e., it's stored in the least significant bit of the full
00359  * word).  */
00360 
00361 /* fsm register in the first register operand position.  */
00362 #define FSM0      (FPCR+1)
00363   {5, 0, MN10300_OPERAND_FSREG },
00364 
00365 /* fsm register in the second register operand position.  */
00366 #define FSM1      (FSM0+1)
00367   {5, 4, MN10300_OPERAND_FSREG },
00368 
00369 /* fsm register in the third register operand position.  */
00370 #define FSM2      (FSM1+1)
00371   {5, 8, MN10300_OPERAND_FSREG },
00372 
00373 /* fsm register in the fourth register operand position.  */
00374 #define FSM3      (FSM2+1)
00375   {5, 12, MN10300_OPERAND_FSREG },
00376 
00377 /* fsn register in the first register operand position.  */
00378 #define FSN1      (FSM3+1)
00379   {5, -4, MN10300_OPERAND_FSREG },
00380 
00381 /* fsn register in the second register operand position.  */
00382 #define FSN2      (FSN1+1)
00383   {5, -8, MN10300_OPERAND_FSREG },
00384 
00385 /* fsm register in the third register operand position.  */
00386 #define FSN3      (FSN2+1)
00387   {5, -12, MN10300_OPERAND_FSREG },
00388 
00389 /* fsm accumulator, in the fourth register operand position.  */
00390 #define FSACC     (FSN3+1)
00391   {3, -16, MN10300_OPERAND_FSREG },
00392 
00393 /* fdm register in the first register operand position.  */
00394 #define FDM0      (FSACC+1)
00395   {5, 0, MN10300_OPERAND_FDREG },
00396 
00397 /* fdm register in the second register operand position.  */
00398 #define FDM1      (FDM0+1)
00399   {5, 4, MN10300_OPERAND_FDREG },
00400 
00401 /* fdm register in the third register operand position.  */
00402 #define FDM2      (FDM1+1)
00403   {5, 8, MN10300_OPERAND_FDREG },
00404 
00405 /* fdm register in the fourth register operand position.  */
00406 #define FDM3      (FDM2+1)
00407   {5, 12, MN10300_OPERAND_FDREG },
00408 
00409 /* fdn register in the first register operand position.  */
00410 #define FDN1      (FDM3+1)
00411   {5, -4, MN10300_OPERAND_FDREG },
00412 
00413 /* fdn register in the second register operand position.  */
00414 #define FDN2      (FDN1+1)
00415   {5, -8, MN10300_OPERAND_FDREG },
00416 
00417 /* fdn register in the third register operand position.  */
00418 #define FDN3      (FDN2+1)
00419   {5, -12, MN10300_OPERAND_FDREG },
00420 
00421 } ; 
00422 
00423 #define MEM(ADDR) PAREN, ADDR, PAREN 
00424 #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN 
00425 #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN 
00426 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
00427 
00428 /* The opcode table.
00429 
00430    The format of the opcode table is:
00431 
00432    NAME              OPCODE        MASK   MATCH_MASK, FORMAT, PROCESSOR      { OPERANDS }
00433 
00434    NAME is the name of the instruction.
00435    OPCODE is the instruction opcode.
00436    MASK is the opcode mask; this is used to tell the disassembler
00437      which bits in the actual opcode must match OPCODE.
00438    OPERANDS is the list of operands.
00439 
00440    The disassembler reads the table in order and prints the first
00441    instruction which matches, so this table is sorted to put more
00442    specific instructions before more general instructions.  It is also
00443    sorted by major opcode.  */
00444 
00445 const struct mn10300_opcode mn10300_opcodes[] = {
00446 { "mov",      0x8000,            0xf000,    0,    FMT_S1, 0,   {SIMM8, DN01}},
00447 { "mov",      0x80,       0xf0,      0x3,  FMT_S0, 0,   {DM1, DN0}},
00448 { "mov",      0xf1e0,            0xfff0,    0,    FMT_D0, 0,   {DM1, AN0}},
00449 { "mov",      0xf1d0,            0xfff0,    0,    FMT_D0, 0,   {AM1, DN0}},
00450 { "mov",      0x9000,            0xf000,    0,    FMT_S1, 0,   {IMM8, AN01}},
00451 { "mov",      0x90,       0xf0,      0x3,  FMT_S0, 0,   {AM1, AN0}},
00452 { "mov",      0x3c,       0xfc,      0,    FMT_S0, 0,   {SP, AN0}},
00453 { "mov",      0xf2f0,            0xfff3,    0,    FMT_D0, 0,   {AM1, SP}},
00454 { "mov",      0xf2e4,            0xfffc,    0,    FMT_D0, 0,   {PSW, DN0}},
00455 { "mov",      0xf2f3,            0xfff3,    0,    FMT_D0, 0,   {DM1, PSW}},
00456 { "mov",      0xf2e0,            0xfffc,    0,    FMT_D0, 0,   {MDR, DN0}},
00457 { "mov",      0xf2f2,            0xfff3,    0,    FMT_D0, 0,   {DM1, MDR}},
00458 { "mov",      0x70,       0xf0,      0,    FMT_S0, 0,   {MEM(AM0), DN1}},
00459 { "mov",      0x5800,            0xfcff,    0,    FMT_S1, 0,   {MEM(SP), DN0}},
00460 { "mov",      0x300000,    0xfc0000,    0,    FMT_S2, 0,       {MEM(IMM16_MEM), DN0}},
00461 { "mov",      0xf000,            0xfff0,    0,    FMT_D0, 0,   {MEM(AM0), AN1}},
00462 { "mov",      0x5c00,            0xfcff,    0,    FMT_S1, 0,   {MEM(SP), AN0}},
00463 { "mov",      0xfaa00000,  0xfffc0000,  0,    FMT_D2, 0,       {MEM(IMM16_MEM), AN0}},
00464 { "mov",      0x60,       0xf0,      0,    FMT_S0, 0,   {DM1, MEM(AN0)}},
00465 { "mov",      0x4200,            0xf3ff,    0,    FMT_S1, 0,   {DM1, MEM(SP)}},
00466 { "mov",      0x010000,    0xf30000,    0,    FMT_S2, 0,       {DM1, MEM(IMM16_MEM)}},
00467 { "mov",      0xf010,            0xfff0,    0,    FMT_D0, 0,   {AM1, MEM(AN0)}},
00468 { "mov",      0x4300,            0xf3ff,    0,    FMT_S1, 0,   {AM1, MEM(SP)}},
00469 { "mov",      0xfa800000,  0xfff30000,  0,    FMT_D2, 0,       {AM1, MEM(IMM16_MEM)}},
00470 { "mov",      0x5c00,            0xfc00,    0,    FMT_S1, 0,   {MEM2(IMM8, SP), AN0}},
00471 { "mov",      0xf80000,    0xfff000,    0,    FMT_D1, 0,       {MEM2(SD8, AM0), DN1}},
00472 { "mov",      0xfa000000,  0xfff00000,  0,    FMT_D2, 0,       {MEM2(SD16, AM0), DN1}},
00473 { "mov",      0x5800,            0xfc00,    0,    FMT_S1, 0,   {MEM2(IMM8, SP), DN0}},
00474 { "mov",      0xfab40000,  0xfffc0000,  0,    FMT_D2, 0,       {MEM2(IMM16, SP), DN0}},
00475 { "mov",      0xf300,            0xffc0,    0,    FMT_D0, 0,   {MEM2(DI, AM0), DN2}},
00476 { "mov",      0xf82000,    0xfff000,    0,    FMT_D1, 0,       {MEM2(SD8,AM0), AN1}},
00477 { "mov",      0xfa200000,  0xfff00000,  0,    FMT_D2, 0,       {MEM2(SD16, AM0), AN1}},
00478 { "mov",      0xfab00000,  0xfffc0000,  0,    FMT_D2, 0,       {MEM2(IMM16, SP), AN0}},
00479 { "mov",      0xf380,            0xffc0,    0,    FMT_D0, 0,   {MEM2(DI, AM0), AN2}},
00480 { "mov",      0x4300,            0xf300,    0,    FMT_S1, 0,   {AM1, MEM2(IMM8, SP)}},
00481 { "mov",      0xf81000,    0xfff000,    0,    FMT_D1, 0,       {DM1, MEM2(SD8, AN0)}},
00482 { "mov",      0xfa100000,  0xfff00000,  0,    FMT_D2, 0,       {DM1, MEM2(SD16, AN0)}},
00483 { "mov",      0x4200,            0xf300,    0,    FMT_S1, 0,   {DM1, MEM2(IMM8, SP)}},
00484 { "mov",      0xfa910000,  0xfff30000,  0,    FMT_D2, 0,       {DM1, MEM2(IMM16, SP)}},
00485 { "mov",      0xf340,            0xffc0,    0,    FMT_D0, 0,   {DM2, MEM2(DI, AN0)}},
00486 { "mov",      0xf83000,    0xfff000,    0,    FMT_D1, 0,       {AM1, MEM2(SD8, AN0)}},
00487 { "mov",      0xfa300000,  0xfff00000,  0,    FMT_D2, 0,       {AM1, MEM2(SD16, AN0)}},
00488 { "mov",      0xfa900000,  0xfff30000,  0,    FMT_D2, 0,       {AM1, MEM2(IMM16, SP)}},
00489 { "mov",      0xf3c0,            0xffc0,    0,    FMT_D0, 0,   {AM2, MEM2(DI, AN0)}},
00490 
00491 { "mov",      0xf020,            0xfffc,    0,    FMT_D0, AM33,       {USP, AN0}},
00492 { "mov",      0xf024,            0xfffc,    0,    FMT_D0, AM33,       {SSP, AN0}},
00493 { "mov",      0xf028,            0xfffc,    0,    FMT_D0, AM33,       {MSP, AN0}},
00494 { "mov",      0xf02c,            0xfffc,    0,    FMT_D0, AM33,       {PC, AN0}},
00495 { "mov",      0xf030,            0xfff3,    0,    FMT_D0, AM33,       {AN1, USP}},
00496 { "mov",      0xf031,            0xfff3,    0,    FMT_D0, AM33,       {AN1, SSP}},
00497 { "mov",      0xf032,            0xfff3,    0,    FMT_D0, AM33,       {AN1, MSP}},
00498 { "mov",      0xf2ec,            0xfffc,    0,    FMT_D0, AM33,       {EPSW, DN0}},
00499 { "mov",      0xf2f1,            0xfff3,    0,    FMT_D0, AM33,       {DM1, EPSW}},
00500 { "mov",      0xf500,            0xffc0,    0,    FMT_D0, AM33,       {AM2, RN0}},
00501 { "mov",      0xf540,            0xffc0,    0,    FMT_D0, AM33,       {DM2, RN0}},
00502 { "mov",      0xf580,            0xffc0,    0,    FMT_D0, AM33,       {RM1, AN0}},
00503 { "mov",      0xf5c0,            0xffc0,    0,    FMT_D0, AM33,       {RM1, DN0}},
00504 { "mov",      0xf90800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00505 { "mov",      0xf9e800,    0xffff00,    0,    FMT_D6, AM33,    {XRM2, RN0}},
00506 { "mov",      0xf9f800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, XRN0}},
00507 { "mov",      0xf90a00,    0xffff00,    0,    FMT_D6, AM33,    {MEM(RM0), RN2}},
00508 { "mov",      0xf98a00,    0xffff0f,    0,    FMT_D6, AM33,    {MEM(SP), RN2}},
00509 { "mov",      0xf96a00,    0xffff00,    0x12, FMT_D6, AM33,    {MEMINC(RM0), RN2}},
00510 { "mov",      0xfb0e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM(IMM8_MEM), RN2}},
00511 { "mov",      0xfd0e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM(IMM24_MEM), RN2}},
00512 { "mov",      0xf91a00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, MEM(RN0)}},
00513 { "mov",      0xf99a00,    0xffff0f,    0,    FMT_D6, AM33,    {RM2, MEM(SP)}},
00514 { "mov",      0xf97a00,    0xffff00,    0,       FMT_D6, AM33, {RM2, MEMINC(RN0)}},
00515 { "mov",      0xfb1e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM(IMM8_MEM)}},
00516 { "mov",      0xfd1e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM(IMM24_MEM)}},
00517 { "mov",      0xfb0a0000,  0xffff0000,  0,    FMT_D7, AM33,    {MEM2(SD8, RM0), RN2}},
00518 { "mov",      0xfd0a0000,  0xffff0000,  0,    FMT_D8, AM33,    {MEM2(SD24, RM0), RN2}},
00519 { "mov",      0xfb8e0000,  0xffff000f,  0,    FMT_D7, AM33,    {MEM2(RI, RM0), RD2}},
00520 { "mov",      0xfb1a0000,  0xffff0000,  0,    FMT_D7, AM33,    {RM2, MEM2(SD8, RN0)}},
00521 { "mov",      0xfd1a0000,  0xffff0000,  0,    FMT_D8, AM33,    {RM2, MEM2(SD24, RN0)}},
00522 { "mov",      0xfb8a0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM2(IMM8, SP), RN2}},
00523 { "mov",      0xfd8a0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM2(IMM24, SP), RN2}},
00524 { "mov",      0xfb9a0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM2(IMM8, SP)}},
00525 { "mov",      0xfd9a0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM2(IMM24, SP)}},
00526 { "mov",      0xfb9e0000,  0xffff000f,  0,    FMT_D7, AM33,    {RD2, MEM2(RI, RN0)}},
00527 { "mov",      0xfb6a0000,  0xffff0000,  0x22, FMT_D7, AM33,    {MEMINC2 (RM0, SIMM8), RN2}},
00528 { "mov",      0xfb7a0000,  0xffff0000,  0,       FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
00529 { "mov",      0xfd6a0000,  0xffff0000,  0x22, FMT_D8, AM33,    {MEMINC2 (RM0, IMM24), RN2}},
00530 { "mov",      0xfd7a0000,  0xffff0000,  0,       FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
00531 { "mov",      0xfe6a0000,  0xffff0000,  0x22, FMT_D9, AM33,    {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
00532 { "mov",      0xfe7a0000,  0xffff0000,  0,       FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
00533 /* These must come after most of the other move instructions to avoid matching
00534    a symbolic name with IMMxx operands.  Ugh.  */
00535 { "mov",      0x2c0000,    0xfc0000,    0,    FMT_S2, 0,       {SIMM16, DN0}},
00536 { "mov",      0xfccc0000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00537 { "mov",      0x240000,    0xfc0000,    0,    FMT_S2, 0,       {IMM16, AN0}},
00538 { "mov",      0xfcdc0000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, AN0}},
00539 { "mov",      0xfca40000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM(IMM32_MEM), DN0}},
00540 { "mov",      0xfca00000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM(IMM32_MEM), AN0}},
00541 { "mov",      0xfc810000,  0xfff30000,  0,    FMT_D4, 0,       {DM1, MEM(IMM32_MEM)}},
00542 { "mov",      0xfc800000,  0xfff30000,  0,    FMT_D4, 0,       {AM1, MEM(IMM32_MEM)}},
00543 { "mov",      0xfc000000,  0xfff00000,  0,    FMT_D4, 0,       {MEM2(IMM32,AM0), DN1}},
00544 { "mov",      0xfcb40000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM2(IMM32, SP), DN0}},
00545 { "mov",      0xfc200000,  0xfff00000,  0,    FMT_D4, 0,       {MEM2(IMM32,AM0), AN1}},
00546 { "mov",      0xfcb00000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM2(IMM32, SP), AN0}},
00547 { "mov",      0xfc100000,  0xfff00000,  0,    FMT_D4, 0,       {DM1, MEM2(IMM32,AN0)}},
00548 { "mov",      0xfc910000,  0xfff30000,  0,    FMT_D4, 0,       {DM1, MEM2(IMM32, SP)}},
00549 { "mov",      0xfc300000,  0xfff00000,  0,    FMT_D4, 0,       {AM1, MEM2(IMM32,AN0)}},
00550 { "mov",      0xfc900000,  0xfff30000,  0,    FMT_D4, 0,       {AM1, MEM2(IMM32, SP)}},
00551 /* These non-promoting variants need to come after all the other memory
00552    moves.  */
00553 { "mov",      0xf8f000,    0xfffc00,    0,    FMT_D1, AM30,    {MEM2(SD8N, AM0), SP}},
00554 { "mov",      0xf8f400,    0xfffc00,    0,    FMT_D1, AM30,    {SP, MEM2(SD8N, AN0)}},
00555 /* These are the same as the previous non-promoting versions.  The am33
00556    does not have restrictions on the offsets used to load/store the stack
00557    pointer.  */
00558 { "mov",      0xf8f000,    0xfffc00,    0,    FMT_D1, AM33,    {MEM2(SD8, AM0), SP}},
00559 { "mov",      0xf8f400,    0xfffc00,    0,    FMT_D1, AM33,    {SP, MEM2(SD8, AN0)}},
00560 /* These must come last so that we favor shorter move instructions for
00561    loading immediates into d0-d3/a0-a3.  */
00562 { "mov",      0xfb080000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00563 { "mov",      0xfd080000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00564 { "mov",      0xfe080000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00565 { "mov",      0xfbf80000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, XRN02}},
00566 { "mov",      0xfdf80000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, XRN02}},
00567 { "mov",      0xfef80000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, XRN02}},
00568 { "mov",      0xfe0e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM(IMM32_HIGH8_MEM), RN2}},
00569 { "mov",      0xfe1e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM(IMM32_HIGH8_MEM)}},
00570 { "mov",      0xfe0a0000,  0xffff0000,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,RM0), RN2}},
00571 { "mov",      0xfe1a0000,  0xffff0000,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, RN0)}},
00572 { "mov",      0xfe8a0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8, SP), RN2}},
00573 { "mov",      0xfe9a0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, SP)}},
00574 
00575 { "movu",     0xfb180000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00576 { "movu",     0xfd180000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00577 { "movu",     0xfe180000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00578 
00579 { "mcst9",    0xf630,      0xfff0,   0,    FMT_D0, AM33,       {DN01}},
00580 { "mcst48",   0xf660,            0xfff0,    0,    FMT_D0, AM33,       {DN01}},
00581 { "swap",     0xf680,            0xfff0,    0,    FMT_D0, AM33,       {DM1, DN0}},
00582 { "swap",     0xf9cb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00583 { "swaph",    0xf690,            0xfff0,    0,    FMT_D0, AM33,       {DM1, DN0}},
00584 { "swaph",    0xf9db00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00585 { "getchx",   0xf6c0,            0xfff0,    0,    FMT_D0, AM33,       {DN01}},
00586 { "getclx",   0xf6d0,            0xfff0,    0,    FMT_D0, AM33,       {DN01}},
00587 { "mac",      0xfb0f0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00588 { "mac",      0xf90b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00589 { "mac",      0xfb0b0000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00590 { "mac",      0xfd0b0000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00591 { "mac",      0xfe0b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00592 { "macu",     0xfb1f0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00593 { "macu",     0xf91b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00594 { "macu",     0xfb1b0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00595 { "macu",     0xfd1b0000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00596 { "macu",     0xfe1b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00597 { "macb",     0xfb2f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00598 { "macb",     0xf92b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00599 { "macb",     0xfb2b0000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00600 { "macb",     0xfd2b0000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00601 { "macb",     0xfe2b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00602 { "macbu",    0xfb3f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00603 { "macbu",    0xf93b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00604 { "macbu",    0xfb3b0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00605 { "macbu",    0xfd3b0000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00606 { "macbu",    0xfe3b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00607 { "mach",     0xfb4f0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00608 { "mach",     0xf94b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00609 { "mach",     0xfb4b0000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00610 { "mach",     0xfd4b0000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00611 { "mach",     0xfe4b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00612 { "machu",    0xfb5f0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00613 { "machu",    0xf95b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00614 { "machu",    0xfb5b0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00615 { "machu",    0xfd5b0000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00616 { "machu",    0xfe5b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00617 { "dmach",    0xfb6f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00618 { "dmach",    0xf96b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00619 { "dmach",    0xfe6b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00620 { "dmachu",   0xfb7f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00621 { "dmachu",   0xf97b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00622 { "dmachu",   0xfe7b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00623 { "dmulh",    0xfb8f0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00624 { "dmulh",    0xf98b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00625 { "dmulh",    0xfe8b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00626 { "dmulhu",   0xfb9f0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00627 { "dmulhu",   0xf99b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00628 { "dmulhu",   0xfe9b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00629 { "mcste",    0xf9bb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00630 { "mcste",    0xfbbb0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00631 { "swhw",     0xf9eb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00632 
00633 { "movbu",    0xf040,            0xfff0,    0,    FMT_D0, 0,   {MEM(AM0), DN1}},
00634 { "movbu",    0xf84000,    0xfff000,    0,    FMT_D1, 0,       {MEM2(SD8, AM0), DN1}},
00635 { "movbu",    0xfa400000,  0xfff00000,  0,    FMT_D2, 0,       {MEM2(SD16, AM0), DN1}},
00636 { "movbu",    0xf8b800,    0xfffcff,    0,    FMT_D1, 0,       {MEM(SP), DN0}},
00637 { "movbu",    0xf8b800,    0xfffc00,    0,    FMT_D1, 0,       {MEM2(IMM8, SP), DN0}},
00638 { "movbu",    0xfab80000,  0xfffc0000,  0,    FMT_D2, 0,       {MEM2(IMM16, SP), DN0}},
00639 { "movbu",    0xf400,            0xffc0,    0,    FMT_D0, 0,   {MEM2(DI, AM0), DN2}},
00640 { "movbu",    0x340000,    0xfc0000,    0,    FMT_S2, 0,       {MEM(IMM16_MEM), DN0}},
00641 { "movbu",    0xf050,            0xfff0,    0,    FMT_D0, 0,   {DM1, MEM(AN0)}},
00642 { "movbu",    0xf85000,    0xfff000,    0,    FMT_D1, 0,       {DM1, MEM2(SD8, AN0)}},
00643 { "movbu",    0xfa500000,  0xfff00000,  0,    FMT_D2, 0,       {DM1, MEM2(SD16, AN0)}},
00644 { "movbu",    0xf89200,    0xfff3ff,    0,    FMT_D1, 0,       {DM1, MEM(SP)}},
00645 { "movbu",    0xf89200,    0xfff300,    0,    FMT_D1, 0,       {DM1, MEM2(IMM8, SP)}},
00646 { "movbu",    0xfa920000,  0xfff30000,  0,    FMT_D2, 0,       {DM1, MEM2(IMM16, SP)}},
00647 { "movbu",    0xf440,            0xffc0,    0,    FMT_D0, 0,   {DM2, MEM2(DI, AN0)}},
00648 { "movbu",    0x020000,    0xf30000,    0,    FMT_S2, 0,       {DM1, MEM(IMM16_MEM)}},
00649 { "movbu",    0xf92a00,    0xffff00,    0,    FMT_D6, AM33,    {MEM(RM0), RN2}},
00650 { "movbu",    0xf93a00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, MEM(RN0)}},
00651 { "movbu",    0xf9aa00,    0xffff0f,    0,    FMT_D6, AM33,    {MEM(SP), RN2}},
00652 { "movbu",    0xf9ba00,    0xffff0f,    0,    FMT_D6, AM33,    {RM2, MEM(SP)}},
00653 { "movbu",    0xfb2a0000,  0xffff0000,  0,    FMT_D7, AM33,    {MEM2(SD8, RM0), RN2}},
00654 { "movbu",    0xfd2a0000,  0xffff0000,  0,    FMT_D8, AM33,    {MEM2(SD24, RM0), RN2}},
00655 { "movbu",    0xfb3a0000,  0xffff0000,  0,    FMT_D7, AM33,    {RM2, MEM2(SD8, RN0)}},
00656 { "movbu",    0xfd3a0000,  0xffff0000,  0,    FMT_D8, AM33,    {RM2, MEM2(SD24, RN0)}},
00657 { "movbu",    0xfbaa0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM2(IMM8, SP), RN2}},
00658 { "movbu",    0xfdaa0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM2(IMM24, SP), RN2}},
00659 { "movbu",    0xfbba0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM2(IMM8, SP)}},
00660 { "movbu",    0xfdba0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM2(IMM24, SP)}},
00661 { "movbu",    0xfb2e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM(IMM8_MEM), RN2}},
00662 { "movbu",    0xfd2e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM(IMM24_MEM), RN2}},
00663 { "movbu",    0xfb3e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM(IMM8_MEM)}},
00664 { "movbu",    0xfd3e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM(IMM24_MEM)}},
00665 { "movbu",    0xfbae0000,  0xffff000f,  0,    FMT_D7, AM33,    {MEM2(RI, RM0), RD2}},
00666 { "movbu",    0xfbbe0000,  0xffff000f,  0,    FMT_D7, AM33,    {RD2, MEM2(RI, RN0)}},
00667 { "movbu",    0xfc400000,  0xfff00000,  0,    FMT_D4, 0,       {MEM2(IMM32,AM0), DN1}},
00668 { "movbu",    0xfcb80000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM2(IMM32, SP), DN0}},
00669 { "movbu",    0xfca80000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM(IMM32_MEM), DN0}},
00670 { "movbu",    0xfc500000,  0xfff00000,  0,    FMT_D4, 0,       {DM1, MEM2(IMM32,AN0)}},
00671 { "movbu",    0xfc920000,  0xfff30000,  0,    FMT_D4, 0,       {DM1, MEM2(IMM32, SP)}},
00672 { "movbu",    0xfc820000,  0xfff30000,  0,    FMT_D4, 0,       {DM1, MEM(IMM32_MEM)}},
00673 { "movbu",    0xfe2a0000,  0xffff0000,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,RM0), RN2}},
00674 { "movbu",    0xfe3a0000,  0xffff0000,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, RN0)}},
00675 { "movbu",    0xfeaa0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,SP), RN2}},
00676 { "movbu",    0xfeba0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, SP)}},
00677 { "movbu",    0xfe2e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM(IMM32_HIGH8_MEM), RN2}},
00678 { "movbu",    0xfe3e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM(IMM32_HIGH8_MEM)}},
00679 
00680 { "movhu",    0xf060,            0xfff0,    0,    FMT_D0, 0,   {MEM(AM0), DN1}},
00681 { "movhu",    0xf86000,    0xfff000,    0,    FMT_D1, 0,       {MEM2(SD8, AM0), DN1}},
00682 { "movhu",    0xfa600000,  0xfff00000,  0,    FMT_D2, 0,       {MEM2(SD16, AM0), DN1}},
00683 { "movhu",    0xf8bc00,    0xfffcff,    0,    FMT_D1, 0,       {MEM(SP), DN0}},
00684 { "movhu",    0xf8bc00,    0xfffc00,    0,    FMT_D1, 0,       {MEM2(IMM8, SP), DN0}},
00685 { "movhu",    0xfabc0000,  0xfffc0000,  0,    FMT_D2, 0,       {MEM2(IMM16, SP), DN0}},
00686 { "movhu",    0xf480,            0xffc0,    0,    FMT_D0, 0,   {MEM2(DI, AM0), DN2}},
00687 { "movhu",    0x380000,    0xfc0000,    0,    FMT_S2, 0,       {MEM(IMM16_MEM), DN0}},
00688 { "movhu",    0xf070,            0xfff0,    0,    FMT_D0, 0,   {DM1, MEM(AN0)}},
00689 { "movhu",    0xf87000,    0xfff000,    0,    FMT_D1, 0,       {DM1, MEM2(SD8, AN0)}},
00690 { "movhu",    0xfa700000,  0xfff00000,  0,    FMT_D2, 0,       {DM1, MEM2(SD16, AN0)}},
00691 { "movhu",    0xf89300,    0xfff3ff,    0,    FMT_D1, 0,       {DM1, MEM(SP)}},
00692 { "movhu",    0xf89300,    0xfff300,    0,    FMT_D1, 0,       {DM1, MEM2(IMM8, SP)}},
00693 { "movhu",    0xfa930000,  0xfff30000,  0,    FMT_D2, 0,       {DM1, MEM2(IMM16, SP)}},
00694 { "movhu",    0xf4c0,            0xffc0,    0,    FMT_D0, 0,   {DM2, MEM2(DI, AN0)}},
00695 { "movhu",    0x030000,    0xf30000,    0,    FMT_S2, 0,       {DM1, MEM(IMM16_MEM)}},
00696 { "movhu",    0xf94a00,    0xffff00,    0,    FMT_D6, AM33,    {MEM(RM0), RN2}},
00697 { "movhu",    0xf95a00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, MEM(RN0)}},
00698 { "movhu",    0xf9ca00,    0xffff0f,    0,    FMT_D6, AM33,    {MEM(SP), RN2}},
00699 { "movhu",    0xf9da00,    0xffff0f,    0,    FMT_D6, AM33,    {RM2, MEM(SP)}},
00700 { "movhu",    0xf9ea00,    0xffff00,    0x12, FMT_D6, AM33,    {MEMINC(RM0), RN2}},
00701 { "movhu",    0xf9fa00,    0xffff00,    0,       FMT_D6, AM33, {RM2, MEMINC(RN0)}},
00702 { "movhu",    0xfb4a0000,  0xffff0000,  0,    FMT_D7, AM33,    {MEM2(SD8, RM0), RN2}},
00703 { "movhu",    0xfd4a0000,  0xffff0000,  0,    FMT_D8, AM33,    {MEM2(SD24, RM0), RN2}},
00704 { "movhu",    0xfb5a0000,  0xffff0000,  0,    FMT_D7, AM33,    {RM2, MEM2(SD8, RN0)}},
00705 { "movhu",    0xfd5a0000,  0xffff0000,  0,    FMT_D8, AM33,    {RM2, MEM2(SD24, RN0)}},
00706 { "movhu",    0xfbca0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM2(IMM8, SP), RN2}},
00707 { "movhu",    0xfdca0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM2(IMM24, SP), RN2}},
00708 { "movhu",    0xfbda0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM2(IMM8, SP)}},
00709 { "movhu",    0xfdda0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM2(IMM24, SP)}},
00710 { "movhu",    0xfb4e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM(IMM8_MEM), RN2}},
00711 { "movhu",    0xfd4e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM(IMM24_MEM), RN2}},
00712 { "movhu",    0xfbce0000,  0xffff000f,  0,    FMT_D7, AM33,    {MEM2(RI, RM0), RD2}},
00713 { "movhu",    0xfbde0000,  0xffff000f,  0,    FMT_D7, AM33,    {RD2, MEM2(RI, RN0)}},
00714 { "movhu",    0xfc600000,  0xfff00000,  0,    FMT_D4, 0,       {MEM2(IMM32,AM0), DN1}},
00715 { "movhu",    0xfcbc0000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM2(IMM32, SP), DN0}},
00716 { "movhu",    0xfcac0000,  0xfffc0000,  0,    FMT_D4, 0,       {MEM(IMM32_MEM), DN0}},
00717 { "movhu",    0xfc700000,  0xfff00000,  0,    FMT_D4, 0,       {DM1, MEM2(IMM32,AN0)}},
00718 { "movhu",    0xfc930000,  0xfff30000,  0,    FMT_D4, 0,       {DM1, MEM2(IMM32, SP)}},
00719 { "movhu",    0xfc830000,  0xfff30000,  0,    FMT_D4, 0,       {DM1, MEM(IMM32_MEM)}},
00720 { "movhu",    0xfe4a0000,  0xffff0000,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,RM0), RN2}},
00721 { "movhu",    0xfe5a0000,  0xffff0000,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, RN0)}},
00722 { "movhu",    0xfeca0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8, SP), RN2}},
00723 { "movhu",    0xfeda0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, SP)}},
00724 { "movhu",    0xfe4e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM(IMM32_HIGH8_MEM), RN2}},
00725 { "movhu",    0xfb5e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM(IMM8_MEM)}},
00726 { "movhu",    0xfd5e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM(IMM24_MEM)}},
00727 { "movhu",    0xfe5e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM(IMM32_HIGH8_MEM)}},
00728 { "movhu",    0xfbea0000,  0xffff0000,  0x22, FMT_D7, AM33,    {MEMINC2 (RM0, SIMM8), RN2}},
00729 { "movhu",    0xfbfa0000,  0xffff0000,  0,       FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
00730 { "movhu",    0xfdea0000,  0xffff0000,  0x22, FMT_D8, AM33,    {MEMINC2 (RM0, IMM24), RN2}},
00731 { "movhu",    0xfdfa0000,  0xffff0000,  0,       FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
00732 { "movhu",    0xfeea0000,  0xffff0000,  0x22, FMT_D9, AM33,    {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
00733 { "movhu",    0xfefa0000,  0xffff0000,  0,       FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
00734 
00735 { "ext",      0xf2d0,            0xfffc,    0,    FMT_D0, 0,   {DN0}},
00736 { "ext",      0xf91800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00737 
00738 { "extb",     0xf92800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00739 { "extb",     0x10,       0xfc,      0,    FMT_S0, 0,   {DN0}},
00740 { "extb",     0xf92800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00741 
00742 { "extbu",    0xf93800,    0xffff00,        0,    FMT_D6, AM33,       {RM2, RN0}},
00743 { "extbu",    0x14,       0xfc,      0,    FMT_S0, 0,   {DN0}},
00744 { "extbu",    0xf93800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00745 
00746 { "exth",     0xf94800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00747 { "exth",     0x18,       0xfc,      0,    FMT_S0, 0,   {DN0}},
00748 { "exth",     0xf94800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00749 
00750 { "exthu",    0xf95800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00751 { "exthu",    0x1c,       0xfc,      0,    FMT_S0, 0,   {DN0}},
00752 { "exthu",    0xf95800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00753 
00754 { "movm",     0xce00,            0xff00,    0,    FMT_S1, 0,   {MEM(SP), REGS}},
00755 { "movm",     0xcf00,            0xff00,    0,    FMT_S1, 0,   {REGS, MEM(SP)}},
00756 { "movm",     0xf8ce00,    0xffff00,    0,    FMT_D1, AM33,    {MEM(USP), REGS}},
00757 { "movm",     0xf8cf00,    0xffff00,    0,    FMT_D1, AM33,    {REGS, MEM(USP)}},
00758 
00759 { "clr",      0x00,       0xf3,      0,    FMT_S0, 0,   {DN1}},
00760 { "clr",      0xf96800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00761 
00762 { "add",      0xfb7c0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00763 { "add",      0xe0,       0xf0,      0,    FMT_S0, 0,   {DM1, DN0}},
00764 { "add",      0xf160,            0xfff0,    0,    FMT_D0, 0,   {DM1, AN0}},
00765 { "add",      0xf150,            0xfff0,    0,    FMT_D0, 0,   {AM1, DN0}},
00766 { "add",      0xf170,            0xfff0,    0,    FMT_D0, 0,   {AM1, AN0}},
00767 { "add",      0x2800,            0xfc00,    0,    FMT_S1, 0,   {SIMM8, DN0}},
00768 { "add",      0xfac00000,  0xfffc0000,  0,    FMT_D2, 0,       {SIMM16, DN0}},
00769 { "add",      0x2000,            0xfc00,    0,    FMT_S1, 0,   {SIMM8, AN0}},
00770 { "add",      0xfad00000,  0xfffc0000,  0,    FMT_D2, 0,       {SIMM16, AN0}},
00771 { "add",      0xf8fe00,    0xffff00,    0,    FMT_D1, 0,       {SIMM8, SP}},
00772 { "add",      0xfafe0000,  0xffff0000,  0,    FMT_D2, 0,       {SIMM16, SP}},
00773 { "add",      0xf97800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00774 { "add",      0xfcc00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00775 { "add",      0xfcd00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, AN0}},
00776 { "add",      0xfcfe0000,  0xffff0000,  0,    FMT_D4, 0,       {IMM32, SP}},
00777 { "add",      0xfb780000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00778 { "add",      0xfd780000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00779 { "add",      0xfe780000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00780 
00781 { "addc",     0xfb8c0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00782 { "addc",     0xf140,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00783 { "addc",     0xf98800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00784 { "addc",     0xfb880000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00785 { "addc",     0xfd880000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00786 { "addc",     0xfe880000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00787 
00788 { "sub",      0xfb9c0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00789 { "sub",      0xf100,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00790 { "sub",      0xf120,            0xfff0,    0,    FMT_D0, 0,   {DM1, AN0}},
00791 { "sub",      0xf110,            0xfff0,    0,    FMT_D0, 0,   {AM1, DN0}},
00792 { "sub",      0xf130,            0xfff0,    0,    FMT_D0, 0,   {AM1, AN0}},
00793 { "sub",      0xf99800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00794 { "sub",      0xfcc40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00795 { "sub",      0xfcd40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, AN0}},
00796 { "sub",      0xfb980000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00797 { "sub",      0xfd980000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00798 { "sub",      0xfe980000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00799 
00800 { "subc",     0xfbac0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00801 { "subc",     0xf180,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00802 { "subc",     0xf9a800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00803 { "subc",     0xfba80000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00804 { "subc",     0xfda80000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00805 { "subc",     0xfea80000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00806 
00807 { "mul",      0xfbad0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00808 { "mul",      0xf240,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00809 { "mul",      0xf9a900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00810 { "mul",      0xfba90000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00811 { "mul",      0xfda90000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00812 { "mul",      0xfea90000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00813 
00814 { "mulu",     0xfbbd0000,  0xffff0000,  0xc,  FMT_D7, AM33,    {RM2, RN0, RD2, RD0}},
00815 { "mulu",     0xf250,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00816 { "mulu",     0xf9b900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00817 { "mulu",     0xfbb90000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00818 { "mulu",     0xfdb90000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00819 { "mulu",     0xfeb90000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00820 
00821 { "div",      0xf260,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00822 { "div",      0xf9c900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00823 
00824 { "divu",     0xf270,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00825 { "divu",     0xf9d900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00826 
00827 { "inc",      0x40,       0xf3,      0,    FMT_S0, 0,   {DN1}},
00828 { "inc",      0x41,       0xf3,      0,    FMT_S0, 0,   {AN1}},
00829 { "inc",      0xf9b800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00830 
00831 { "inc4",     0x50,       0xfc,      0,    FMT_S0, 0,   {AN0}},
00832 { "inc4",     0xf9c800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00833 
00834 { "cmp",      0xa000,            0xf000,    0,    FMT_S1, 0,   {SIMM8, DN01}},
00835 { "cmp",      0xa0,       0xf0,      0x3,  FMT_S0, 0,   {DM1, DN0}},
00836 { "cmp",      0xf1a0,            0xfff0,    0,    FMT_D0, 0,   {DM1, AN0}},
00837 { "cmp",      0xf190,            0xfff0,    0,    FMT_D0, 0,   {AM1, DN0}},
00838 { "cmp",      0xb000,            0xf000,    0,    FMT_S1, 0,   {IMM8, AN01}},
00839 { "cmp",      0xb0,       0xf0,      0x3,  FMT_S0, 0,   {AM1, AN0}},
00840 { "cmp",      0xfac80000,  0xfffc0000,  0,    FMT_D2, 0,       {SIMM16, DN0}},
00841 { "cmp",      0xfad80000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM16, AN0}},
00842 { "cmp",      0xf9d800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00843 { "cmp",      0xfcc80000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00844 { "cmp",      0xfcd80000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, AN0}},
00845 { "cmp",      0xfbd80000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00846 { "cmp",      0xfdd80000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
00847 { "cmp",      0xfed80000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00848 
00849 { "and",      0xfb0d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00850 { "and",      0xf200,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00851 { "and",      0xf8e000,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
00852 { "and",      0xfae00000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM16, DN0}},
00853 { "and",      0xfafc0000,  0xffff0000,  0,    FMT_D2, 0,       {IMM16, PSW}},
00854 { "and",      0xfcfc0000,  0xffff0000,  0,    FMT_D4, AM33,    {IMM32, EPSW}},
00855 { "and",      0xf90900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00856 { "and",      0xfce00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00857 { "and",      0xfb090000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00858 { "and",      0xfd090000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00859 { "and",      0xfe090000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00860 
00861 { "or",              0xfb1d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00862 { "or",              0xf210,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00863 { "or",              0xf8e400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
00864 { "or",              0xfae40000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM16, DN0}},
00865 { "or",              0xfafd0000,  0xffff0000,  0,    FMT_D2, 0,       {IMM16, PSW}},
00866 { "or",              0xfcfd0000,  0xffff0000,  0,    FMT_D4, AM33,    {IMM32, EPSW}},
00867 { "or",              0xf91900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00868 { "or",              0xfce40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00869 { "or",              0xfb190000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00870 { "or",              0xfd190000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00871 { "or",              0xfe190000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00872 
00873 { "xor",      0xfb2d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00874 { "xor",      0xf220,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00875 { "xor",      0xfae80000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM16, DN0}},
00876 { "xor",      0xf92900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00877 { "xor",      0xfce80000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00878 { "xor",      0xfb290000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00879 { "xor",      0xfd290000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00880 { "xor",      0xfe290000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00881 
00882 { "not",      0xf230,            0xfffc,    0,    FMT_D0, 0,   {DN0}},
00883 { "not",      0xf93900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00884 
00885 { "btst",     0xf8ec00,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
00886 { "btst",     0xfaec0000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM16, DN0}},
00887 { "btst",     0xfcec0000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
00888 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
00889    them to match last since they do not promote.  */
00890 { "btst",     0xfbe90000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00891 { "btst",     0xfde90000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00892 { "btst",     0xfee90000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00893 { "btst",     0xfe820000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
00894 { "btst",     0xfe020000,  0xffff0000,  0,    FMT_D5, 0,       {IMM8E, MEM(IMM32_LOWSHIFT8)}},
00895 { "btst",     0xfaf80000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
00896 
00897 { "bset",     0xf080,            0xfff0,    0,    FMT_D0, 0,   {DM1, MEM(AN0)}},
00898 { "bset",     0xfe800000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
00899 { "bset",     0xfe000000,  0xffff0000,  0,    FMT_D5, 0,       {IMM8E, MEM(IMM32_LOWSHIFT8)}},
00900 { "bset",     0xfaf00000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
00901 
00902 { "bclr",     0xf090,            0xfff0,    0,    FMT_D0, 0,   {DM1, MEM(AN0)}},
00903 { "bclr",     0xfe810000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
00904 { "bclr",     0xfe010000,  0xffff0000,  0,    FMT_D5, 0,       {IMM8E, MEM(IMM32_LOWSHIFT8)}},
00905 { "bclr",     0xfaf40000,  0xfffc0000,  0,    FMT_D2, 0,       {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
00906 
00907 { "asr",      0xfb4d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00908 { "asr",      0xf2b0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00909 { "asr",      0xf8c800,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
00910 { "asr",      0xf94900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00911 { "asr",      0xfb490000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00912 { "asr",      0xfd490000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00913 { "asr",      0xfe490000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00914 { "asr",      0xf8c801,    0xfffcff,    0,    FMT_D1, 0,       {DN0}},
00915 { "asr",      0xfb490001,  0xffff00ff,  0,    FMT_D7, AM33,    {RN02}},
00916 
00917 { "lsr",      0xfb5d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00918 { "lsr",      0xf2a0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00919 { "lsr",      0xf8c400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
00920 { "lsr",      0xf95900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00921 { "lsr",      0xfb590000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
00922 { "lsr",      0xfd590000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00923 { "lsr",      0xfe590000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00924 { "lsr",      0xf8c401,    0xfffcff,    0,    FMT_D1, 0,       {DN0}},
00925 { "lsr",      0xfb590001,  0xffff00ff,  0,    FMT_D7, AM33,    {RN02}},
00926 
00927 { "asl",      0xfb6d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
00928 { "asl",      0xf290,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
00929 { "asl",      0xf8c000,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
00930 { "asl",      0xf96900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
00931 { "asl",      0xfb690000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
00932 { "asl",      0xfd690000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
00933 { "asl",      0xfe690000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
00934 { "asl",      0xf8c001,    0xfffcff,    0,    FMT_D1, 0,       {DN0}},
00935 { "asl",      0xfb690001,  0xffff00ff,  0,    FMT_D7, AM33,    {RN02}},
00936 
00937 { "asl2",     0x54,       0xfc,      0,    FMT_S0, 0,   {DN0}},
00938 { "asl2",     0xf97900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00939 
00940 { "ror",      0xf284,            0xfffc,    0,    FMT_D0, 0,   {DN0}},
00941 { "ror",      0xf98900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00942 
00943 { "rol",      0xf280,            0xfffc,    0,    FMT_D0, 0,   {DN0}},
00944 { "rol",      0xf99900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
00945 
00946 { "beq",      0xc800,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00947 { "bne",      0xc900,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00948 { "bgt",      0xc100,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00949 { "bge",      0xc200,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00950 { "ble",      0xc300,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00951 { "blt",      0xc000,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00952 { "bhi",      0xc500,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00953 { "bcc",      0xc600,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00954 { "bls",      0xc700,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00955 { "bcs",      0xc400,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00956 { "bvc",      0xf8e800,    0xffff00,    0,    FMT_D1, 0,       {SD8N_PCREL}},
00957 { "bvs",      0xf8e900,    0xffff00,    0,    FMT_D1, 0,       {SD8N_PCREL}},
00958 { "bnc",      0xf8ea00,    0xffff00,    0,    FMT_D1, 0,       {SD8N_PCREL}},
00959 { "bns",      0xf8eb00,    0xffff00,    0,    FMT_D1, 0,       {SD8N_PCREL}},
00960 { "bra",      0xca00,            0xff00,    0,    FMT_S1, 0,   {SD8N_PCREL}},
00961 
00962 { "leq",      0xd8,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00963 { "lne",      0xd9,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00964 { "lgt",      0xd1,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00965 { "lge",      0xd2,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00966 { "lle",      0xd3,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00967 { "llt",      0xd0,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00968 { "lhi",      0xd5,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00969 { "lcc",      0xd6,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00970 { "lls",      0xd7,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00971 { "lcs",      0xd4,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00972 { "lra",      0xda,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00973 { "setlb",    0xdb,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
00974 
00975 { "fbeq",     0xf8d000,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00976 { "fbne",     0xf8d100,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00977 { "fbgt",     0xf8d200,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00978 { "fbge",     0xf8d300,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00979 { "fblt",     0xf8d400,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00980 { "fble",     0xf8d500,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00981 { "fbuo",     0xf8d600,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00982 { "fblg",     0xf8d700,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00983 { "fbleg",    0xf8d800,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00984 { "fbug",     0xf8d900,    0xffff00,        0,    FMT_D1, AM33_2,     {SD8N_PCREL}},
00985 { "fbuge",    0xf8da00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
00986 { "fbul",     0xf8db00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
00987 { "fbule",    0xf8dc00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
00988 { "fbue",     0xf8dd00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
00989 
00990 { "fleq",     0xf0d0,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00991 { "flne",     0xf0d1,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00992 { "flgt",     0xf0d2,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00993 { "flge",     0xf0d3,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00994 { "fllt",     0xf0d4,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00995 { "flle",     0xf0d5,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00996 { "fluo",     0xf0d6,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00997 { "fllg",     0xf0d7,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00998 { "flleg",    0xf0d8,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
00999 { "flug",     0xf0d9,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
01000 { "fluge",    0xf0da,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
01001 { "flul",     0xf0db,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
01002 { "flule",    0xf0dc,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
01003 { "flue",     0xf0dd,            0xffff,    0,    FMT_D0, AM33_2,     {UNUSED}},
01004 
01005 { "jmp",      0xf0f4,            0xfffc,    0,    FMT_D0, 0,   {PAREN,AN0,PAREN}},
01006 { "jmp",      0xcc0000,    0xff0000,    0,    FMT_S2, 0,       {IMM16_PCREL}},
01007 { "jmp",      0xdc000000,  0xff000000,  0,    FMT_S4, 0,       {IMM32_HIGH24}},
01008 { "call",     0xcd000000,  0xff000000,  0,    FMT_S4, 0,       {D16_SHIFT,REGS,IMM8E}},
01009 { "call",     0xdd000000,  0xff000000,  0,    FMT_S6, 0,       {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
01010 { "calls",    0xf0f0,            0xfffc,    0,    FMT_D0, 0,   {PAREN,AN0,PAREN}},
01011 { "calls",    0xfaff0000,  0xffff0000,  0,    FMT_D2, 0,       {IMM16_PCREL}},
01012 { "calls",    0xfcff0000,  0xffff0000,  0,    FMT_D4, 0,       {IMM32_PCREL}},
01013 
01014 { "ret",      0xdf0000,    0xff0000,    0,    FMT_S2, 0,       {REGS_SHIFT8, IMM8}},
01015 { "retf",     0xde0000,    0xff0000,    0,    FMT_S2, 0,       {REGS_SHIFT8, IMM8}},
01016 { "rets",     0xf0fc,            0xffff,    0,    FMT_D0, 0,   {UNUSED}},
01017 { "rti",      0xf0fd,            0xffff,    0,    FMT_D0, 0,   {UNUSED}},
01018 { "trap",     0xf0fe,            0xffff,    0,    FMT_D0, 0,   {UNUSED}},
01019 { "rtm",      0xf0ff,            0xffff,    0,    FMT_D0, 0,   {UNUSED}},
01020 { "nop",      0xcb,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
01021 
01022 { "dcpf",     0xf9a600,    0xffff0f,    0,       FMT_D6, AM33_2,  {MEM (RM2)}},
01023 { "dcpf",     0xf9a700,    0xffffff,    0,       FMT_D6, AM33_2,  {MEM (SP)}},
01024 { "dcpf",     0xfba60000,  0xffff00ff,  0,       FMT_D7, AM33_2,  {MEM2 (RI,RM0)}},
01025 { "dcpf",     0xfba70000,  0xffff0f00,  0,       FMT_D7, AM33_2,  {MEM2 (SD8,RM2)}},
01026 { "dcpf",     0xfda70000,  0xffff0f00,  0,    FMT_D8, AM33_2,  {MEM2 (SD24,RM2)}},
01027 { "dcpf",     0xfe460000,  0xffff0f00,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8,RM2)}},
01028 
01029 { "fmov",     0xf92000,    0xfffe00,    0,    FMT_D6, AM33_2,  {MEM (RM2), FSM0}},
01030 { "fmov",     0xf92200,    0xfffe00,    0,    FMT_D6, AM33_2,  {MEMINC (RM2), FSM0}},
01031 { "fmov",     0xf92400,    0xfffef0,    0,    FMT_D6, AM33_2,  {MEM (SP), FSM0}},
01032 { "fmov",     0xf92600,    0xfffe00,    0,    FMT_D6, AM33_2,  {RM2, FSM0}},
01033 { "fmov",     0xf93000,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, MEM (RM0)}},
01034 { "fmov",     0xf93100,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, MEMINC (RM0)}},
01035 { "fmov",     0xf93400,    0xfffd0f,    0,    FMT_D6, AM33_2,  {FSM1, MEM (SP)}},
01036 { "fmov",     0xf93500,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, RM0}},
01037 { "fmov",     0xf94000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
01038 { "fmov",     0xf9a000,    0xfffe01,    0,    FMT_D6, AM33_2,  {MEM (RM2), FDM0}},
01039 { "fmov",     0xf9a200,    0xfffe01,    0,    FMT_D6, AM33_2,  {MEMINC (RM2), FDM0}},
01040 { "fmov",     0xf9a400,    0xfffef1,    0,    FMT_D6, AM33_2,  {MEM (SP), FDM0}},
01041 { "fmov",     0xf9b000,    0xfffd10,    0,    FMT_D6, AM33_2,  {FDM1, MEM (RM0)}},
01042 { "fmov",     0xf9b100,    0xfffd10,    0,    FMT_D6, AM33_2,  {FDM1, MEMINC (RM0)}},
01043 { "fmov",     0xf9b400,    0xfffd1f,    0,    FMT_D6, AM33_2,  {FDM1, MEM (SP)}},
01044 { "fmov",     0xf9b500,    0xffff0f,    0,    FMT_D6, AM33_2,  {RM2, FPCR}},
01045 { "fmov",     0xf9b700,    0xfffff0,    0,    FMT_D6, AM33_2,  {FPCR, RM0}},
01046 { "fmov",     0xf9c000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
01047 { "fmov",     0xfb200000,  0xfffe0000,  0,    FMT_D7, AM33_2,  {MEM2 (SD8, RM2), FSM2}},
01048 { "fmov",     0xfb220000,  0xfffe0000,  0,    FMT_D7, AM33_2,  {MEMINC2 (RM2, SIMM8), FSM2}},
01049 { "fmov",     0xfb240000,  0xfffef000,  0,    FMT_D7, AM33_2,  {MEM2 (IMM8, SP), FSM2}},
01050 { "fmov",     0xfb270000,  0xffff000d,  0,    FMT_D7, AM33_2,  {MEM2 (RI, RM0), FSN1}},
01051 { "fmov",     0xfb300000,  0xfffd0000,  0,    FMT_D7, AM33_2,  {FSM3, MEM2 (SD8, RM0)}},
01052 { "fmov",     0xfb310000,  0xfffd0000,  0,    FMT_D7, AM33_2,  {FSM3, MEMINC2 (RM0, SIMM8)}},
01053 { "fmov",     0xfb340000,  0xfffd0f00,  0,    FMT_D7, AM33_2,  {FSM3, MEM2 (IMM8, SP)}},
01054 { "fmov",     0xfb370000,  0xffff000d,  0,    FMT_D7, AM33_2,  {FSN1, MEM2(RI, RM0)}},
01055   /* FIXME: the spec doesn't say the fd register must be even for the
01056    * next two insns.  Assuming it was a mistake in the spec.  */
01057 { "fmov",     0xfb470000,  0xffff001d,  0,    FMT_D7, AM33_2,  {MEM2 (RI, RM0), FDN1}},
01058 { "fmov",     0xfb570000,  0xffff001d,  0,    FMT_D7, AM33_2,  {FDN1, MEM2(RI, RM0)}},
01059   /* END of FIXME */
01060 { "fmov",     0xfba00000,  0xfffe0100,  0,    FMT_D7, AM33_2,  {MEM2 (SD8, RM2), FDM2}},
01061 { "fmov",     0xfba20000,  0xfffe0100,  0,    FMT_D7, AM33_2,  {MEMINC2 (RM2, SIMM8), FDM2}},
01062 { "fmov",     0xfba40000,  0xfffef100,  0,    FMT_D7, AM33_2,  {MEM2 (IMM8, SP), FDM2}},
01063 { "fmov",     0xfbb00000,  0xfffd1000,  0,    FMT_D7, AM33_2,  {FDM3, MEM2 (SD8, RM0)}},
01064 { "fmov",     0xfbb10000,  0xfffd1000,  0,    FMT_D7, AM33_2,  {FDM3, MEMINC2 (RM0, SIMM8)}},
01065 { "fmov",     0xfbb40000,  0xfffd1f00,  0,    FMT_D7, AM33_2,  {FDM3, MEM2 (IMM8, SP)}},
01066 { "fmov",     0xfd200000,  0xfffe0000,  0,    FMT_D8, AM33_2,  {MEM2 (SIMM24, RM2), FSM2}},
01067 { "fmov",     0xfd220000,  0xfffe0000,  0,    FMT_D8, AM33_2,  {MEMINC2 (RM2, SIMM24), FSM2}},
01068 { "fmov",     0xfd240000,  0xfffef000,  0,    FMT_D8, AM33_2,  {MEM2 (IMM24, SP), FSM2}},
01069 { "fmov",     0xfd300000,  0xfffd0000,  0,    FMT_D8, AM33_2,  {FSM3, MEM2 (SIMM24, RM0)}},
01070 { "fmov",     0xfd310000,  0xfffd0000,  0,    FMT_D8, AM33_2,  {FSM3, MEMINC2 (RM0, SIMM24)}},
01071 { "fmov",     0xfd340000,  0xfffd0f00,  0,    FMT_D8, AM33_2,  {FSM3, MEM2 (IMM24, SP)}},
01072 { "fmov",     0xfda00000,  0xfffe0100,  0,    FMT_D8, AM33_2,  {MEM2 (SIMM24, RM2), FDM2}},
01073 { "fmov",     0xfda20000,  0xfffe0100,  0,    FMT_D8, AM33_2,  {MEMINC2 (RM2, SIMM24), FDM2}},
01074 { "fmov",     0xfda40000,  0xfffef100,  0,    FMT_D8, AM33_2,  {MEM2 (IMM24, SP), FDM2}},
01075 { "fmov",     0xfdb00000,  0xfffd1000,  0,    FMT_D8, AM33_2,  {FDM3, MEM2 (SIMM24, RM0)}},
01076 { "fmov",     0xfdb10000,  0xfffd1000,  0,    FMT_D8, AM33_2,  {FDM3, MEMINC2 (RM0, SIMM24)}},
01077 { "fmov",     0xfdb40000,  0xfffd1f00,  0,    FMT_D8, AM33_2,  {FDM3, MEM2 (IMM24, SP)}},
01078 { "fmov",     0xfdb50000,  0xffff0000,  0,    FMT_D4, AM33_2,  {IMM32, FPCR}},
01079 { "fmov",     0xfe200000,  0xfffe0000,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, RM2), FSM2}},
01080 { "fmov",     0xfe220000,  0xfffe0000,  0,    FMT_D9, AM33_2,  {MEMINC2 (RM2, IMM32_HIGH8), FSM2}},
01081 { "fmov",     0xfe240000,  0xfffef000,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, SP), FSM2}},
01082 { "fmov",     0xfe260000,  0xfffef000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM2}},
01083 { "fmov",     0xfe300000,  0xfffd0000,  0,    FMT_D9, AM33_2,  {FSM3, MEM2 (IMM32_HIGH8, RM0)}},
01084 { "fmov",     0xfe310000,  0xfffd0000,  0,    FMT_D9, AM33_2,  {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}},
01085 { "fmov",     0xfe340000,  0xfffd0f00,  0,    FMT_D9, AM33_2,  {FSM3, MEM2 (IMM32_HIGH8, SP)}},
01086 { "fmov",     0xfe400000,  0xfffe0100,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, RM2), FDM2}},
01087 { "fmov",     0xfe420000,  0xfffe0100,  0,    FMT_D9, AM33_2,  {MEMINC2 (RM2, IMM32_HIGH8), FDM2}},
01088 { "fmov",     0xfe440000,  0xfffef100,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, SP), FDM2}},
01089 { "fmov",     0xfe500000,  0xfffd1000,  0,    FMT_D9, AM33_2,  {FDM3, MEM2 (IMM32_HIGH8, RM0)}},
01090 { "fmov",     0xfe510000,  0xfffd1000,  0,    FMT_D9, AM33_2,  {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}},
01091 { "fmov",     0xfe540000,  0xfffd1f00,  0,    FMT_D9, AM33_2,  {FDM3, MEM2 (IMM32_HIGH8, SP)}},
01092 
01093   /* FIXME: these are documented in the instruction bitmap, but not in
01094    * the instruction manual.  */
01095 { "ftoi",     0xfb400000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
01096 { "itof",     0xfb420000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
01097 { "ftod",     0xfb520000,  0xffff0f15,  0,    FMT_D10,AM33_2,  {FSN3, FDN1}},
01098 { "dtof",     0xfb560000,  0xffff1f05,  0,    FMT_D10,AM33_2,  {FDN3, FSN1}},
01099   /* END of FIXME */
01100 
01101 { "fabs",     0xfb440000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
01102 { "fabs",     0xfbc40000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
01103 { "fabs",     0xf94400,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
01104 { "fabs",     0xf9c400,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
01105 
01106 { "fneg",     0xfb460000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
01107 { "fneg",     0xfbc60000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
01108 { "fneg",     0xf94600,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
01109 { "fneg",     0xf9c600,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
01110 
01111 { "frsqrt",   0xfb500000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
01112 { "frsqrt",   0xfbd00000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
01113 { "frsqrt",   0xf95000,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
01114 { "frsqrt",   0xf9d000,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
01115 
01116   /* FIXME: this is documented in the instruction bitmap, but not in
01117    * the instruction manual.  */
01118 { "fsqrt",    0xfb540000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
01119 { "fsqrt",    0xfbd40000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
01120 { "fsqrt",    0xf95200,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
01121 { "fsqrt",    0xf9d200,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
01122   /* END of FIXME */
01123 
01124 { "fcmp",     0xf95400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
01125 { "fcmp",     0xf9d400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
01126 { "fcmp",     0xfe350000,  0xfffd0f00,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3}},
01127 
01128 { "fadd",     0xfb600000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
01129 { "fadd",     0xfbe00000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
01130 { "fadd",     0xf96000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
01131 { "fadd",     0xf9e000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
01132 { "fadd",     0xfe600000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
01133 
01134 { "fsub",     0xfb640000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
01135 { "fsub",     0xfbe40000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
01136 { "fsub",     0xf96400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
01137 { "fsub",     0xf9e400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
01138 { "fsub",     0xfe640000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
01139 
01140 { "fmul",     0xfb700000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
01141 { "fmul",     0xfbf00000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
01142 { "fmul",     0xf97000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
01143 { "fmul",     0xf9f000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
01144 { "fmul",     0xfe700000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
01145 
01146 { "fdiv",     0xfb740000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
01147 { "fdiv",     0xfbf40000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
01148 { "fdiv",     0xf97400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
01149 { "fdiv",     0xf9f400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
01150 { "fdiv",     0xfe740000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
01151 
01152 { "fmadd",    0xfb800000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
01153 { "fmsub",    0xfb840000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
01154 { "fnmadd",   0xfb900000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
01155 { "fnmsub",   0xfb940000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
01156 
01157 /* UDF instructions.  */
01158 { "udf00",    0xf600,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01159 { "udf00",    0xf90000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01160 { "udf00",    0xfb000000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01161 { "udf00",    0xfd000000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01162 { "udf01",    0xf610,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01163 { "udf01",    0xf91000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01164 { "udf01",    0xfb100000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01165 { "udf01",    0xfd100000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01166 { "udf02",    0xf620,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01167 { "udf02",    0xf92000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01168 { "udf02",    0xfb200000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01169 { "udf02",    0xfd200000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01170 { "udf03",    0xf630,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01171 { "udf03",    0xf93000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01172 { "udf03",    0xfb300000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01173 { "udf03",    0xfd300000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01174 { "udf04",    0xf640,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01175 { "udf04",    0xf94000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01176 { "udf04",    0xfb400000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01177 { "udf04",    0xfd400000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01178 { "udf05",    0xf650,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01179 { "udf05",    0xf95000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01180 { "udf05",    0xfb500000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01181 { "udf05",    0xfd500000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01182 { "udf06",    0xf660,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01183 { "udf06",    0xf96000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01184 { "udf06",    0xfb600000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01185 { "udf06",    0xfd600000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01186 { "udf07",    0xf670,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01187 { "udf07",    0xf97000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01188 { "udf07",    0xfb700000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01189 { "udf07",    0xfd700000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01190 { "udf08",    0xf680,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01191 { "udf08",    0xf98000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01192 { "udf08",    0xfb800000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01193 { "udf08",    0xfd800000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01194 { "udf09",    0xf690,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01195 { "udf09",    0xf99000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01196 { "udf09",    0xfb900000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01197 { "udf09",    0xfd900000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01198 { "udf10",    0xf6a0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01199 { "udf10",    0xf9a000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01200 { "udf10",    0xfba00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01201 { "udf10",    0xfda00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01202 { "udf11",    0xf6b0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01203 { "udf11",    0xf9b000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01204 { "udf11",    0xfbb00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01205 { "udf11",    0xfdb00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01206 { "udf12",    0xf6c0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01207 { "udf12",    0xf9c000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01208 { "udf12",    0xfbc00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01209 { "udf12",    0xfdc00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01210 { "udf13",    0xf6d0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01211 { "udf13",    0xf9d000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01212 { "udf13",    0xfbd00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01213 { "udf13",    0xfdd00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01214 { "udf14",    0xf6e0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01215 { "udf14",    0xf9e000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01216 { "udf14",    0xfbe00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01217 { "udf14",    0xfde00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01218 { "udf15",    0xf6f0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01219 { "udf15",    0xf9f000,    0xfffc00,    0,    FMT_D1, 0,       {SIMM8, DN0}},
01220 { "udf15",    0xfbf00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
01221 { "udf15",    0xfdf00000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01222 { "udf20",    0xf500,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01223 { "udf21",    0xf510,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01224 { "udf22",    0xf520,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01225 { "udf23",    0xf530,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01226 { "udf24",    0xf540,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01227 { "udf25",    0xf550,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01228 { "udf26",    0xf560,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01229 { "udf27",    0xf570,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01230 { "udf28",    0xf580,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01231 { "udf29",    0xf590,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01232 { "udf30",    0xf5a0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01233 { "udf31",    0xf5b0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01234 { "udf32",    0xf5c0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01235 { "udf33",    0xf5d0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01236 { "udf34",    0xf5e0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01237 { "udf35",    0xf5f0,            0xfff0,    0,    FMT_D0, 0,   {DM1, DN0}},
01238 { "udfu00",   0xf90400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01239 { "udfu00",   0xfb040000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01240 { "udfu00",   0xfd040000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01241 { "udfu01",   0xf91400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01242 { "udfu01",   0xfb140000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01243 { "udfu01",   0xfd140000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01244 { "udfu02",   0xf92400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01245 { "udfu02",   0xfb240000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01246 { "udfu02",   0xfd240000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01247 { "udfu03",   0xf93400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01248 { "udfu03",   0xfb340000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01249 { "udfu03",   0xfd340000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01250 { "udfu04",   0xf94400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01251 { "udfu04",   0xfb440000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01252 { "udfu04",   0xfd440000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01253 { "udfu05",   0xf95400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01254 { "udfu05",   0xfb540000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01255 { "udfu05",   0xfd540000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01256 { "udfu06",   0xf96400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01257 { "udfu06",   0xfb640000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01258 { "udfu06",   0xfd640000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01259 { "udfu07",   0xf97400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01260 { "udfu07",   0xfb740000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01261 { "udfu07",   0xfd740000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01262 { "udfu08",   0xf98400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01263 { "udfu08",   0xfb840000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01264 { "udfu08",   0xfd840000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01265 { "udfu09",   0xf99400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01266 { "udfu09",   0xfb940000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01267 { "udfu09",   0xfd940000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01268 { "udfu10",   0xf9a400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01269 { "udfu10",   0xfba40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01270 { "udfu10",   0xfda40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01271 { "udfu11",   0xf9b400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01272 { "udfu11",   0xfbb40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01273 { "udfu11",   0xfdb40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01274 { "udfu12",   0xf9c400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01275 { "udfu12",   0xfbc40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01276 { "udfu12",   0xfdc40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01277 { "udfu13",   0xf9d400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01278 { "udfu13",   0xfbd40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01279 { "udfu13",   0xfdd40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01280 { "udfu14",   0xf9e400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01281 { "udfu14",   0xfbe40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01282 { "udfu14",   0xfde40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01283 { "udfu15",   0xf9f400,    0xfffc00,    0,    FMT_D1, 0,       {IMM8, DN0}},
01284 { "udfu15",   0xfbf40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
01285 { "udfu15",   0xfdf40000,  0xfffc0000,  0,    FMT_D4, 0,       {IMM32, DN0}},
01286 
01287 { "putx",     0xf500,            0xfff0,    0,    FMT_D0, AM30,       {DN01}},
01288 { "getx",     0xf6f0,            0xfff0,    0,    FMT_D0, AM30,       {DN01}},
01289 { "mulq",     0xf600,            0xfff0,    0,    FMT_D0, AM30,       {DM1, DN0}},
01290 { "mulq",     0xf90000,    0xfffc00,    0,    FMT_D1, AM30,    {SIMM8, DN0}},
01291 { "mulq",     0xfb000000,  0xfffc0000,  0,    FMT_D2, AM30,    {SIMM16, DN0}},
01292 { "mulq",     0xfd000000,  0xfffc0000,  0,    FMT_D4, AM30,    {IMM32, DN0}},
01293 { "mulqu",    0xf610,            0xfff0,    0,    FMT_D0, AM30,       {DM1, DN0}},
01294 { "mulqu",    0xf91400,    0xfffc00,    0,    FMT_D1, AM30,    {SIMM8, DN0}},
01295 { "mulqu",    0xfb140000,  0xfffc0000,  0,    FMT_D2, AM30,    {SIMM16, DN0}},
01296 { "mulqu",    0xfd140000,  0xfffc0000,  0,    FMT_D4, AM30,    {IMM32, DN0}},
01297 { "sat16",    0xf640,            0xfff0,    0,    FMT_D0, AM30,       {DM1, DN0}},
01298 { "sat16",    0xf9ab00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
01299 
01300 { "sat24",    0xf650,            0xfff0,    0,    FMT_D0, AM30,       {DM1, DN0}},
01301 { "sat24",    0xfbaf0000,  0xffff00ff,  0,    FMT_D7, AM33,    {RM2, RN0}},
01302 
01303 { "bsch",     0xfbff0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
01304 { "bsch",     0xf670,            0xfff0,    0,    FMT_D0, AM30,       {DM1, DN0}},
01305 { "bsch",     0xf9fb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
01306 
01307 /* Extension.  We need some instruction to trigger "emulated syscalls"
01308    for our simulator.  */
01309 { "syscall",  0xf0e0,            0xfff0,    0,    FMT_D0, AM33,       {IMM4}},
01310 { "syscall",    0xf0c0,      0xffff,      0,    FMT_D0, 0,     {UNUSED}},
01311 
01312 /* Extension.  When talking to the simulator, gdb requires some instruction
01313    that will trigger a "breakpoint" (really just an instruction that isn't
01314    otherwise used by the tools.  This instruction must be the same size
01315    as the smallest instruction on the target machine.  In the case of the
01316    mn10x00 the "break" instruction must be one byte.  0xff is available on
01317    both mn10x00 architectures.  */
01318 { "break",    0xff,       0xff,      0,    FMT_S0, 0,   {UNUSED}},
01319 
01320 { "add_add",  0xf7000000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01321 { "add_add",  0xf7100000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01322 { "add_add",  0xf7040000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01323 { "add_add",  0xf7140000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01324 { "add_sub",  0xf7200000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01325 { "add_sub",  0xf7300000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01326 { "add_sub",  0xf7240000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01327 { "add_sub",  0xf7340000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01328 { "add_cmp",  0xf7400000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01329 { "add_cmp",  0xf7500000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01330 { "add_cmp",  0xf7440000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01331 { "add_cmp",  0xf7540000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01332 { "add_mov",  0xf7600000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01333 { "add_mov",  0xf7700000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01334 { "add_mov",  0xf7640000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01335 { "add_mov",  0xf7740000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01336 { "add_asr",  0xf7800000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01337 { "add_asr",  0xf7900000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01338 { "add_asr",  0xf7840000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01339 { "add_asr",  0xf7940000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01340 { "add_lsr",  0xf7a00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01341 { "add_lsr",  0xf7b00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01342 { "add_lsr",  0xf7a40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01343 { "add_lsr",  0xf7b40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01344 { "add_asl",  0xf7c00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01345 { "add_asl",  0xf7d00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01346 { "add_asl",  0xf7c40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01347 { "add_asl",  0xf7d40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01348 { "cmp_add",  0xf7010000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01349 { "cmp_add",  0xf7110000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01350 { "cmp_add",  0xf7050000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01351 { "cmp_add",  0xf7150000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01352 { "cmp_sub",  0xf7210000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01353 { "cmp_sub",  0xf7310000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01354 { "cmp_sub",  0xf7250000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01355 { "cmp_sub",  0xf7350000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01356 { "cmp_mov",  0xf7610000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01357 { "cmp_mov",  0xf7710000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01358 { "cmp_mov",  0xf7650000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01359 { "cmp_mov",  0xf7750000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01360 { "cmp_asr",  0xf7810000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01361 { "cmp_asr",  0xf7910000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01362 { "cmp_asr",  0xf7850000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01363 { "cmp_asr",  0xf7950000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01364 { "cmp_lsr",  0xf7a10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01365 { "cmp_lsr",  0xf7b10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01366 { "cmp_lsr",  0xf7a50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01367 { "cmp_lsr",  0xf7b50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01368 { "cmp_asl",  0xf7c10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01369 { "cmp_asl",  0xf7d10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01370 { "cmp_asl",  0xf7c50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01371 { "cmp_asl",  0xf7d50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01372 { "sub_add",  0xf7020000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01373 { "sub_add",  0xf7120000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01374 { "sub_add",  0xf7060000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01375 { "sub_add",  0xf7160000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01376 { "sub_sub",  0xf7220000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01377 { "sub_sub",  0xf7320000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01378 { "sub_sub",  0xf7260000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01379 { "sub_sub",  0xf7360000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01380 { "sub_cmp",  0xf7420000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01381 { "sub_cmp",  0xf7520000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01382 { "sub_cmp",  0xf7460000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01383 { "sub_cmp",  0xf7560000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01384 { "sub_mov",  0xf7620000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01385 { "sub_mov",  0xf7720000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01386 { "sub_mov",  0xf7660000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01387 { "sub_mov",  0xf7760000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01388 { "sub_asr",  0xf7820000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01389 { "sub_asr",  0xf7920000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01390 { "sub_asr",  0xf7860000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01391 { "sub_asr",  0xf7960000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01392 { "sub_lsr",  0xf7a20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01393 { "sub_lsr",  0xf7b20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01394 { "sub_lsr",  0xf7a60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01395 { "sub_lsr",  0xf7b60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01396 { "sub_asl",  0xf7c20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01397 { "sub_asl",  0xf7d20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01398 { "sub_asl",  0xf7c60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01399 { "sub_asl",  0xf7d60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01400 { "mov_add",  0xf7030000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01401 { "mov_add",  0xf7130000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01402 { "mov_add",  0xf7070000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01403 { "mov_add",  0xf7170000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01404 { "mov_sub",  0xf7230000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01405 { "mov_sub",  0xf7330000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01406 { "mov_sub",  0xf7270000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01407 { "mov_sub",  0xf7370000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01408 { "mov_cmp",  0xf7430000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01409 { "mov_cmp",  0xf7530000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01410 { "mov_cmp",  0xf7470000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01411 { "mov_cmp",  0xf7570000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01412 { "mov_mov",  0xf7630000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01413 { "mov_mov",  0xf7730000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01414 { "mov_mov",  0xf7670000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01415 { "mov_mov",  0xf7770000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, SIMM4_2, RN0}},
01416 { "mov_asr",  0xf7830000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01417 { "mov_asr",  0xf7930000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01418 { "mov_asr",  0xf7870000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01419 { "mov_asr",  0xf7970000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01420 { "mov_lsr",  0xf7a30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01421 { "mov_lsr",  0xf7b30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01422 { "mov_lsr",  0xf7a70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01423 { "mov_lsr",  0xf7b70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01424 { "mov_asl",  0xf7c30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01425 { "mov_asl",  0xf7d30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01426 { "mov_asl",  0xf7c70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, RM2, RN0}},
01427 { "mov_asl",  0xf7d70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_6, RN4, IMM4_2, RN0}},
01428 { "and_add",  0xf7080000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01429 { "and_add",  0xf7180000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01430 { "and_sub",  0xf7280000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01431 { "and_sub",  0xf7380000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01432 { "and_cmp",  0xf7480000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01433 { "and_cmp",  0xf7580000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01434 { "and_mov",  0xf7680000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01435 { "and_mov",  0xf7780000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01436 { "and_asr",  0xf7880000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01437 { "and_asr",  0xf7980000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01438 { "and_lsr",  0xf7a80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01439 { "and_lsr",  0xf7b80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01440 { "and_asl",  0xf7c80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01441 { "and_asl",  0xf7d80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01442 { "dmach_add",       0xf7090000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01443 { "dmach_add",       0xf7190000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01444 { "dmach_sub",       0xf7290000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01445 { "dmach_sub",       0xf7390000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01446 { "dmach_cmp",       0xf7490000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01447 { "dmach_cmp",       0xf7590000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01448 { "dmach_mov",       0xf7690000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01449 { "dmach_mov",       0xf7790000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01450 { "dmach_asr",       0xf7890000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01451 { "dmach_asr",       0xf7990000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01452 { "dmach_lsr",       0xf7a90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01453 { "dmach_lsr",       0xf7b90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01454 { "dmach_asl",       0xf7c90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01455 { "dmach_asl",       0xf7d90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01456 { "xor_add",  0xf70a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01457 { "xor_add",  0xf71a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01458 { "xor_sub",  0xf72a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01459 { "xor_sub",  0xf73a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01460 { "xor_cmp",  0xf74a0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01461 { "xor_cmp",  0xf75a0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01462 { "xor_mov",  0xf76a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01463 { "xor_mov",  0xf77a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01464 { "xor_asr",  0xf78a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01465 { "xor_asr",  0xf79a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01466 { "xor_lsr",  0xf7aa0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01467 { "xor_lsr",  0xf7ba0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01468 { "xor_asl",  0xf7ca0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01469 { "xor_asl",  0xf7da0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01470 { "swhw_add", 0xf70b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01471 { "swhw_add", 0xf71b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01472 { "swhw_sub", 0xf72b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01473 { "swhw_sub", 0xf73b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01474 { "swhw_cmp", 0xf74b0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01475 { "swhw_cmp", 0xf75b0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01476 { "swhw_mov", 0xf76b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01477 { "swhw_mov", 0xf77b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01478 { "swhw_asr", 0xf78b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01479 { "swhw_asr", 0xf79b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01480 { "swhw_lsr", 0xf7ab0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01481 { "swhw_lsr", 0xf7bb0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01482 { "swhw_asl", 0xf7cb0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01483 { "swhw_asl", 0xf7db0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01484 { "or_add",   0xf70c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01485 { "or_add",   0xf71c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01486 { "or_sub",   0xf72c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01487 { "or_sub",   0xf73c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01488 { "or_cmp",   0xf74c0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01489 { "or_cmp",   0xf75c0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01490 { "or_mov",   0xf76c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01491 { "or_mov",   0xf77c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01492 { "or_asr",   0xf78c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01493 { "or_asr",   0xf79c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01494 { "or_lsr",   0xf7ac0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01495 { "or_lsr",   0xf7bc0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01496 { "or_asl",   0xf7cc0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01497 { "or_asl",   0xf7dc0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01498 { "sat16_add",       0xf70d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01499 { "sat16_add",       0xf71d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01500 { "sat16_sub",       0xf72d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01501 { "sat16_sub",       0xf73d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01502 { "sat16_cmp",       0xf74d0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01503 { "sat16_cmp",       0xf75d0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01504 { "sat16_mov",       0xf76d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01505 { "sat16_mov",       0xf77d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, SIMM4_2, RN0}},
01506 { "sat16_asr",       0xf78d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01507 { "sat16_asr",       0xf79d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01508 { "sat16_lsr",       0xf7ad0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01509 { "sat16_lsr",       0xf7bd0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01510 { "sat16_asl",       0xf7cd0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, RM2, RN0}},
01511 { "sat16_asl",       0xf7dd0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM6, RN4, IMM4_2, RN0}},
01512 /* Ugh.  Synthetic instructions.  */
01513 { "add_and",  0xf7080000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01514 { "add_and",  0xf7180000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01515 { "add_dmach",       0xf7090000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01516 { "add_dmach",       0xf7190000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01517 { "add_or",   0xf70c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01518 { "add_or",   0xf71c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01519 { "add_sat16",       0xf70d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01520 { "add_sat16",       0xf71d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01521 { "add_swhw", 0xf70b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01522 { "add_swhw", 0xf71b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01523 { "add_xor",  0xf70a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01524 { "add_xor",  0xf71a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01525 { "asl_add",  0xf7c00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01526 { "asl_add",  0xf7d00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01527 { "asl_add",  0xf7c40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01528 { "asl_add",  0xf7d40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01529 { "asl_and",  0xf7c80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01530 { "asl_and",  0xf7d80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01531 { "asl_cmp",  0xf7c10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01532 { "asl_cmp",  0xf7d10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4, }},
01533 { "asl_cmp",  0xf7c50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01534 { "asl_cmp",  0xf7d50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01535 { "asl_dmach",       0xf7c90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01536 { "asl_dmach",       0xf7d90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01537 { "asl_mov",  0xf7c30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01538 { "asl_mov",  0xf7d30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01539 { "asl_mov",  0xf7c70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01540 { "asl_mov",  0xf7d70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01541 { "asl_or",   0xf7cc0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01542 { "asl_or",   0xf7dc0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01543 { "asl_sat16",       0xf7cd0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01544 { "asl_sat16",       0xf7dd0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01545 { "asl_sub",  0xf7c20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01546 { "asl_sub",  0xf7d20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01547 { "asl_sub",  0xf7c60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01548 { "asl_sub",  0xf7d60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01549 { "asl_swhw", 0xf7cb0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01550 { "asl_swhw", 0xf7db0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01551 { "asl_xor",  0xf7ca0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01552 { "asl_xor",  0xf7da0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01553 { "asr_add",  0xf7800000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01554 { "asr_add",  0xf7900000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01555 { "asr_add",  0xf7840000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01556 { "asr_add",  0xf7940000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01557 { "asr_and",  0xf7880000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01558 { "asr_and",  0xf7980000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01559 { "asr_cmp",  0xf7810000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01560 { "asr_cmp",  0xf7910000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4, }},
01561 { "asr_cmp",  0xf7850000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01562 { "asr_cmp",  0xf7950000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01563 { "asr_dmach",       0xf7890000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01564 { "asr_dmach",       0xf7990000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01565 { "asr_mov",  0xf7830000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01566 { "asr_mov",  0xf7930000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01567 { "asr_mov",  0xf7870000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01568 { "asr_mov",  0xf7970000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01569 { "asr_or",   0xf78c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01570 { "asr_or",   0xf79c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01571 { "asr_sat16",       0xf78d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01572 { "asr_sat16",       0xf79d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01573 { "asr_sub",  0xf7820000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01574 { "asr_sub",  0xf7920000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01575 { "asr_sub",  0xf7860000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01576 { "asr_sub",  0xf7960000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01577 { "asr_swhw", 0xf78b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01578 { "asr_swhw", 0xf79b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01579 { "asr_xor",  0xf78a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01580 { "asr_xor",  0xf79a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01581 { "cmp_and",  0xf7480000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01582 { "cmp_and",  0xf7580000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01583 { "cmp_dmach",       0xf7490000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01584 { "cmp_dmach",       0xf7590000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01585 { "cmp_or",   0xf74c0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01586 { "cmp_or",   0xf75c0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01587 { "cmp_sat16",       0xf74d0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01588 { "cmp_sat16",       0xf75d0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01589 { "cmp_swhw", 0xf74b0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01590 { "cmp_swhw", 0xf75b0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01591 { "cmp_xor",  0xf74a0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01592 { "cmp_xor",  0xf75a0000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01593 { "lsr_add",  0xf7a00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01594 { "lsr_add",  0xf7b00000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01595 { "lsr_add",  0xf7a40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01596 { "lsr_add",  0xf7b40000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01597 { "lsr_and",  0xf7a80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01598 { "lsr_and",  0xf7b80000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01599 { "lsr_cmp",  0xf7a10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01600 { "lsr_cmp",  0xf7b10000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4, }},
01601 { "lsr_cmp",  0xf7a50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01602 { "lsr_cmp",  0xf7b50000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01603 { "lsr_dmach",       0xf7a90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01604 { "lsr_dmach",       0xf7b90000,  0xffff0000,  0x0,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01605 { "lsr_mov",  0xf7a30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01606 { "lsr_mov",  0xf7b30000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01607 { "lsr_mov",  0xf7a70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01608 { "lsr_mov",  0xf7b70000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01609 { "lsr_or",   0xf7ac0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01610 { "lsr_or",   0xf7bc0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01611 { "lsr_sat16",       0xf7ad0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01612 { "lsr_sat16",       0xf7bd0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01613 { "lsr_sub",  0xf7a20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01614 { "lsr_sub",  0xf7b20000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01615 { "lsr_sub",  0xf7a60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, SIMM4_6, RN4}},
01616 { "lsr_sub",  0xf7b60000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, SIMM4_6, RN4}},
01617 { "lsr_swhw", 0xf7ab0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01618 { "lsr_swhw", 0xf7bb0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01619 { "lsr_xor",  0xf7aa0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01620 { "lsr_xor",  0xf7ba0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {IMM4_2, RN0, RM6, RN4}},
01621 { "mov_and",  0xf7680000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01622 { "mov_and",  0xf7780000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01623 { "mov_dmach",       0xf7690000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01624 { "mov_dmach",       0xf7790000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01625 { "mov_or",   0xf76c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01626 { "mov_or",   0xf77c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01627 { "mov_sat16",       0xf76d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01628 { "mov_sat16",       0xf77d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01629 { "mov_swhw", 0xf76b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01630 { "mov_swhw", 0xf77b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01631 { "mov_xor",  0xf76a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01632 { "mov_xor",  0xf77a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01633 { "sub_and",  0xf7280000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01634 { "sub_and",  0xf7380000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01635 { "sub_dmach",       0xf7290000,  0xffff0000,  0x0,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01636 { "sub_dmach",       0xf7390000,  0xffff0000,  0x0,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01637 { "sub_or",   0xf72c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01638 { "sub_or",   0xf73c0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01639 { "sub_sat16",       0xf72d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01640 { "sub_sat16",       0xf73d0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01641 { "sub_swhw", 0xf72b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01642 { "sub_swhw", 0xf73b0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01643 { "sub_xor",  0xf72a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {RM2, RN0, RM6, RN4}},
01644 { "sub_xor",  0xf73a0000,  0xffff0000,  0xa,  FMT_D10, AM33,    {SIMM4_2, RN0, RM6, RN4}},
01645 { "mov_llt",  0xf7e00000,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01646 { "mov_lgt",  0xf7e00001,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01647 { "mov_lge",  0xf7e00002,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01648 { "mov_lle",  0xf7e00003,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01649 { "mov_lcs",  0xf7e00004,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01650 { "mov_lhi",  0xf7e00005,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01651 { "mov_lcc",  0xf7e00006,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01652 { "mov_lls",  0xf7e00007,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01653 { "mov_leq",  0xf7e00008,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01654 { "mov_lne",  0xf7e00009,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01655 { "mov_lra",  0xf7e0000a,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01656 { "llt_mov",  0xf7e00000,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01657 { "lgt_mov",  0xf7e00001,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01658 { "lge_mov",  0xf7e00002,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01659 { "lle_mov",  0xf7e00003,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01660 { "lcs_mov",  0xf7e00004,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01661 { "lhi_mov",  0xf7e00005,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01662 { "lcc_mov",  0xf7e00006,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01663 { "lls_mov",  0xf7e00007,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01664 { "leq_mov",  0xf7e00008,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01665 { "lne_mov",  0xf7e00009,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01666 { "lra_mov",  0xf7e0000a,  0xffff000f,  0x22, FMT_D10, AM33,    {MEMINC2 (RN4,SIMM4_2), RM6}},
01667  
01668 { 0, 0, 0, 0, 0, 0, {0}},
01669 
01670 } ;
01671 
01672 const int mn10300_num_opcodes =
01673   sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
01674 
01675