Back to index

cell-binutils  2.17cvs20070401
m10200-opc.c
Go to the documentation of this file.
00001 /* Assemble Matsushita MN10200 instructions.
00002    Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
00003 
00004 This program is free software; you can redistribute it and/or modify
00005 it under the terms of the GNU General Public License as published by
00006 the Free Software Foundation; either version 2 of the License, or
00007 (at your option) any later version.
00008 
00009 This program is distributed in the hope that it will be useful,
00010 but WITHOUT ANY WARRANTY; without even the implied warranty of
00011 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012 GNU General Public License for more details.
00013 
00014 You should have received a copy of the GNU General Public License
00015 along with this program; if not, write to the Free Software
00016 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00017 
00018 #include "sysdep.h"
00019 #include "opcode/mn10200.h"
00020 
00021 
00022 const struct mn10200_operand mn10200_operands[] = {
00023 #define UNUSED       0
00024   {0, 0, 0}, 
00025 
00026 /* dn register in the first register operand position.  */
00027 #define DN0      (UNUSED+1)
00028   {2, 0, MN10200_OPERAND_DREG},
00029 
00030 /* dn register in the second register operand position.  */
00031 #define DN1      (DN0+1)
00032   {2, 2, MN10200_OPERAND_DREG},
00033 
00034 /* dm register in the first register operand position.  */
00035 #define DM0      (DN1+1)
00036   {2, 0, MN10200_OPERAND_DREG},
00037 
00038 /* dm register in the second register operand position.  */
00039 #define DM1      (DM0+1)
00040   {2, 2, MN10200_OPERAND_DREG},
00041 
00042 /* an register in the first register operand position.  */
00043 #define AN0      (DM1+1)
00044   {2, 0, MN10200_OPERAND_AREG},
00045 
00046 /* an register in the second register operand position.  */
00047 #define AN1      (AN0+1)
00048   {2, 2, MN10200_OPERAND_AREG},
00049 
00050 /* am register in the first register operand position.  */
00051 #define AM0      (AN1+1)
00052   {2, 0, MN10200_OPERAND_AREG},
00053 
00054 /* am register in the second register operand position.  */
00055 #define AM1      (AM0+1)
00056   {2, 2, MN10200_OPERAND_AREG},
00057 
00058 /* 8 bit unsigned immediate which may promote to a 16bit
00059    unsigned immediate.  */
00060 #define IMM8    (AM1+1)
00061   {8, 0, MN10200_OPERAND_PROMOTE},
00062 
00063 /* 16 bit unsigned immediate which may promote to a 32bit
00064    unsigned immediate.  */
00065 #define IMM16    (IMM8+1)
00066   {16, 0, MN10200_OPERAND_PROMOTE},
00067 
00068 /* 16 bit pc-relative immediate which may promote to a 16bit
00069    pc-relative immediate.  */
00070 #define IMM16_PCREL    (IMM16+1)
00071   {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED},
00072 
00073 /* 16bit unsigned dispacement in a memory operation which
00074    may promote to a 32bit displacement.  */
00075 #define IMM16_MEM    (IMM16_PCREL+1)
00076   {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},
00077 
00078 /* 24 immediate, low 16 bits in the main instruction
00079    word, 8 in the extension word.  */
00080 
00081 #define IMM24    (IMM16_MEM+1)
00082   {24, 0, MN10200_OPERAND_EXTENDED},
00083 
00084 /* 32bit pc-relative offset.  */
00085 #define IMM24_PCREL    (IMM24+1)
00086   {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED},
00087 
00088 /* 32bit memory offset.  */
00089 #define IMM24_MEM    (IMM24_PCREL+1)
00090   {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},
00091 
00092 /* Processor status word.  */
00093 #define PSW    (IMM24_MEM+1)
00094   {0, 0, MN10200_OPERAND_PSW},
00095 
00096 /* MDR register.  */
00097 #define MDR    (PSW+1)
00098   {0, 0, MN10200_OPERAND_MDR},
00099 
00100 /* Index register.  */
00101 #define DI (MDR+1)
00102   {2, 4, MN10200_OPERAND_DREG},
00103 
00104 /* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
00105 #define SD8    (DI+1)
00106   {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
00107 
00108 /* 16 bit signed displacement, may promote to 32bit dispacement.  */
00109 #define SD16    (SD8+1)
00110   {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
00111 
00112 /* 8 bit pc-relative displacement.  */
00113 #define SD8N_PCREL    (SD16+1)
00114   {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX},
00115 
00116 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
00117 #define SIMM8    (SD8N_PCREL+1)
00118   {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
00119 
00120 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
00121 #define SIMM16    (SIMM8+1)
00122   {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
00123 
00124 /* 16 bit signed immediate which may not promote.  */
00125 #define SIMM16N    (SIMM16+1)
00126   {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK},
00127 
00128 /* Either an open paren or close paren.  */
00129 #define PAREN (SIMM16N+1)
00130   {0, 0, MN10200_OPERAND_PAREN}, 
00131 
00132 /* dn register that appears in the first and second register positions.  */
00133 #define DN01     (PAREN+1)
00134   {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},
00135 
00136 /* an register that appears in the first and second register positions.  */
00137 #define AN01     (DN01+1)
00138   {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
00139 } ; 
00140 
00141 #define MEM(ADDR) PAREN, ADDR, PAREN 
00142 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
00143 
00144 /* The opcode table.
00145 
00146    The format of the opcode table is:
00147 
00148    NAME              OPCODE        MASK          { OPERANDS }
00149 
00150    NAME is the name of the instruction.
00151    OPCODE is the instruction opcode.
00152    MASK is the opcode mask; this is used to tell the disassembler
00153      which bits in the actual opcode must match OPCODE.
00154    OPERANDS is the list of operands.
00155 
00156    The disassembler reads the table in order and prints the first
00157    instruction which matches, so this table is sorted to put more
00158    specific instructions before more general instructions.  It is also
00159    sorted by major opcode.  */
00160 
00161 const struct mn10200_opcode mn10200_opcodes[] = {
00162 { "mov",      0x8000,              0xf000,              FMT_2, {SIMM8, DN01}},
00163 { "mov",      0x80,         0xf0,         FMT_1, {DN1, DM0}},
00164 { "mov",      0xf230,              0xfff0,              FMT_4, {DM1, AN0}},
00165 { "mov",      0xf2f0,              0xfff0,              FMT_4, {AN1, DM0}},
00166 { "mov",      0xf270,              0xfff0,              FMT_4, {AN1, AM0}},
00167 { "mov",      0xf3f0,              0xfffc,              FMT_4, {PSW, DN0}},
00168 { "mov",      0xf3d0,              0xfff3,              FMT_4, {DN1, PSW}},
00169 { "mov",      0xf3e0,              0xfffc,              FMT_4, {MDR, DN0}},
00170 { "mov",      0xf3c0,              0xfff3,              FMT_4, {DN1, MDR}},
00171 { "mov",      0x20,         0xf0,         FMT_1, {MEM(AN1), DM0}},
00172 { "mov",      0x6000,              0xf000,              FMT_2, {MEM2(SD8, AN1), DM0}},
00173 { "mov",      0xf7c00000,   0xfff00000,   FMT_6, {MEM2(SD16, AN1), DM0}},
00174 { "mov",      0xf4800000,   0xfff00000,   FMT_7, {MEM2(IMM24,AN1), DM0}},
00175 { "mov",      0xf140,              0xffc0,              FMT_4, {MEM2(DI, AN1), DM0}},
00176 { "mov",      0xc80000,     0xfc0000,     FMT_3, {MEM(IMM16_MEM), DN0}},
00177 { "mov",      0xf4c00000,   0xfffc0000,   FMT_7, {MEM(IMM24_MEM), DN0}},
00178 { "mov",      0x7000,              0xf000,              FMT_2, {MEM2(SD8,AN1), AM0}},
00179 { "mov",      0x7000,              0xf000,              FMT_2, {MEM(AN1), AM0}},
00180 { "mov",      0xf7b00000,   0xfff00000,   FMT_6, {MEM2(SD16, AN1), AM0}},
00181 { "mov",      0xf4f00000,   0xfff00000,   FMT_7, {MEM2(IMM24,AN1), AM0}},
00182 { "mov",      0xf100,              0xffc0,              FMT_4, {MEM2(DI, AN1), AM0}},
00183 { "mov",      0xf7300000,   0xfffc0000,   FMT_6, {MEM(IMM16_MEM), AN0}},
00184 { "mov",      0xf4d00000,   0xfffc0000,   FMT_7, {MEM(IMM24_MEM), AN0}},
00185 { "mov",      0x00,         0xf0,         FMT_1, {DM0, MEM(AN1)}},
00186 { "mov",      0x4000,              0xf000,              FMT_2, {DM0, MEM2(SD8, AN1)}},
00187 { "mov",      0xf7800000,   0xfff00000,   FMT_6, {DM0, MEM2(SD16, AN1)}},
00188 { "mov",      0xf4000000,   0xfff00000,   FMT_7, {DM0, MEM2(IMM24, AN1)}},
00189 { "mov",      0xf1c0,              0xffc0,              FMT_4, {DM0, MEM2(DI, AN1)}},
00190 { "mov",      0xc00000,     0xfc0000,     FMT_3, {DN0, MEM(IMM16_MEM)}},
00191 { "mov",      0xf4400000,   0xfffc0000,   FMT_7, {DN0, MEM(IMM24_MEM)}},
00192 { "mov",      0x5000,              0xf000,              FMT_2, {AM0, MEM2(SD8, AN1)}},
00193 { "mov",      0x5000,              0xf000,              FMT_2, {AM0, MEM(AN1)}},
00194 { "mov",      0xf7a00000,   0xfff00000,   FMT_6, {AM0, MEM2(SD16, AN1)}},
00195 { "mov",      0xf4100000,   0xfff00000,   FMT_7, {AM0, MEM2(IMM24,AN1)}},
00196 { "mov",      0xf180,              0xffc0,              FMT_4, {AM0, MEM2(DI, AN1)}},
00197 { "mov",      0xf7200000,   0xfffc0000,   FMT_6, {AN0, MEM(IMM16_MEM)}},
00198 { "mov",      0xf4500000,   0xfffc0000,   FMT_7, {AN0, MEM(IMM24_MEM)}},
00199 { "mov",      0xf80000,     0xfc0000,     FMT_3, {SIMM16, DN0}},
00200 { "mov",      0xf4700000,   0xfffc0000,   FMT_7, {IMM24, DN0}},
00201 { "mov",      0xdc0000,     0xfc0000,     FMT_3, {IMM16, AN0}},
00202 { "mov",      0xf4740000,   0xfffc0000,   FMT_7, {IMM24, AN0}},
00203 
00204 { "movx",     0xf57000,     0xfff000,     FMT_5, {MEM2(SD8, AN1), DM0}},
00205 { "movx",     0xf7700000,   0xfff00000,   FMT_6, {MEM2(SD16, AN1), DM0}},
00206 { "movx",     0xf4b00000,   0xfff00000,   FMT_7, {MEM2(IMM24,AN1), DM0}},
00207 { "movx",     0xf55000,     0xfff000,     FMT_5, {DM0, MEM2(SD8, AN1)}},
00208 { "movx",     0xf7600000,   0xfff00000,   FMT_6, {DM0, MEM2(SD16, AN1)}},
00209 { "movx",     0xf4300000,   0xfff00000,   FMT_7, {DM0, MEM2(IMM24, AN1)}},
00210 
00211 { "movb",     0xf52000,     0xfff000,     FMT_5, {MEM2(SD8, AN1), DM0}},
00212 { "movb",     0xf7d00000,   0xfff00000,   FMT_6, {MEM2(SD16, AN1), DM0}},
00213 { "movb",     0xf4a00000,   0xfff00000,   FMT_7, {MEM2(IMM24,AN1), DM0}},
00214 { "movb",     0xf040,              0xffc0,              FMT_4, {MEM2(DI, AN1), DM0}},
00215 { "movb",     0xf4c40000,   0xfffc0000,   FMT_7, {MEM(IMM24_MEM), DN0}},
00216 { "movb",     0x10,         0xf0,         FMT_1, {DM0, MEM(AN1)}},
00217 { "movb",     0xf51000,     0xfff000,     FMT_5, {DM0, MEM2(SD8, AN1)}},
00218 { "movb",     0xf7900000,   0xfff00000,   FMT_6, {DM0, MEM2(SD16, AN1)}},
00219 { "movb",     0xf4200000,   0xfff00000,   FMT_7, {DM0, MEM2(IMM24, AN1)}},
00220 { "movb",     0xf0c0,              0xffc0,              FMT_4, {DM0, MEM2(DI, AN1)}},
00221 { "movb",     0xc40000,     0xfc0000,     FMT_3, {DN0, MEM(IMM16_MEM)}},
00222 { "movb",     0xf4440000,   0xfffc0000,   FMT_7, {DN0, MEM(IMM24_MEM)}},
00223 
00224 { "movbu",    0x30,         0xf0,         FMT_1, {MEM(AN1), DM0}},
00225 { "movbu",    0xf53000,     0xfff000,     FMT_5, {MEM2(SD8, AN1), DM0}},
00226 { "movbu",    0xf7500000,   0xfff00000,   FMT_6, {MEM2(SD16, AN1), DM0}},
00227 { "movbu",    0xf4900000,   0xfff00000,   FMT_7, {MEM2(IMM24,AN1), DM0}},
00228 { "movbu",    0xf080,              0xffc0,              FMT_4, {MEM2(DI, AN1), DM0}},
00229 { "movbu",    0xcc0000,     0xfc0000,     FMT_3, {MEM(IMM16_MEM), DN0}},
00230 { "movbu",    0xf4c80000,   0xfffc0000,   FMT_7, {MEM(IMM24_MEM), DN0}},
00231 
00232 { "ext",      0xf3c1,              0xfff3,              FMT_4, {DN1}},
00233 { "extx",     0xb0,         0xfc,         FMT_1, {DN0}},
00234 { "extxu",    0xb4,         0xfc,         FMT_1, {DN0}},
00235 { "extxb",    0xb8,         0xfc,         FMT_1, {DN0}},
00236 { "extxbu",   0xbc,         0xfc,         FMT_1, {DN0}},
00237 
00238 { "add",      0x90,         0xf0,         FMT_1, {DN1, DM0}},
00239 { "add",      0xf200,              0xfff0,              FMT_4, {DM1, AN0}},
00240 { "add",      0xf2c0,              0xfff0,              FMT_4, {AN1, DM0}},
00241 { "add",      0xf240,              0xfff0,              FMT_4, {AN1, AM0}},
00242 { "add",      0xd400,              0xfc00,              FMT_2, {SIMM8, DN0}},
00243 { "add",      0xf7180000,   0xfffc0000,   FMT_6, {SIMM16, DN0}},
00244 { "add",      0xf4600000,   0xfffc0000,   FMT_7, {IMM24, DN0}},
00245 { "add",      0xd000,              0xfc00,              FMT_2, {SIMM8, AN0}},
00246 { "add",      0xf7080000,   0xfffc0000,   FMT_6, {SIMM16, AN0}},
00247 { "add",      0xf4640000,   0xfffc0000,   FMT_7, {IMM24, AN0}},
00248 { "addc",     0xf280,              0xfff0,              FMT_4, {DN1, DM0}},
00249 { "addnf",    0xf50c00,     0xfffc00,     FMT_5, {SIMM8, AN0}},
00250 
00251 { "sub",      0xa0,         0xf0,         FMT_1, {DN1, DM0}},
00252 { "sub",      0xf210,              0xfff0,              FMT_4, {DN1, AN0}},
00253 { "sub",      0xf2d0,              0xfff0,              FMT_4, {AN1, DM0}},
00254 { "sub",      0xf250,              0xfff0,              FMT_4, {AN1, AM0}},
00255 { "sub",      0xf71c0000,   0xfffc0000,   FMT_6, {IMM16, DN0}},
00256 { "sub",      0xf4680000,   0xfffc0000,   FMT_7, {IMM24, DN0}},
00257 { "sub",      0xf70c0000,   0xfffc0000,   FMT_6, {IMM16, AN0}},
00258 { "sub",      0xf46c0000,   0xfffc0000,   FMT_7, {IMM24, AN0}},
00259 { "subc",     0xf290,              0xfff0,              FMT_4, {DN1, DM0}},
00260 
00261 { "mul",      0xf340,              0xfff0,              FMT_4, {DN1, DM0}},
00262 { "mulu",     0xf350,              0xfff0,              FMT_4, {DN1, DM0}},
00263 
00264 { "divu",     0xf360,              0xfff0,              FMT_4, {DN1, DM0}},
00265 
00266 { "cmp",      0xf390,              0xfff0,              FMT_4, {DN1, DM0}},
00267 { "cmp",      0xf220,              0xfff0,              FMT_4, {DM1, AN0}},
00268 { "cmp",      0xf2e0,              0xfff0,              FMT_4, {AN1, DM0}},
00269 { "cmp",      0xf260,              0xfff0,              FMT_4, {AN1, AM0}},
00270 { "cmp",      0xd800,              0xfc00,              FMT_2, {SIMM8, DN0}},
00271 { "cmp",      0xf7480000,   0xfffc0000,   FMT_6, {SIMM16, DN0}},
00272 { "cmp",      0xf4780000,   0xfffc0000,   FMT_7, {IMM24, DN0}},
00273 { "cmp",      0xec0000,     0xfc0000,     FMT_3, {IMM16, AN0}},
00274 { "cmp",      0xf47c0000,   0xfffc0000,   FMT_7, {IMM24, AN0}},
00275 
00276 { "and",      0xf300,              0xfff0,              FMT_4, {DN1, DM0}},
00277 { "and",      0xf50000,     0xfffc00,     FMT_5, {IMM8, DN0}},
00278 { "and",      0xf7000000,   0xfffc0000,   FMT_6, {SIMM16N, DN0}},
00279 { "and",      0xf7100000,   0xffff0000,   FMT_6, {SIMM16N, PSW}},
00280 { "or",              0xf310,              0xfff0,              FMT_4, {DN1, DM0}},
00281 { "or",              0xf50800,     0xfffc00,     FMT_5, {IMM8, DN0}},
00282 { "or",              0xf7400000,   0xfffc0000,   FMT_6, {SIMM16N, DN0}},
00283 { "or",              0xf7140000,   0xffff0000,   FMT_6, {SIMM16N, PSW}},
00284 { "xor",      0xf320,              0xfff0,              FMT_4, {DN1, DM0}},
00285 { "xor",      0xf74c0000,   0xfffc0000,   FMT_6, {SIMM16N, DN0}},
00286 { "not",      0xf3e4,              0xfffc,              FMT_4, {DN0}},
00287 
00288 { "asr",      0xf338,              0xfffc,              FMT_4, {DN0}},
00289 { "lsr",      0xf33c,              0xfffc,              FMT_4, {DN0}},
00290 { "ror",      0xf334,              0xfffc,              FMT_4, {DN0}},
00291 { "rol",      0xf330,              0xfffc,              FMT_4, {DN0}},
00292 
00293 { "btst",     0xf50400,     0xfffc00,     FMT_5, {IMM8, DN0}},
00294 { "btst",     0xf7040000,   0xfffc0000,   FMT_6, {SIMM16N, DN0}},
00295 { "bset",     0xf020,              0xfff0,              FMT_4, {DM0, MEM(AN1)}},
00296 { "bclr",     0xf030,              0xfff0,              FMT_4, {DM0, MEM(AN1)}},
00297 
00298 { "beq",      0xe800,              0xff00,              FMT_2, {SD8N_PCREL}},
00299 { "bne",      0xe900,              0xff00,              FMT_2, {SD8N_PCREL}},
00300 { "blt",      0xe000,              0xff00,              FMT_2, {SD8N_PCREL}},
00301 { "ble",      0xe300,              0xff00,              FMT_2, {SD8N_PCREL}},
00302 { "bge",      0xe200,              0xff00,              FMT_2, {SD8N_PCREL}},
00303 { "bgt",      0xe100,              0xff00,              FMT_2, {SD8N_PCREL}},
00304 { "bcs",      0xe400,              0xff00,              FMT_2, {SD8N_PCREL}},
00305 { "bls",      0xe700,              0xff00,              FMT_2, {SD8N_PCREL}},
00306 { "bcc",      0xe600,              0xff00,              FMT_2, {SD8N_PCREL}},
00307 { "bhi",      0xe500,              0xff00,              FMT_2, {SD8N_PCREL}},
00308 { "bvc",      0xf5fc00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00309 { "bvs",      0xf5fd00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00310 { "bnc",      0xf5fe00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00311 { "bns",      0xf5ff00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00312 { "bra",      0xea00,              0xff00,              FMT_2, {SD8N_PCREL}},
00313 
00314 { "beqx",     0xf5e800,     0xffff00,     FMT_5, {SD8N_PCREL}},
00315 { "bnex",     0xf5e900,     0xffff00,     FMT_5, {SD8N_PCREL}},
00316 { "bltx",     0xf5e000,     0xffff00,     FMT_5, {SD8N_PCREL}},
00317 { "blex",     0xf5e300,     0xffff00,     FMT_5, {SD8N_PCREL}},
00318 { "bgex",     0xf5e200,     0xffff00,     FMT_5, {SD8N_PCREL}},
00319 { "bgtx",     0xf5e100,     0xffff00,     FMT_5, {SD8N_PCREL}},
00320 { "bcsx",     0xf5e400,     0xffff00,     FMT_5, {SD8N_PCREL}},
00321 { "blsx",     0xf5e700,     0xffff00,     FMT_5, {SD8N_PCREL}},
00322 { "bccx",     0xf5e600,     0xffff00,     FMT_5, {SD8N_PCREL}},
00323 { "bhix",     0xf5e500,     0xffff00,     FMT_5, {SD8N_PCREL}},
00324 { "bvcx",     0xf5ec00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00325 { "bvsx",     0xf5ed00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00326 { "bncx",     0xf5ee00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00327 { "bnsx",     0xf5ef00,     0xffff00,     FMT_5, {SD8N_PCREL}},
00328 
00329 { "jmp",      0xfc0000,     0xff0000,     FMT_3, {IMM16_PCREL}},
00330 { "jmp",      0xf4e00000,   0xffff0000,   FMT_7, {IMM24_PCREL}},
00331 { "jmp",      0xf000,              0xfff3,              FMT_4, {PAREN,AN1,PAREN}},
00332 { "jsr",      0xfd0000,     0xff0000,     FMT_3, {IMM16_PCREL}},
00333 { "jsr",      0xf4e10000,   0xffff0000,   FMT_7, {IMM24_PCREL}},
00334 { "jsr",      0xf001,              0xfff3,              FMT_4, {PAREN,AN1,PAREN}},
00335 
00336 { "nop",      0xf6,         0xff,         FMT_1, {UNUSED}},
00337 
00338 { "rts",      0xfe,         0xff,         FMT_1, {UNUSED}},
00339 { "rti",      0xeb,         0xff,         FMT_1, {UNUSED}},
00340 
00341 /* Extension.  We need some instruction to trigger "emulated syscalls"
00342    for our simulator.  */
00343 { "syscall",  0xf010,              0xffff,              FMT_4, {UNUSED}},
00344 
00345 /* Extension.  When talking to the simulator, gdb requires some instruction
00346    that will trigger a "breakpoint" (really just an instruction that isn't
00347    otherwise used by the tools.  This instruction must be the same size
00348    as the smallest instruction on the target machine.  In the case of the
00349    mn10x00 the "break" instruction must be one byte.  0xff is available on
00350    both mn10x00 architectures.  */
00351 { "break",      0xff,           0xff,           FMT_1, {UNUSED}},
00352 
00353 { 0, 0, 0, 0, {0}},
00354 
00355 } ;
00356 
00357 const int mn10200_num_opcodes =
00358   sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
00359 
00360