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cell-binutils  2.17cvs20070401
iq2000-desc.h
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00001 /* CPU data header for iq2000.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef IQ2000_CPU_H
00026 #define IQ2000_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH iq2000
00031 
00032 /* Given symbol S, return iq2000_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) iq2000##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) iq2000_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_IQ2000BF
00042 #define HAVE_CPU_IQ10BF
00043 
00044 #define CGEN_INSN_LSB0_P 1
00045 
00046 /* Minimum size of any insn (in bytes).  */
00047 #define CGEN_MIN_INSN_SIZE 4
00048 
00049 /* Maximum size of any insn (in bytes).  */
00050 #define CGEN_MAX_INSN_SIZE 4
00051 
00052 #define CGEN_INT_INSN_P 1
00053 
00054 /* Maximum number of syntax elements in an instruction.  */
00055 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
00056 
00057 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00058    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00059    we can't hash on everything up to the space.  */
00060 #define CGEN_MNEMONIC_OPERANDS
00061 
00062 /* Maximum number of fields in an instruction.  */
00063 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
00064 
00065 /* Enums.  */
00066 
00067 /* Enum declaration for .  */
00068 typedef enum gr_names {
00069   H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1
00070  , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3
00071  , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5
00072  , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7
00073  , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9
00074  , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11
00075  , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13
00076  , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15
00077  , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17
00078  , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19
00079  , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21
00080  , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23
00081  , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25
00082  , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27
00083  , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29
00084  , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31
00085 } GR_NAMES;
00086 
00087 /* Enum declaration for primary opcodes.  */
00088 typedef enum opcodes {
00089   OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3
00090  , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7
00091  , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11
00092  , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15
00093  , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19
00094  , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23
00095  , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27
00096  , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31
00097  , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36
00098  , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41
00099  , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47
00100  , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63
00101 } OPCODES;
00102 
00103 /* Enum declaration for iq10-only primary opcodes.  */
00104 typedef enum q10_opcodes {
00105   OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47
00106  , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63
00107 } Q10_OPCODES;
00108 
00109 /* Enum declaration for branch sub-opcodes.  */
00110 typedef enum regimm_functions {
00111   FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3
00112  , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7
00113  , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16
00114  , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20
00115  , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23
00116 } REGIMM_FUNCTIONS;
00117 
00118 /* Enum declaration for function sub-opcodes.  */
00119 typedef enum functions {
00120   FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3
00121  , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7
00122  , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12
00123  , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33
00124  , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37
00125  , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42
00126  , FUNC_SLTU = 43, FUNC_MRGB = 45
00127 } FUNCTIONS;
00128 
00129 /* Enum declaration for iq10-only special function sub-opcodes.  */
00130 typedef enum q10s_functions {
00131   FUNC10_YIELD = 14, FUNC10_CNT1S = 46
00132 } Q10S_FUNCTIONS;
00133 
00134 /* Enum declaration for iq10 function sub-opcodes.  */
00135 typedef enum cop_functions {
00136   FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3
00137  , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7
00138  , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12
00139  , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18
00140  , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33
00141  , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37
00142  , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41
00143  , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0
00144  , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8
00145  , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20
00146  , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29
00147  , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35
00148  , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41
00149  , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48
00150  , FUNC10_CM32SA = 56
00151 } COP_FUNCTIONS;
00152 
00153 /* Enum declaration for iq10 function sub-opcodes.  */
00154 typedef enum cop_cm128_4functions {
00155   FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6
00156 } COP_CM128_4FUNCTIONS;
00157 
00158 /* Enum declaration for iq10 function sub-opcodes.  */
00159 typedef enum cop_cm128_3functions {
00160   FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7
00161 } COP_CM128_3FUNCTIONS;
00162 
00163 /* Enum declaration for iq10 coprocessor sub-opcodes.  */
00164 typedef enum cop2_functions {
00165   FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3
00166  , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5
00167  , FUNC10_WBI = 6, FUNC10_WBIU = 7
00168 } COP2_FUNCTIONS;
00169 
00170 /* Enum declaration for iq10 coprocessor cam sub-opcodes.  */
00171 typedef enum cop3_cam_functions {
00172   FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19
00173 } COP3_CAM_FUNCTIONS;
00174 
00175 /* Attributes.  */
00176 
00177 /* Enum declaration for machine type selection.  */
00178 typedef enum mach_attr {
00179   MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX
00180 } MACH_ATTR;
00181 
00182 /* Enum declaration for instruction set selection.  */
00183 typedef enum isa_attr {
00184   ISA_IQ2000, ISA_MAX
00185 } ISA_ATTR;
00186 
00187 /* Number of architecture variants.  */
00188 #define MAX_ISAS  1
00189 #define MAX_MACHS ((int) MACH_MAX)
00190 
00191 /* Ifield support.  */
00192 
00193 /* Ifield attribute indices.  */
00194 
00195 /* Enum declaration for cgen_ifld attrs.  */
00196 typedef enum cgen_ifld_attr {
00197   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00198  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00199  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00200 } CGEN_IFLD_ATTR;
00201 
00202 /* Number of non-boolean elements in cgen_ifld_attr.  */
00203 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00204 
00205 /* cgen_ifld attribute accessor macros.  */
00206 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00207 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00208 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00209 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00210 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00211 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00212 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00213 
00214 /* Enum declaration for iq2000 ifield types.  */
00215 typedef enum ifield_type {
00216   IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS
00217  , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP
00218  , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM
00219  , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG
00220  , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT
00221  , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL
00222  , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19
00223  , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z
00224  , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z
00225  , IQ2000_F_CM_4Z, IQ2000_F_MAX
00226 } IFIELD_TYPE;
00227 
00228 #define MAX_IFLD ((int) IQ2000_F_MAX)
00229 
00230 /* Hardware attribute indices.  */
00231 
00232 /* Enum declaration for cgen_hw attrs.  */
00233 typedef enum cgen_hw_attr {
00234   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00235  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00236 } CGEN_HW_ATTR;
00237 
00238 /* Number of non-boolean elements in cgen_hw_attr.  */
00239 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00240 
00241 /* cgen_hw attribute accessor macros.  */
00242 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00243 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00244 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00245 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00246 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00247 
00248 /* Enum declaration for iq2000 hardware types.  */
00249 typedef enum cgen_hw_type {
00250   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00251  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX
00252 } CGEN_HW_TYPE;
00253 
00254 #define MAX_HW ((int) HW_MAX)
00255 
00256 /* Operand attribute indices.  */
00257 
00258 /* Enum declaration for cgen_operand attrs.  */
00259 typedef enum cgen_operand_attr {
00260   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00261  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00262  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00263 } CGEN_OPERAND_ATTR;
00264 
00265 /* Number of non-boolean elements in cgen_operand_attr.  */
00266 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00267 
00268 /* cgen_operand attribute accessor macros.  */
00269 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00270 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00271 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00272 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00273 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00274 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00275 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00276 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00277 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00278 
00279 /* Enum declaration for iq2000 operand types.  */
00280 typedef enum cgen_operand_type {
00281   IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD
00282  , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT
00283  , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG
00284  , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT
00285  , IQ2000_OPERAND__INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
00286  , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z
00287  , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM
00288  , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10
00289  , IQ2000_OPERAND_MAX
00290 } CGEN_OPERAND_TYPE;
00291 
00292 /* Number of operands types.  */
00293 #define MAX_OPERANDS 32
00294 
00295 /* Maximum number of operands referenced by any insn.  */
00296 #define MAX_OPERAND_INSTANCES 8
00297 
00298 /* Insn attribute indices.  */
00299 
00300 /* Enum declaration for cgen_insn attrs.  */
00301 typedef enum cgen_insn_attr {
00302   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00303  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00304  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY
00305  , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS
00306  , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
00307  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
00308 } CGEN_INSN_ATTR;
00309 
00310 /* Number of non-boolean elements in cgen_insn_attr.  */
00311 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00312 
00313 /* cgen_insn attribute accessor macros.  */
00314 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00315 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00316 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00317 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00318 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00319 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00320 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00321 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00322 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00323 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00324 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00325 #define CGEN_ATTR_CGEN_INSN_YIELD_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_YIELD_INSN)) != 0)
00326 #define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
00327 #define CGEN_ATTR_CGEN_INSN_EVEN_REG_NUM_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EVEN_REG_NUM)) != 0)
00328 #define CGEN_ATTR_CGEN_INSN_UNSUPPORTED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNSUPPORTED)) != 0)
00329 #define CGEN_ATTR_CGEN_INSN_USES_RD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RD)) != 0)
00330 #define CGEN_ATTR_CGEN_INSN_USES_RS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RS)) != 0)
00331 #define CGEN_ATTR_CGEN_INSN_USES_RT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RT)) != 0)
00332 #define CGEN_ATTR_CGEN_INSN_USES_R31_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_R31)) != 0)
00333 
00334 /* cgen.h uses things we just defined.  */
00335 #include "opcode/cgen.h"
00336 
00337 extern const struct cgen_ifld iq2000_cgen_ifld_table[];
00338 
00339 /* Attributes.  */
00340 extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[];
00341 extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[];
00342 extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[];
00343 extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[];
00344 
00345 /* Hardware decls.  */
00346 
00347 extern CGEN_KEYWORD iq2000_cgen_opval_gr_names;
00348 
00349 extern const CGEN_HW_ENTRY iq2000_cgen_hw_table[];
00350 
00351 
00352 
00353 #endif /* IQ2000_CPU_H */