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cell-binutils  2.17cvs20070401
iq2000-desc.c
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00001 /* CPU data for iq2000.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "iq2000-desc.h"
00032 #include "iq2000-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "iq2000", MACH_IQ2000 },
00050   { "iq10", MACH_IQ10 },
00051   { "max", MACH_MAX },
00052   { 0, 0 }
00053 };
00054 
00055 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00056 {
00057   { "iq2000", ISA_IQ2000 },
00058   { "max", ISA_MAX },
00059   { 0, 0 }
00060 };
00061 
00062 const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] =
00063 {
00064   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00065   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00066   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00067   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00068   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00069   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00070   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00071   { 0, 0, 0 }
00072 };
00073 
00074 const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] =
00075 {
00076   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00077   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00078   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00079   { "PC", &bool_attr[0], &bool_attr[0] },
00080   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00081   { 0, 0, 0 }
00082 };
00083 
00084 const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] =
00085 {
00086   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00087   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00088   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00089   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00090   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00091   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00092   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00093   { "RELAX", &bool_attr[0], &bool_attr[0] },
00094   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00095   { 0, 0, 0 }
00096 };
00097 
00098 const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
00099 {
00100   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00101   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00102   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00103   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00104   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00105   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00106   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00107   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00108   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00109   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00110   { "PBB", &bool_attr[0], &bool_attr[0] },
00111   { "YIELD-INSN", &bool_attr[0], &bool_attr[0] },
00112   { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
00113   { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] },
00114   { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] },
00115   { "USES-RD", &bool_attr[0], &bool_attr[0] },
00116   { "USES-RS", &bool_attr[0], &bool_attr[0] },
00117   { "USES-RT", &bool_attr[0], &bool_attr[0] },
00118   { "USES-R31", &bool_attr[0], &bool_attr[0] },
00119   { 0, 0, 0 }
00120 };
00121 
00122 /* Instruction set variants.  */
00123 
00124 static const CGEN_ISA iq2000_cgen_isa_table[] = {
00125   { "iq2000", 32, 32, 32, 32 },
00126   { 0, 0, 0, 0, 0 }
00127 };
00128 
00129 /* Machine variants.  */
00130 
00131 static const CGEN_MACH iq2000_cgen_mach_table[] = {
00132   { "iq2000", "iq2000", MACH_IQ2000, 0 },
00133   { "iq10", "iq10", MACH_IQ10, 0 },
00134   { 0, 0, 0, 0 }
00135 };
00136 
00137 static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] =
00138 {
00139   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00140   { "%0", 0, {0, {{{0, 0}}}}, 0, 0 },
00141   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
00142   { "%1", 1, {0, {{{0, 0}}}}, 0, 0 },
00143   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
00144   { "%2", 2, {0, {{{0, 0}}}}, 0, 0 },
00145   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
00146   { "%3", 3, {0, {{{0, 0}}}}, 0, 0 },
00147   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
00148   { "%4", 4, {0, {{{0, 0}}}}, 0, 0 },
00149   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
00150   { "%5", 5, {0, {{{0, 0}}}}, 0, 0 },
00151   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
00152   { "%6", 6, {0, {{{0, 0}}}}, 0, 0 },
00153   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
00154   { "%7", 7, {0, {{{0, 0}}}}, 0, 0 },
00155   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
00156   { "%8", 8, {0, {{{0, 0}}}}, 0, 0 },
00157   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
00158   { "%9", 9, {0, {{{0, 0}}}}, 0, 0 },
00159   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
00160   { "%10", 10, {0, {{{0, 0}}}}, 0, 0 },
00161   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
00162   { "%11", 11, {0, {{{0, 0}}}}, 0, 0 },
00163   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
00164   { "%12", 12, {0, {{{0, 0}}}}, 0, 0 },
00165   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
00166   { "%13", 13, {0, {{{0, 0}}}}, 0, 0 },
00167   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
00168   { "%14", 14, {0, {{{0, 0}}}}, 0, 0 },
00169   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
00170   { "%15", 15, {0, {{{0, 0}}}}, 0, 0 },
00171   { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
00172   { "%16", 16, {0, {{{0, 0}}}}, 0, 0 },
00173   { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
00174   { "%17", 17, {0, {{{0, 0}}}}, 0, 0 },
00175   { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
00176   { "%18", 18, {0, {{{0, 0}}}}, 0, 0 },
00177   { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
00178   { "%19", 19, {0, {{{0, 0}}}}, 0, 0 },
00179   { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
00180   { "%20", 20, {0, {{{0, 0}}}}, 0, 0 },
00181   { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
00182   { "%21", 21, {0, {{{0, 0}}}}, 0, 0 },
00183   { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
00184   { "%22", 22, {0, {{{0, 0}}}}, 0, 0 },
00185   { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
00186   { "%23", 23, {0, {{{0, 0}}}}, 0, 0 },
00187   { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
00188   { "%24", 24, {0, {{{0, 0}}}}, 0, 0 },
00189   { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
00190   { "%25", 25, {0, {{{0, 0}}}}, 0, 0 },
00191   { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
00192   { "%26", 26, {0, {{{0, 0}}}}, 0, 0 },
00193   { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
00194   { "%27", 27, {0, {{{0, 0}}}}, 0, 0 },
00195   { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
00196   { "%28", 28, {0, {{{0, 0}}}}, 0, 0 },
00197   { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
00198   { "%29", 29, {0, {{{0, 0}}}}, 0, 0 },
00199   { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
00200   { "%30", 30, {0, {{{0, 0}}}}, 0, 0 },
00201   { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
00202   { "%31", 31, {0, {{{0, 0}}}}, 0, 0 }
00203 };
00204 
00205 CGEN_KEYWORD iq2000_cgen_opval_gr_names =
00206 {
00207   & iq2000_cgen_opval_gr_names_entries[0],
00208   64,
00209   0, 0, 0, 0, ""
00210 };
00211 
00212 
00213 /* The hardware table.  */
00214 
00215 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00216 #define A(a) (1 << CGEN_HW_##a)
00217 #else
00218 #define A(a) (1 << CGEN_HW_a)
00219 #endif
00220 
00221 const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
00222 {
00223   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00224   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00225   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00226   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00227   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00228   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00229   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00230   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00231 };
00232 
00233 #undef A
00234 
00235 
00236 /* The instruction field table.  */
00237 
00238 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00239 #define A(a) (1 << CGEN_IFLD_##a)
00240 #else
00241 #define A(a) (1 << CGEN_IFLD_a)
00242 #endif
00243 
00244 const CGEN_IFLD iq2000_cgen_ifld_table[] =
00245 {
00246   { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00247   { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00248   { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00249   { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00250   { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00251   { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00252   { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00253   { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00254   { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00255   { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00256   { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00257   { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00258   { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00259   { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00260   { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00261   { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00262   { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00263   { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00264   { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00265   { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00266   { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00267   { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00268   { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00269   { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00270   { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00271   { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00272   { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00273   { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00274   { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00275   { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00276   { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00277   { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00278   { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00279   { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00280   { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00281   { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00282   { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00283   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00284 };
00285 
00286 #undef A
00287 
00288 
00289 
00290 /* multi ifield declarations */
00291 
00292 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [];
00293 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [];
00294 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [];
00295 
00296 
00297 /* multi ifield definitions */
00298 
00299 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] =
00300 {
00301     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
00302     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
00303     { 0, { (const PTR) 0 } }
00304 };
00305 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] =
00306 {
00307     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
00308     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
00309     { 0, { (const PTR) 0 } }
00310 };
00311 const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] =
00312 {
00313     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
00314     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
00315     { 0, { (const PTR) 0 } }
00316 };
00317 
00318 /* The operand table.  */
00319 
00320 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00321 #define A(a) (1 << CGEN_OPERAND_##a)
00322 #else
00323 #define A(a) (1 << CGEN_OPERAND_a)
00324 #endif
00325 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00326 #define OPERAND(op) IQ2000_OPERAND_##op
00327 #else
00328 #define OPERAND(op) IQ2000_OPERAND_op
00329 #endif
00330 
00331 const CGEN_OPERAND iq2000_cgen_operand_table[] =
00332 {
00333 /* pc: program counter */
00334   { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
00335     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } }, 
00336     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00337 /* rs: register Rs */
00338   { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
00339     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 
00340     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00341 /* rt: register Rt */
00342   { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
00343     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 
00344     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00345 /* rd: register Rd */
00346   { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
00347     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, 
00348     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00349 /* rd-rs: register Rd from Rs */
00350   { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
00351     { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } }, 
00352     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00353 /* rd-rt: register Rd from Rt */
00354   { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
00355     { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } }, 
00356     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00357 /* rt-rs: register Rt from Rs */
00358   { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
00359     { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } }, 
00360     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00361 /* shamt: shift amount */
00362   { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
00363     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } }, 
00364     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00365 /* imm: immediate */
00366   { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
00367     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
00368     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00369 /* offset: pc-relative offset */
00370   { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
00371     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } }, 
00372     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00373 /* baseoff: base register offset */
00374   { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
00375     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
00376     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00377 /* jmptarg: jump target */
00378   { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
00379     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } }, 
00380     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00381 /* mask: mask */
00382   { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
00383     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } }, 
00384     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00385 /* maskq10: iq10 mask */
00386   { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
00387     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } }, 
00388     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00389 /* maskl: mask left */
00390   { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
00391     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } }, 
00392     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00393 /* count: count */
00394   { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
00395     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } }, 
00396     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00397 /* _index: index */
00398   { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
00399     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } }, 
00400     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00401 /* execode: execcode */
00402   { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
00403     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } }, 
00404     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00405 /* bytecount: byte count */
00406   { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
00407     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } }, 
00408     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00409 /* cam-y: cam global opn y */
00410   { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
00411     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } }, 
00412     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00413 /* cam-z: cam global mask z */
00414   { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
00415     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } }, 
00416     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00417 /* cm-3func: CM 3 bit fn field */
00418   { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
00419     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } }, 
00420     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00421 /* cm-4func: CM 4 bit fn field */
00422   { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
00423     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } }, 
00424     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00425 /* cm-3z: CM 3 bit Z field */
00426   { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
00427     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } }, 
00428     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00429 /* cm-4z: CM 4 bit Z field */
00430   { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
00431     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } }, 
00432     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00433 /* base: base register */
00434   { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
00435     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 
00436     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00437 /* maskr: mask right */
00438   { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
00439     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 
00440     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00441 /* bitnum: bit number */
00442   { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
00443     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 
00444     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00445 /* hi16: high 16 bit immediate */
00446   { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
00447     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
00448     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00449 /* lo16: 16 bit signed immediate, for low */
00450   { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
00451     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
00452     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00453 /* mlo16: negated 16 bit signed immediate */
00454   { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
00455     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 
00456     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00457 /* jmptargq10: iq10 21-bit jump offset */
00458   { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
00459     { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } }, 
00460     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00461 /* sentinel */
00462   { 0, 0, 0, 0, 0,
00463     { 0, { (const PTR) 0 } },
00464     { 0, { { { (1<<MACH_BASE), 0 } } } } }
00465 };
00466 
00467 #undef A
00468 
00469 
00470 /* The instruction table.  */
00471 
00472 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00473 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00474 #define A(a) (1 << CGEN_INSN_##a)
00475 #else
00476 #define A(a) (1 << CGEN_INSN_a)
00477 #endif
00478 
00479 static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
00480 {
00481   /* Special null first entry.
00482      A `num' value of zero is thus invalid.
00483      Also, the special `invalid' insn resides here.  */
00484   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00485 /* add ${rd-rs},$rt */
00486   {
00487     -1, "add2", "add", 32,
00488     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00489   },
00490 /* add $rd,$rs,$rt */
00491   {
00492     IQ2000_INSN_ADD, "add", "add", 32,
00493     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00494   },
00495 /* addi ${rt-rs},$lo16 */
00496   {
00497     -1, "addi2", "addi", 32,
00498     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00499   },
00500 /* addi $rt,$rs,$lo16 */
00501   {
00502     IQ2000_INSN_ADDI, "addi", "addi", 32,
00503     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00504   },
00505 /* addiu ${rt-rs},$lo16 */
00506   {
00507     -1, "addiu2", "addiu", 32,
00508     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00509   },
00510 /* addiu $rt,$rs,$lo16 */
00511   {
00512     IQ2000_INSN_ADDIU, "addiu", "addiu", 32,
00513     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00514   },
00515 /* addu ${rd-rs},$rt */
00516   {
00517     -1, "addu2", "addu", 32,
00518     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00519   },
00520 /* addu $rd,$rs,$rt */
00521   {
00522     IQ2000_INSN_ADDU, "addu", "addu", 32,
00523     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00524   },
00525 /* ado16 ${rd-rs},$rt */
00526   {
00527     -1, "ado162", "ado16", 32,
00528     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00529   },
00530 /* ado16 $rd,$rs,$rt */
00531   {
00532     IQ2000_INSN_ADO16, "ado16", "ado16", 32,
00533     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00534   },
00535 /* and ${rd-rs},$rt */
00536   {
00537     -1, "and2", "and", 32,
00538     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00539   },
00540 /* and $rd,$rs,$rt */
00541   {
00542     IQ2000_INSN_AND, "and", "and", 32,
00543     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00544   },
00545 /* andi ${rt-rs},$lo16 */
00546   {
00547     -1, "andi2", "andi", 32,
00548     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00549   },
00550 /* andi $rt,$rs,$lo16 */
00551   {
00552     IQ2000_INSN_ANDI, "andi", "andi", 32,
00553     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00554   },
00555 /* andoi ${rt-rs},$lo16 */
00556   {
00557     -1, "andoi2", "andoi", 32,
00558     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00559   },
00560 /* andoi $rt,$rs,$lo16 */
00561   {
00562     IQ2000_INSN_ANDOI, "andoi", "andoi", 32,
00563     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00564   },
00565 /* nor ${rd-rs},$rt */
00566   {
00567     -1, "nor2", "nor", 32,
00568     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00569   },
00570 /* nor $rd,$rs,$rt */
00571   {
00572     IQ2000_INSN_NOR, "nor", "nor", 32,
00573     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00574   },
00575 /* or ${rd-rs},$rt */
00576   {
00577     -1, "or2", "or", 32,
00578     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00579   },
00580 /* or $rd,$rs,$rt */
00581   {
00582     IQ2000_INSN_OR, "or", "or", 32,
00583     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00584   },
00585 /* ori ${rt-rs},$lo16 */
00586   {
00587     -1, "ori2", "ori", 32,
00588     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00589   },
00590 /* ori $rt,$rs,$lo16 */
00591   {
00592     IQ2000_INSN_ORI, "ori", "ori", 32,
00593     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00594   },
00595 /* ram $rd,$rt,$shamt,$maskl,$maskr */
00596   {
00597     IQ2000_INSN_RAM, "ram", "ram", 32,
00598     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00599   },
00600 /* sll $rd,$rt,$shamt */
00601   {
00602     IQ2000_INSN_SLL, "sll", "sll", 32,
00603     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00604   },
00605 /* sllv ${rd-rt},$rs */
00606   {
00607     -1, "sllv2", "sllv", 32,
00608     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00609   },
00610 /* sllv $rd,$rt,$rs */
00611   {
00612     IQ2000_INSN_SLLV, "sllv", "sllv", 32,
00613     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00614   },
00615 /* slmv ${rd-rt},$rs,$shamt */
00616   {
00617     -1, "slmv2", "slmv", 32,
00618     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00619   },
00620 /* slmv $rd,$rt,$rs,$shamt */
00621   {
00622     IQ2000_INSN_SLMV, "slmv", "slmv", 32,
00623     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00624   },
00625 /* slt ${rd-rs},$rt */
00626   {
00627     -1, "slt2", "slt", 32,
00628     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00629   },
00630 /* slt $rd,$rs,$rt */
00631   {
00632     IQ2000_INSN_SLT, "slt", "slt", 32,
00633     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00634   },
00635 /* slti ${rt-rs},$imm */
00636   {
00637     -1, "slti2", "slti", 32,
00638     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00639   },
00640 /* slti $rt,$rs,$imm */
00641   {
00642     IQ2000_INSN_SLTI, "slti", "slti", 32,
00643     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00644   },
00645 /* sltiu ${rt-rs},$imm */
00646   {
00647     -1, "sltiu2", "sltiu", 32,
00648     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00649   },
00650 /* sltiu $rt,$rs,$imm */
00651   {
00652     IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32,
00653     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00654   },
00655 /* sltu ${rd-rs},$rt */
00656   {
00657     -1, "sltu2", "sltu", 32,
00658     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00659   },
00660 /* sltu $rd,$rs,$rt */
00661   {
00662     IQ2000_INSN_SLTU, "sltu", "sltu", 32,
00663     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00664   },
00665 /* sra ${rd-rt},$shamt */
00666   {
00667     -1, "sra2", "sra", 32,
00668     { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00669   },
00670 /* sra $rd,$rt,$shamt */
00671   {
00672     IQ2000_INSN_SRA, "sra", "sra", 32,
00673     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00674   },
00675 /* srav ${rd-rt},$rs */
00676   {
00677     -1, "srav2", "srav", 32,
00678     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00679   },
00680 /* srav $rd,$rt,$rs */
00681   {
00682     IQ2000_INSN_SRAV, "srav", "srav", 32,
00683     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00684   },
00685 /* srl $rd,$rt,$shamt */
00686   {
00687     IQ2000_INSN_SRL, "srl", "srl", 32,
00688     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00689   },
00690 /* srlv ${rd-rt},$rs */
00691   {
00692     -1, "srlv2", "srlv", 32,
00693     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00694   },
00695 /* srlv $rd,$rt,$rs */
00696   {
00697     IQ2000_INSN_SRLV, "srlv", "srlv", 32,
00698     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00699   },
00700 /* srmv ${rd-rt},$rs,$shamt */
00701   {
00702     -1, "srmv2", "srmv", 32,
00703     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00704   },
00705 /* srmv $rd,$rt,$rs,$shamt */
00706   {
00707     IQ2000_INSN_SRMV, "srmv", "srmv", 32,
00708     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00709   },
00710 /* sub ${rd-rs},$rt */
00711   {
00712     -1, "sub2", "sub", 32,
00713     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00714   },
00715 /* sub $rd,$rs,$rt */
00716   {
00717     IQ2000_INSN_SUB, "sub", "sub", 32,
00718     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00719   },
00720 /* subu ${rd-rs},$rt */
00721   {
00722     -1, "subu2", "subu", 32,
00723     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00724   },
00725 /* subu $rd,$rs,$rt */
00726   {
00727     IQ2000_INSN_SUBU, "subu", "subu", 32,
00728     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00729   },
00730 /* xor ${rd-rs},$rt */
00731   {
00732     -1, "xor2", "xor", 32,
00733     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00734   },
00735 /* xor $rd,$rs,$rt */
00736   {
00737     IQ2000_INSN_XOR, "xor", "xor", 32,
00738     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
00739   },
00740 /* xori ${rt-rs},$lo16 */
00741   {
00742     -1, "xori2", "xori", 32,
00743     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
00744   },
00745 /* xori $rt,$rs,$lo16 */
00746   {
00747     IQ2000_INSN_XORI, "xori", "xori", 32,
00748     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00749   },
00750 /* bbi $rs($bitnum),$offset */
00751   {
00752     IQ2000_INSN_BBI, "bbi", "bbi", 32,
00753     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00754   },
00755 /* bbin $rs($bitnum),$offset */
00756   {
00757     IQ2000_INSN_BBIN, "bbin", "bbin", 32,
00758     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00759   },
00760 /* bbv $rs,$rt,$offset */
00761   {
00762     IQ2000_INSN_BBV, "bbv", "bbv", 32,
00763     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00764   },
00765 /* bbvn $rs,$rt,$offset */
00766   {
00767     IQ2000_INSN_BBVN, "bbvn", "bbvn", 32,
00768     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00769   },
00770 /* beq $rs,$rt,$offset */
00771   {
00772     IQ2000_INSN_BEQ, "beq", "beq", 32,
00773     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00774   },
00775 /* beql $rs,$rt,$offset */
00776   {
00777     IQ2000_INSN_BEQL, "beql", "beql", 32,
00778     { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00779   },
00780 /* bgez $rs,$offset */
00781   {
00782     IQ2000_INSN_BGEZ, "bgez", "bgez", 32,
00783     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00784   },
00785 /* bgezal $rs,$offset */
00786   {
00787     IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32,
00788     { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00789   },
00790 /* bgezall $rs,$offset */
00791   {
00792     IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32,
00793     { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00794   },
00795 /* bgezl $rs,$offset */
00796   {
00797     IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32,
00798     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00799   },
00800 /* bltz $rs,$offset */
00801   {
00802     IQ2000_INSN_BLTZ, "bltz", "bltz", 32,
00803     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00804   },
00805 /* bltzl $rs,$offset */
00806   {
00807     IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32,
00808     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00809   },
00810 /* bltzal $rs,$offset */
00811   {
00812     IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32,
00813     { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00814   },
00815 /* bltzall $rs,$offset */
00816   {
00817     IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32,
00818     { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00819   },
00820 /* bmb0 $rs,$rt,$offset */
00821   {
00822     IQ2000_INSN_BMB0, "bmb0", "bmb0", 32,
00823     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00824   },
00825 /* bmb1 $rs,$rt,$offset */
00826   {
00827     IQ2000_INSN_BMB1, "bmb1", "bmb1", 32,
00828     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00829   },
00830 /* bmb2 $rs,$rt,$offset */
00831   {
00832     IQ2000_INSN_BMB2, "bmb2", "bmb2", 32,
00833     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00834   },
00835 /* bmb3 $rs,$rt,$offset */
00836   {
00837     IQ2000_INSN_BMB3, "bmb3", "bmb3", 32,
00838     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00839   },
00840 /* bne $rs,$rt,$offset */
00841   {
00842     IQ2000_INSN_BNE, "bne", "bne", 32,
00843     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00844   },
00845 /* bnel $rs,$rt,$offset */
00846   {
00847     IQ2000_INSN_BNEL, "bnel", "bnel", 32,
00848     { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00849   },
00850 /* jalr $rd,$rs */
00851   {
00852     IQ2000_INSN_JALR, "jalr", "jalr", 32,
00853     { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00854   },
00855 /* jr $rs */
00856   {
00857     IQ2000_INSN_JR, "jr", "jr", 32,
00858     { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00859   },
00860 /* lb $rt,$lo16($base) */
00861   {
00862     IQ2000_INSN_LB, "lb", "lb", 32,
00863     { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
00864   },
00865 /* lbu $rt,$lo16($base) */
00866   {
00867     IQ2000_INSN_LBU, "lbu", "lbu", 32,
00868     { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
00869   },
00870 /* lh $rt,$lo16($base) */
00871   {
00872     IQ2000_INSN_LH, "lh", "lh", 32,
00873     { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
00874   },
00875 /* lhu $rt,$lo16($base) */
00876   {
00877     IQ2000_INSN_LHU, "lhu", "lhu", 32,
00878     { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
00879   },
00880 /* lui $rt,$hi16 */
00881   {
00882     IQ2000_INSN_LUI, "lui", "lui", 32,
00883     { 0|A(USES_RT), { { { (1<<MACH_BASE), 0 } } } }
00884   },
00885 /* lw $rt,$lo16($base) */
00886   {
00887     IQ2000_INSN_LW, "lw", "lw", 32,
00888     { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
00889   },
00890 /* sb $rt,$lo16($base) */
00891   {
00892     IQ2000_INSN_SB, "sb", "sb", 32,
00893     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00894   },
00895 /* sh $rt,$lo16($base) */
00896   {
00897     IQ2000_INSN_SH, "sh", "sh", 32,
00898     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00899   },
00900 /* sw $rt,$lo16($base) */
00901   {
00902     IQ2000_INSN_SW, "sw", "sw", 32,
00903     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
00904   },
00905 /* break */
00906   {
00907     IQ2000_INSN_BREAK, "break", "break", 32,
00908     { 0, { { { (1<<MACH_BASE), 0 } } } }
00909   },
00910 /* syscall */
00911   {
00912     IQ2000_INSN_SYSCALL, "syscall", "syscall", 32,
00913     { 0|A(YIELD_INSN), { { { (1<<MACH_BASE), 0 } } } }
00914   },
00915 /* andoui $rt,$rs,$hi16 */
00916   {
00917     IQ2000_INSN_ANDOUI, "andoui", "andoui", 32,
00918     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
00919   },
00920 /* andoui ${rt-rs},$hi16 */
00921   {
00922     -1, "andoui2", "andoui", 32,
00923     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
00924   },
00925 /* orui ${rt-rs},$hi16 */
00926   {
00927     -1, "orui2", "orui", 32,
00928     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
00929   },
00930 /* orui $rt,$rs,$hi16 */
00931   {
00932     IQ2000_INSN_ORUI, "orui", "orui", 32,
00933     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
00934   },
00935 /* bgtz $rs,$offset */
00936   {
00937     IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32,
00938     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00939   },
00940 /* bgtzl $rs,$offset */
00941   {
00942     IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32,
00943     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00944   },
00945 /* blez $rs,$offset */
00946   {
00947     IQ2000_INSN_BLEZ, "blez", "blez", 32,
00948     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00949   },
00950 /* blezl $rs,$offset */
00951   {
00952     IQ2000_INSN_BLEZL, "blezl", "blezl", 32,
00953     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00954   },
00955 /* mrgb $rd,$rs,$rt,$mask */
00956   {
00957     IQ2000_INSN_MRGB, "mrgb", "mrgb", 32,
00958     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
00959   },
00960 /* mrgb ${rd-rs},$rt,$mask */
00961   {
00962     -1, "mrgb2", "mrgb", 32,
00963     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
00964   },
00965 /* bctxt $rs,$offset */
00966   {
00967     IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32,
00968     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00969   },
00970 /* bc0f $offset */
00971   {
00972     IQ2000_INSN_BC0F, "bc0f", "bc0f", 32,
00973     { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00974   },
00975 /* bc0fl $offset */
00976   {
00977     IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32,
00978     { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00979   },
00980 /* bc3f $offset */
00981   {
00982     IQ2000_INSN_BC3F, "bc3f", "bc3f", 32,
00983     { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00984   },
00985 /* bc3fl $offset */
00986   {
00987     IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32,
00988     { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00989   },
00990 /* bc0t $offset */
00991   {
00992     IQ2000_INSN_BC0T, "bc0t", "bc0t", 32,
00993     { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00994   },
00995 /* bc0tl $offset */
00996   {
00997     IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32,
00998     { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
00999   },
01000 /* bc3t $offset */
01001   {
01002     IQ2000_INSN_BC3T, "bc3t", "bc3t", 32,
01003     { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
01004   },
01005 /* bc3tl $offset */
01006   {
01007     IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32,
01008     { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
01009   },
01010 /* cfc0 $rt,$rd */
01011   {
01012     IQ2000_INSN_CFC0, "cfc0", "cfc0", 32,
01013     { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01014   },
01015 /* cfc1 $rt,$rd */
01016   {
01017     IQ2000_INSN_CFC1, "cfc1", "cfc1", 32,
01018     { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01019   },
01020 /* cfc2 $rt,$rd */
01021   {
01022     IQ2000_INSN_CFC2, "cfc2", "cfc2", 32,
01023     { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01024   },
01025 /* cfc3 $rt,$rd */
01026   {
01027     IQ2000_INSN_CFC3, "cfc3", "cfc3", 32,
01028     { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01029   },
01030 /* chkhdr $rd,$rt */
01031   {
01032     IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32,
01033     { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01034   },
01035 /* ctc0 $rt,$rd */
01036   {
01037     IQ2000_INSN_CTC0, "ctc0", "ctc0", 32,
01038     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01039   },
01040 /* ctc1 $rt,$rd */
01041   {
01042     IQ2000_INSN_CTC1, "ctc1", "ctc1", 32,
01043     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01044   },
01045 /* ctc2 $rt,$rd */
01046   {
01047     IQ2000_INSN_CTC2, "ctc2", "ctc2", 32,
01048     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01049   },
01050 /* ctc3 $rt,$rd */
01051   {
01052     IQ2000_INSN_CTC3, "ctc3", "ctc3", 32,
01053     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01054   },
01055 /* jcr $rs */
01056   {
01057     IQ2000_INSN_JCR, "jcr", "jcr", 32,
01058     { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
01059   },
01060 /* luc32 $rt,$rd */
01061   {
01062     IQ2000_INSN_LUC32, "luc32", "luc32", 32,
01063     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01064   },
01065 /* luc32l $rt,$rd */
01066   {
01067     IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32,
01068     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01069   },
01070 /* luc64 $rt,$rd */
01071   {
01072     IQ2000_INSN_LUC64, "luc64", "luc64", 32,
01073     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01074   },
01075 /* luc64l $rt,$rd */
01076   {
01077     IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32,
01078     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01079   },
01080 /* luk $rt,$rd */
01081   {
01082     IQ2000_INSN_LUK, "luk", "luk", 32,
01083     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01084   },
01085 /* lulck $rt */
01086   {
01087     IQ2000_INSN_LULCK, "lulck", "lulck", 32,
01088     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01089   },
01090 /* lum32 $rt,$rd */
01091   {
01092     IQ2000_INSN_LUM32, "lum32", "lum32", 32,
01093     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01094   },
01095 /* lum32l $rt,$rd */
01096   {
01097     IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32,
01098     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01099   },
01100 /* lum64 $rt,$rd */
01101   {
01102     IQ2000_INSN_LUM64, "lum64", "lum64", 32,
01103     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01104   },
01105 /* lum64l $rt,$rd */
01106   {
01107     IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32,
01108     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01109   },
01110 /* lur $rt,$rd */
01111   {
01112     IQ2000_INSN_LUR, "lur", "lur", 32,
01113     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01114   },
01115 /* lurl $rt,$rd */
01116   {
01117     IQ2000_INSN_LURL, "lurl", "lurl", 32,
01118     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01119   },
01120 /* luulck $rt */
01121   {
01122     IQ2000_INSN_LUULCK, "luulck", "luulck", 32,
01123     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01124   },
01125 /* mfc0 $rt,$rd */
01126   {
01127     IQ2000_INSN_MFC0, "mfc0", "mfc0", 32,
01128     { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01129   },
01130 /* mfc1 $rt,$rd */
01131   {
01132     IQ2000_INSN_MFC1, "mfc1", "mfc1", 32,
01133     { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01134   },
01135 /* mfc2 $rt,$rd */
01136   {
01137     IQ2000_INSN_MFC2, "mfc2", "mfc2", 32,
01138     { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01139   },
01140 /* mfc3 $rt,$rd */
01141   {
01142     IQ2000_INSN_MFC3, "mfc3", "mfc3", 32,
01143     { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
01144   },
01145 /* mtc0 $rt,$rd */
01146   {
01147     IQ2000_INSN_MTC0, "mtc0", "mtc0", 32,
01148     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01149   },
01150 /* mtc1 $rt,$rd */
01151   {
01152     IQ2000_INSN_MTC1, "mtc1", "mtc1", 32,
01153     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01154   },
01155 /* mtc2 $rt,$rd */
01156   {
01157     IQ2000_INSN_MTC2, "mtc2", "mtc2", 32,
01158     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01159   },
01160 /* mtc3 $rt,$rd */
01161   {
01162     IQ2000_INSN_MTC3, "mtc3", "mtc3", 32,
01163     { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01164   },
01165 /* pkrl $rd,$rt */
01166   {
01167     IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
01168     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01169   },
01170 /* pkrlr1 $rt,$_index,$count */
01171   {
01172     IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
01173     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01174   },
01175 /* pkrlr30 $rt,$_index,$count */
01176   {
01177     IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
01178     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01179   },
01180 /* rb $rd,$rt */
01181   {
01182     IQ2000_INSN_RB, "rb", "rb", 32,
01183     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01184   },
01185 /* rbr1 $rt,$_index,$count */
01186   {
01187     IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
01188     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01189   },
01190 /* rbr30 $rt,$_index,$count */
01191   {
01192     IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
01193     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01194   },
01195 /* rfe */
01196   {
01197     IQ2000_INSN_RFE, "rfe", "rfe", 32,
01198     { 0, { { { (1<<MACH_IQ2000), 0 } } } }
01199   },
01200 /* rx $rd,$rt */
01201   {
01202     IQ2000_INSN_RX, "rx", "rx", 32,
01203     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01204   },
01205 /* rxr1 $rt,$_index,$count */
01206   {
01207     IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
01208     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01209   },
01210 /* rxr30 $rt,$_index,$count */
01211   {
01212     IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
01213     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01214   },
01215 /* sleep */
01216   {
01217     IQ2000_INSN_SLEEP, "sleep", "sleep", 32,
01218     { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
01219   },
01220 /* srrd $rt */
01221   {
01222     IQ2000_INSN_SRRD, "srrd", "srrd", 32,
01223     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01224   },
01225 /* srrdl $rt */
01226   {
01227     IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32,
01228     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01229   },
01230 /* srulck $rt */
01231   {
01232     IQ2000_INSN_SRULCK, "srulck", "srulck", 32,
01233     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01234   },
01235 /* srwr $rt,$rd */
01236   {
01237     IQ2000_INSN_SRWR, "srwr", "srwr", 32,
01238     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01239   },
01240 /* srwru $rt,$rd */
01241   {
01242     IQ2000_INSN_SRWRU, "srwru", "srwru", 32,
01243     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01244   },
01245 /* trapqfl */
01246   {
01247     IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32,
01248     { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
01249   },
01250 /* trapqne */
01251   {
01252     IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32,
01253     { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
01254   },
01255 /* traprel $rt */
01256   {
01257     IQ2000_INSN_TRAPREL, "traprel", "traprel", 32,
01258     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01259   },
01260 /* wb $rd,$rt */
01261   {
01262     IQ2000_INSN_WB, "wb", "wb", 32,
01263     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01264   },
01265 /* wbu $rd,$rt */
01266   {
01267     IQ2000_INSN_WBU, "wbu", "wbu", 32,
01268     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01269   },
01270 /* wbr1 $rt,$_index,$count */
01271   {
01272     IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
01273     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01274   },
01275 /* wbr1u $rt,$_index,$count */
01276   {
01277     IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
01278     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01279   },
01280 /* wbr30 $rt,$_index,$count */
01281   {
01282     IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
01283     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01284   },
01285 /* wbr30u $rt,$_index,$count */
01286   {
01287     IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
01288     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01289   },
01290 /* wx $rd,$rt */
01291   {
01292     IQ2000_INSN_WX, "wx", "wx", 32,
01293     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01294   },
01295 /* wxu $rd,$rt */
01296   {
01297     IQ2000_INSN_WXU, "wxu", "wxu", 32,
01298     { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
01299   },
01300 /* wxr1 $rt,$_index,$count */
01301   {
01302     IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
01303     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01304   },
01305 /* wxr1u $rt,$_index,$count */
01306   {
01307     IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
01308     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01309   },
01310 /* wxr30 $rt,$_index,$count */
01311   {
01312     IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
01313     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01314   },
01315 /* wxr30u $rt,$_index,$count */
01316   {
01317     IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
01318     { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
01319   },
01320 /* ldw $rt,$lo16($base) */
01321   {
01322     IQ2000_INSN_LDW, "ldw", "ldw", 32,
01323     { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
01324   },
01325 /* sdw $rt,$lo16($base) */
01326   {
01327     IQ2000_INSN_SDW, "sdw", "sdw", 32,
01328     { 0|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
01329   },
01330 /* j $jmptarg */
01331   {
01332     IQ2000_INSN_J, "j", "j", 32,
01333     { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
01334   },
01335 /* jal $jmptarg */
01336   {
01337     IQ2000_INSN_JAL, "jal", "jal", 32,
01338     { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
01339   },
01340 /* bmb $rs,$rt,$offset */
01341   {
01342     IQ2000_INSN_BMB, "bmb", "bmb", 32,
01343     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
01344   },
01345 /* andoui $rt,$rs,$hi16 */
01346   {
01347     IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32,
01348     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01349   },
01350 /* andoui ${rt-rs},$hi16 */
01351   {
01352     -1, "andoui2-q10", "andoui", 32,
01353     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
01354   },
01355 /* orui $rt,$rs,$hi16 */
01356   {
01357     IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32,
01358     { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01359   },
01360 /* orui ${rt-rs},$hi16 */
01361   {
01362     -1, "orui2-q10", "orui", 32,
01363     { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
01364   },
01365 /* mrgb $rd,$rs,$rt,$maskq10 */
01366   {
01367     IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32,
01368     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01369   },
01370 /* mrgb ${rd-rs},$rt,$maskq10 */
01371   {
01372     -1, "mrgbq102", "mrgb", 32,
01373     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
01374   },
01375 /* j $jmptarg */
01376   {
01377     IQ2000_INSN_JQ10, "jq10", "j", 32,
01378     { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01379   },
01380 /* jal $rt,$jmptarg */
01381   {
01382     IQ2000_INSN_JALQ10, "jalq10", "jal", 32,
01383     { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01384   },
01385 /* jal $jmptarg */
01386   {
01387     IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32,
01388     { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01389   },
01390 /* bbil $rs($bitnum),$offset */
01391   {
01392     IQ2000_INSN_BBIL, "bbil", "bbil", 32,
01393     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01394   },
01395 /* bbinl $rs($bitnum),$offset */
01396   {
01397     IQ2000_INSN_BBINL, "bbinl", "bbinl", 32,
01398     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01399   },
01400 /* bbvl $rs,$rt,$offset */
01401   {
01402     IQ2000_INSN_BBVL, "bbvl", "bbvl", 32,
01403     { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01404   },
01405 /* bbvnl $rs,$rt,$offset */
01406   {
01407     IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32,
01408     { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01409   },
01410 /* bgtzal $rs,$offset */
01411   {
01412     IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32,
01413     { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01414   },
01415 /* bgtzall $rs,$offset */
01416   {
01417     IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32,
01418     { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01419   },
01420 /* blezal $rs,$offset */
01421   {
01422     IQ2000_INSN_BLEZAL, "blezal", "blezal", 32,
01423     { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01424   },
01425 /* blezall $rs,$offset */
01426   {
01427     IQ2000_INSN_BLEZALL, "blezall", "blezall", 32,
01428     { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01429   },
01430 /* bgtz $rs,$offset */
01431   {
01432     IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32,
01433     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01434   },
01435 /* bgtzl $rs,$offset */
01436   {
01437     IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32,
01438     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01439   },
01440 /* blez $rs,$offset */
01441   {
01442     IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32,
01443     { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01444   },
01445 /* blezl $rs,$offset */
01446   {
01447     IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32,
01448     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01449   },
01450 /* bmb $rs,$rt,$offset */
01451   {
01452     IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32,
01453     { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01454   },
01455 /* bmbl $rs,$rt,$offset */
01456   {
01457     IQ2000_INSN_BMBL, "bmbl", "bmbl", 32,
01458     { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01459   },
01460 /* bri $rs,$offset */
01461   {
01462     IQ2000_INSN_BRI, "bri", "bri", 32,
01463     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01464   },
01465 /* brv $rs,$offset */
01466   {
01467     IQ2000_INSN_BRV, "brv", "brv", 32,
01468     { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01469   },
01470 /* bctx $rs,$offset */
01471   {
01472     IQ2000_INSN_BCTX, "bctx", "bctx", 32,
01473     { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
01474   },
01475 /* yield */
01476   {
01477     IQ2000_INSN_YIELD, "yield", "yield", 32,
01478     { 0, { { { (1<<MACH_IQ10), 0 } } } }
01479   },
01480 /* crc32 $rd,$rs,$rt */
01481   {
01482     IQ2000_INSN_CRC32, "crc32", "crc32", 32,
01483     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01484   },
01485 /* crc32b $rd,$rs,$rt */
01486   {
01487     IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32,
01488     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01489   },
01490 /* cnt1s $rd,$rs */
01491   {
01492     IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32,
01493     { 0|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01494   },
01495 /* avail $rd */
01496   {
01497     IQ2000_INSN_AVAIL, "avail", "avail", 32,
01498     { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01499   },
01500 /* free $rd,$rs */
01501   {
01502     IQ2000_INSN_FREE, "free", "free", 32,
01503     { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01504   },
01505 /* tstod $rd,$rs */
01506   {
01507     IQ2000_INSN_TSTOD, "tstod", "tstod", 32,
01508     { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01509   },
01510 /* cmphdr $rd */
01511   {
01512     IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32,
01513     { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01514   },
01515 /* mcid $rd,$rt */
01516   {
01517     IQ2000_INSN_MCID, "mcid", "mcid", 32,
01518     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01519   },
01520 /* dba $rd */
01521   {
01522     IQ2000_INSN_DBA, "dba", "dba", 32,
01523     { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01524   },
01525 /* dbd $rd,$rs,$rt */
01526   {
01527     IQ2000_INSN_DBD, "dbd", "dbd", 32,
01528     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01529   },
01530 /* dpwt $rd,$rs */
01531   {
01532     IQ2000_INSN_DPWT, "dpwt", "dpwt", 32,
01533     { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01534   },
01535 /* chkhdr $rd,$rs */
01536   {
01537     IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32,
01538     { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01539   },
01540 /* rba $rd,$rs,$rt */
01541   {
01542     IQ2000_INSN_RBA, "rba", "rba", 32,
01543     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01544   },
01545 /* rbal $rd,$rs,$rt */
01546   {
01547     IQ2000_INSN_RBAL, "rbal", "rbal", 32,
01548     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01549   },
01550 /* rbar $rd,$rs,$rt */
01551   {
01552     IQ2000_INSN_RBAR, "rbar", "rbar", 32,
01553     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01554   },
01555 /* wba $rd,$rs,$rt */
01556   {
01557     IQ2000_INSN_WBA, "wba", "wba", 32,
01558     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01559   },
01560 /* wbau $rd,$rs,$rt */
01561   {
01562     IQ2000_INSN_WBAU, "wbau", "wbau", 32,
01563     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01564   },
01565 /* wbac $rd,$rs,$rt */
01566   {
01567     IQ2000_INSN_WBAC, "wbac", "wbac", 32,
01568     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01569   },
01570 /* rbi $rd,$rs,$rt,$bytecount */
01571   {
01572     IQ2000_INSN_RBI, "rbi", "rbi", 32,
01573     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01574   },
01575 /* rbil $rd,$rs,$rt,$bytecount */
01576   {
01577     IQ2000_INSN_RBIL, "rbil", "rbil", 32,
01578     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01579   },
01580 /* rbir $rd,$rs,$rt,$bytecount */
01581   {
01582     IQ2000_INSN_RBIR, "rbir", "rbir", 32,
01583     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01584   },
01585 /* wbi $rd,$rs,$rt,$bytecount */
01586   {
01587     IQ2000_INSN_WBI, "wbi", "wbi", 32,
01588     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01589   },
01590 /* wbic $rd,$rs,$rt,$bytecount */
01591   {
01592     IQ2000_INSN_WBIC, "wbic", "wbic", 32,
01593     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01594   },
01595 /* wbiu $rd,$rs,$rt,$bytecount */
01596   {
01597     IQ2000_INSN_WBIU, "wbiu", "wbiu", 32,
01598     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01599   },
01600 /* pkrli $rd,$rs,$rt,$bytecount */
01601   {
01602     IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32,
01603     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01604   },
01605 /* pkrlih $rd,$rs,$rt,$bytecount */
01606   {
01607     IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32,
01608     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01609   },
01610 /* pkrliu $rd,$rs,$rt,$bytecount */
01611   {
01612     IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32,
01613     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01614   },
01615 /* pkrlic $rd,$rs,$rt,$bytecount */
01616   {
01617     IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32,
01618     { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01619   },
01620 /* pkrla $rd,$rs,$rt */
01621   {
01622     IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32,
01623     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01624   },
01625 /* pkrlau $rd,$rs,$rt */
01626   {
01627     IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32,
01628     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01629   },
01630 /* pkrlah $rd,$rs,$rt */
01631   {
01632     IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32,
01633     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01634   },
01635 /* pkrlac $rd,$rs,$rt */
01636   {
01637     IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32,
01638     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01639   },
01640 /* lock $rd,$rt */
01641   {
01642     IQ2000_INSN_LOCK, "lock", "lock", 32,
01643     { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
01644   },
01645 /* unlk $rd,$rt */
01646   {
01647     IQ2000_INSN_UNLK, "unlk", "unlk", 32,
01648     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01649   },
01650 /* swrd $rd,$rt */
01651   {
01652     IQ2000_INSN_SWRD, "swrd", "swrd", 32,
01653     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01654   },
01655 /* swrdl $rd,$rt */
01656   {
01657     IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32,
01658     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01659   },
01660 /* swwr $rd,$rs,$rt */
01661   {
01662     IQ2000_INSN_SWWR, "swwr", "swwr", 32,
01663     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01664   },
01665 /* swwru $rd,$rs,$rt */
01666   {
01667     IQ2000_INSN_SWWRU, "swwru", "swwru", 32,
01668     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01669   },
01670 /* dwrd $rd,$rt */
01671   {
01672     IQ2000_INSN_DWRD, "dwrd", "dwrd", 32,
01673     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01674   },
01675 /* dwrdl $rd,$rt */
01676   {
01677     IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32,
01678     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01679   },
01680 /* cam36 $rd,$rt,${cam-z},${cam-y} */
01681   {
01682     IQ2000_INSN_CAM36, "cam36", "cam36", 32,
01683     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01684   },
01685 /* cam72 $rd,$rt,${cam-y},${cam-z} */
01686   {
01687     IQ2000_INSN_CAM72, "cam72", "cam72", 32,
01688     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01689   },
01690 /* cam144 $rd,$rt,${cam-y},${cam-z} */
01691   {
01692     IQ2000_INSN_CAM144, "cam144", "cam144", 32,
01693     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01694   },
01695 /* cam288 $rd,$rt,${cam-y},${cam-z} */
01696   {
01697     IQ2000_INSN_CAM288, "cam288", "cam288", 32,
01698     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01699   },
01700 /* cm32and $rd,$rs,$rt */
01701   {
01702     IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32,
01703     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01704   },
01705 /* cm32andn $rd,$rs,$rt */
01706   {
01707     IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32,
01708     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01709   },
01710 /* cm32or $rd,$rs,$rt */
01711   {
01712     IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32,
01713     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01714   },
01715 /* cm32ra $rd,$rs,$rt */
01716   {
01717     IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32,
01718     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01719   },
01720 /* cm32rd $rd,$rt */
01721   {
01722     IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32,
01723     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01724   },
01725 /* cm32ri $rd,$rt */
01726   {
01727     IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32,
01728     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01729   },
01730 /* cm32rs $rd,$rs,$rt */
01731   {
01732     IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32,
01733     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01734   },
01735 /* cm32sa $rd,$rs,$rt */
01736   {
01737     IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32,
01738     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01739   },
01740 /* cm32sd $rd,$rt */
01741   {
01742     IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32,
01743     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01744   },
01745 /* cm32si $rd,$rt */
01746   {
01747     IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32,
01748     { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
01749   },
01750 /* cm32ss $rd,$rs,$rt */
01751   {
01752     IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32,
01753     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01754   },
01755 /* cm32xor $rd,$rs,$rt */
01756   {
01757     IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32,
01758     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01759   },
01760 /* cm64clr $rd,$rt */
01761   {
01762     IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32,
01763     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01764   },
01765 /* cm64ra $rd,$rs,$rt */
01766   {
01767     IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32,
01768     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01769   },
01770 /* cm64rd $rd,$rt */
01771   {
01772     IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32,
01773     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01774   },
01775 /* cm64ri $rd,$rt */
01776   {
01777     IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32,
01778     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01779   },
01780 /* cm64ria2 $rd,$rs,$rt */
01781   {
01782     IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32,
01783     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01784   },
01785 /* cm64rs $rd,$rs,$rt */
01786   {
01787     IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32,
01788     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01789   },
01790 /* cm64sa $rd,$rs,$rt */
01791   {
01792     IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32,
01793     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01794   },
01795 /* cm64sd $rd,$rt */
01796   {
01797     IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32,
01798     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01799   },
01800 /* cm64si $rd,$rt */
01801   {
01802     IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32,
01803     { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01804   },
01805 /* cm64sia2 $rd,$rs,$rt */
01806   {
01807     IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32,
01808     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01809   },
01810 /* cm64ss $rd,$rs,$rt */
01811   {
01812     IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32,
01813     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01814   },
01815 /* cm128ria2 $rd,$rs,$rt */
01816   {
01817     IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32,
01818     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01819   },
01820 /* cm128ria3 $rd,$rs,$rt,${cm-3z} */
01821   {
01822     IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32,
01823     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01824   },
01825 /* cm128ria4 $rd,$rs,$rt,${cm-4z} */
01826   {
01827     IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32,
01828     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01829   },
01830 /* cm128sia2 $rd,$rs,$rt */
01831   {
01832     IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32,
01833     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01834   },
01835 /* cm128sia3 $rd,$rs,$rt,${cm-3z} */
01836   {
01837     IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32,
01838     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
01839   },
01840 /* cm128sia4 $rd,$rs,$rt,${cm-4z} */
01841   {
01842     IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32,
01843     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01844   },
01845 /* cm128vsa $rd,$rs,$rt */
01846   {
01847     IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32,
01848     { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01849   },
01850 /* cfc $rd,$rt */
01851   {
01852     IQ2000_INSN_CFC, "cfc", "cfc", 32,
01853     { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ10), 0 } } } }
01854   },
01855 /* ctc $rs,$rt */
01856   {
01857     IQ2000_INSN_CTC, "ctc", "ctc", 32,
01858     { 0|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
01859   },
01860 };
01861 
01862 #undef OP
01863 #undef A
01864 
01865 /* Initialize anything needed to be done once, before any cpu_open call.  */
01866 
01867 static void
01868 init_tables (void)
01869 {
01870 }
01871 
01872 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
01873 static void build_hw_table      (CGEN_CPU_TABLE *);
01874 static void build_ifield_table  (CGEN_CPU_TABLE *);
01875 static void build_operand_table (CGEN_CPU_TABLE *);
01876 static void build_insn_table    (CGEN_CPU_TABLE *);
01877 static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *);
01878 
01879 /* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name.  */
01880 
01881 static const CGEN_MACH *
01882 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
01883 {
01884   while (table->name)
01885     {
01886       if (strcmp (name, table->bfd_name) == 0)
01887        return table;
01888       ++table;
01889     }
01890   abort ();
01891 }
01892 
01893 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
01894 
01895 static void
01896 build_hw_table (CGEN_CPU_TABLE *cd)
01897 {
01898   int i;
01899   int machs = cd->machs;
01900   const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0];
01901   /* MAX_HW is only an upper bound on the number of selected entries.
01902      However each entry is indexed by it's enum so there can be holes in
01903      the table.  */
01904   const CGEN_HW_ENTRY **selected =
01905     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01906 
01907   cd->hw_table.init_entries = init;
01908   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01909   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01910   /* ??? For now we just use machs to determine which ones we want.  */
01911   for (i = 0; init[i].name != NULL; ++i)
01912     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01913        & machs)
01914       selected[init[i].type] = &init[i];
01915   cd->hw_table.entries = selected;
01916   cd->hw_table.num_entries = MAX_HW;
01917 }
01918 
01919 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
01920 
01921 static void
01922 build_ifield_table (CGEN_CPU_TABLE *cd)
01923 {
01924   cd->ifld_table = & iq2000_cgen_ifld_table[0];
01925 }
01926 
01927 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
01928 
01929 static void
01930 build_operand_table (CGEN_CPU_TABLE *cd)
01931 {
01932   int i;
01933   int machs = cd->machs;
01934   const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0];
01935   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01936      However each entry is indexed by it's enum so there can be holes in
01937      the table.  */
01938   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
01939 
01940   cd->operand_table.init_entries = init;
01941   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01942   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01943   /* ??? For now we just use mach to determine which ones we want.  */
01944   for (i = 0; init[i].name != NULL; ++i)
01945     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01946        & machs)
01947       selected[init[i].type] = &init[i];
01948   cd->operand_table.entries = selected;
01949   cd->operand_table.num_entries = MAX_OPERANDS;
01950 }
01951 
01952 /* Subroutine of iq2000_cgen_cpu_open to build the hardware table.
01953    ??? This could leave out insns not supported by the specified mach/isa,
01954    but that would cause errors like "foo only supported by bar" to become
01955    "unknown insn", so for now we include all insns and require the app to
01956    do the checking later.
01957    ??? On the other hand, parsing of such insns may require their hardware or
01958    operand elements to be in the table [which they mightn't be].  */
01959 
01960 static void
01961 build_insn_table (CGEN_CPU_TABLE *cd)
01962 {
01963   int i;
01964   const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0];
01965   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01966 
01967   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01968   for (i = 0; i < MAX_INSNS; ++i)
01969     insns[i].base = &ib[i];
01970   cd->insn_table.init_entries = insns;
01971   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01972   cd->insn_table.num_init_entries = MAX_INSNS;
01973 }
01974 
01975 /* Subroutine of iq2000_cgen_cpu_open to rebuild the tables.  */
01976 
01977 static void
01978 iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
01979 {
01980   int i;
01981   CGEN_BITSET *isas = cd->isas;
01982   unsigned int machs = cd->machs;
01983 
01984   cd->int_insn_p = CGEN_INT_INSN_P;
01985 
01986   /* Data derived from the isa spec.  */
01987 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01988   cd->default_insn_bitsize = UNSET;
01989   cd->base_insn_bitsize = UNSET;
01990   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
01991   cd->max_insn_bitsize = 0;
01992   for (i = 0; i < MAX_ISAS; ++i)
01993     if (cgen_bitset_contains (isas, i))
01994       {
01995        const CGEN_ISA *isa = & iq2000_cgen_isa_table[i];
01996 
01997        /* Default insn sizes of all selected isas must be
01998           equal or we set the result to 0, meaning "unknown".  */
01999        if (cd->default_insn_bitsize == UNSET)
02000          cd->default_insn_bitsize = isa->default_insn_bitsize;
02001        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
02002          ; /* This is ok.  */
02003        else
02004          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
02005 
02006        /* Base insn sizes of all selected isas must be equal
02007           or we set the result to 0, meaning "unknown".  */
02008        if (cd->base_insn_bitsize == UNSET)
02009          cd->base_insn_bitsize = isa->base_insn_bitsize;
02010        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
02011          ; /* This is ok.  */
02012        else
02013          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
02014 
02015        /* Set min,max insn sizes.  */
02016        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
02017          cd->min_insn_bitsize = isa->min_insn_bitsize;
02018        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
02019          cd->max_insn_bitsize = isa->max_insn_bitsize;
02020       }
02021 
02022   /* Data derived from the mach spec.  */
02023   for (i = 0; i < MAX_MACHS; ++i)
02024     if (((1 << i) & machs) != 0)
02025       {
02026        const CGEN_MACH *mach = & iq2000_cgen_mach_table[i];
02027 
02028        if (mach->insn_chunk_bitsize != 0)
02029        {
02030          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
02031            {
02032              fprintf (stderr, "iq2000_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
02033                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
02034              abort ();
02035            }
02036 
02037          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
02038        }
02039       }
02040 
02041   /* Determine which hw elements are used by MACH.  */
02042   build_hw_table (cd);
02043 
02044   /* Build the ifield table.  */
02045   build_ifield_table (cd);
02046 
02047   /* Determine which operands are used by MACH/ISA.  */
02048   build_operand_table (cd);
02049 
02050   /* Build the instruction table.  */
02051   build_insn_table (cd);
02052 }
02053 
02054 /* Initialize a cpu table and return a descriptor.
02055    It's much like opening a file, and must be the first function called.
02056    The arguments are a set of (type/value) pairs, terminated with
02057    CGEN_CPU_OPEN_END.
02058 
02059    Currently supported values:
02060    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
02061    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
02062    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
02063    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
02064    CGEN_CPU_OPEN_END:     terminates arguments
02065 
02066    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
02067    precluded.
02068 
02069    ??? We only support ISO C stdargs here, not K&R.
02070    Laziness, plus experiment to see if anything requires K&R - eventually
02071    K&R will no longer be supported - e.g. GDB is currently trying this.  */
02072 
02073 CGEN_CPU_DESC
02074 iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
02075 {
02076   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
02077   static int init_p;
02078   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
02079   unsigned int machs = 0; /* 0 = "unspecified" */
02080   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
02081   va_list ap;
02082 
02083   if (! init_p)
02084     {
02085       init_tables ();
02086       init_p = 1;
02087     }
02088 
02089   memset (cd, 0, sizeof (*cd));
02090 
02091   va_start (ap, arg_type);
02092   while (arg_type != CGEN_CPU_OPEN_END)
02093     {
02094       switch (arg_type)
02095        {
02096        case CGEN_CPU_OPEN_ISAS :
02097          isas = va_arg (ap, CGEN_BITSET *);
02098          break;
02099        case CGEN_CPU_OPEN_MACHS :
02100          machs = va_arg (ap, unsigned int);
02101          break;
02102        case CGEN_CPU_OPEN_BFDMACH :
02103          {
02104            const char *name = va_arg (ap, const char *);
02105            const CGEN_MACH *mach =
02106              lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name);
02107 
02108            machs |= 1 << mach->num;
02109            break;
02110          }
02111        case CGEN_CPU_OPEN_ENDIAN :
02112          endian = va_arg (ap, enum cgen_endian);
02113          break;
02114        default :
02115          fprintf (stderr, "iq2000_cgen_cpu_open: unsupported argument `%d'\n",
02116                  arg_type);
02117          abort (); /* ??? return NULL? */
02118        }
02119       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
02120     }
02121   va_end (ap);
02122 
02123   /* Mach unspecified means "all".  */
02124   if (machs == 0)
02125     machs = (1 << MAX_MACHS) - 1;
02126   /* Base mach is always selected.  */
02127   machs |= 1;
02128   if (endian == CGEN_ENDIAN_UNKNOWN)
02129     {
02130       /* ??? If target has only one, could have a default.  */
02131       fprintf (stderr, "iq2000_cgen_cpu_open: no endianness specified\n");
02132       abort ();
02133     }
02134 
02135   cd->isas = cgen_bitset_copy (isas);
02136   cd->machs = machs;
02137   cd->endian = endian;
02138   /* FIXME: for the sparc case we can determine insn-endianness statically.
02139      The worry here is where both data and insn endian can be independently
02140      chosen, in which case this function will need another argument.
02141      Actually, will want to allow for more arguments in the future anyway.  */
02142   cd->insn_endian = endian;
02143 
02144   /* Table (re)builder.  */
02145   cd->rebuild_tables = iq2000_cgen_rebuild_tables;
02146   iq2000_cgen_rebuild_tables (cd);
02147 
02148   /* Default to not allowing signed overflow.  */
02149   cd->signed_overflow_ok_p = 0;
02150   
02151   return (CGEN_CPU_DESC) cd;
02152 }
02153 
02154 /* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
02155    MACH_NAME is the bfd name of the mach.  */
02156 
02157 CGEN_CPU_DESC
02158 iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
02159 {
02160   return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
02161                             CGEN_CPU_OPEN_ENDIAN, endian,
02162                             CGEN_CPU_OPEN_END);
02163 }
02164 
02165 /* Close a cpu table.
02166    ??? This can live in a machine independent file, but there's currently
02167    no place to put this file (there's no libcgen).  libopcodes is the wrong
02168    place as some simulator ports use this but they don't use libopcodes.  */
02169 
02170 void
02171 iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
02172 {
02173   unsigned int i;
02174   const CGEN_INSN *insns;
02175 
02176   if (cd->macro_insn_table.init_entries)
02177     {
02178       insns = cd->macro_insn_table.init_entries;
02179       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
02180        if (CGEN_INSN_RX ((insns)))
02181          regfree (CGEN_INSN_RX (insns));
02182     }
02183 
02184   if (cd->insn_table.init_entries)
02185     {
02186       insns = cd->insn_table.init_entries;
02187       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
02188        if (CGEN_INSN_RX (insns))
02189          regfree (CGEN_INSN_RX (insns));
02190     }  
02191 
02192   if (cd->macro_insn_table.init_entries)
02193     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
02194 
02195   if (cd->insn_table.init_entries)
02196     free ((CGEN_INSN *) cd->insn_table.init_entries);
02197 
02198   if (cd->hw_table.entries)
02199     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
02200 
02201   if (cd->operand_table.entries)
02202     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
02203 
02204   free (cd);
02205 }
02206