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cell-binutils  2.17cvs20070401
ip2k-desc.h
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00001 /* CPU data header for ip2k.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef IP2K_CPU_H
00026 #define IP2K_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH ip2k
00031 
00032 /* Given symbol S, return ip2k_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) ip2k##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) ip2k_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_IP2KBF
00042 
00043 #define CGEN_INSN_LSB0_P 1
00044 
00045 /* Minimum size of any insn (in bytes).  */
00046 #define CGEN_MIN_INSN_SIZE 2
00047 
00048 /* Maximum size of any insn (in bytes).  */
00049 #define CGEN_MAX_INSN_SIZE 2
00050 
00051 #define CGEN_INT_INSN_P 1
00052 
00053 /* Maximum number of syntax elements in an instruction.  */
00054 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12
00055 
00056 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00057    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00058    we can't hash on everything up to the space.  */
00059 #define CGEN_MNEMONIC_OPERANDS
00060 
00061 /* Maximum number of fields in an instruction.  */
00062 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3
00063 
00064 /* Enums.  */
00065 
00066 /* Enum declaration for op6 enums.  */
00067 typedef enum insn_op6 {
00068   OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC
00069  , OP6_OR, OP6_AND, OP6_XOR, OP6_ADD
00070  , OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ
00071  , OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ
00072  , OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ
00073  , OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC
00074 } INSN_OP6;
00075 
00076 /* Enum declaration for dir enums.  */
00077 typedef enum insn_dir {
00078   DIR_TO_W, DIR_NOTTO_W
00079 } INSN_DIR;
00080 
00081 /* Enum declaration for op4 enums.  */
00082 typedef enum insn_op4 {
00083   OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10
00084  , OP4_SB = 11
00085 } INSN_OP4;
00086 
00087 /* Enum declaration for op4mid enums.  */
00088 typedef enum insn_op4mid {
00089   OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3
00090  , OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8
00091  , OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12
00092  , OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15
00093 } INSN_OP4MID;
00094 
00095 /* Enum declaration for op3 enums.  */
00096 typedef enum insn_op3 {
00097   OP3_CALL = 6, OP3_JMP = 7
00098 } INSN_OP3;
00099 
00100 /* Enum declaration for .  */
00101 typedef enum register_names {
00102   H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5
00103  , H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9
00104  , H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13
00105  , H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17
00106  , H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21
00107  , H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25
00108  , H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29
00109  , H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33
00110  , H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37
00111  , H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41
00112  , H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45
00113  , H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50
00114  , H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57
00115  , H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66
00116  , H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70
00117  , H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73
00118  , H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76
00119  , H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80
00120  , H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84
00121  , H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88
00122  , H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90
00123  , H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94
00124  , H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98
00125  , H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102
00126  , H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106
00127  , H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110
00128  , H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114
00129  , H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118
00130  , H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122
00131  , H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126
00132  , H_REGISTERS_CALLL = 127
00133 } REGISTER_NAMES;
00134 
00135 /* Attributes.  */
00136 
00137 /* Enum declaration for machine type selection.  */
00138 typedef enum mach_attr {
00139   MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX
00140 } MACH_ATTR;
00141 
00142 /* Enum declaration for instruction set selection.  */
00143 typedef enum isa_attr {
00144   ISA_IP2K, ISA_MAX
00145 } ISA_ATTR;
00146 
00147 /* Number of architecture variants.  */
00148 #define MAX_ISAS  1
00149 #define MAX_MACHS ((int) MACH_MAX)
00150 
00151 /* Ifield support.  */
00152 
00153 /* Ifield attribute indices.  */
00154 
00155 /* Enum declaration for cgen_ifld attrs.  */
00156 typedef enum cgen_ifld_attr {
00157   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00158  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00159  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00160 } CGEN_IFLD_ATTR;
00161 
00162 /* Number of non-boolean elements in cgen_ifld_attr.  */
00163 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00164 
00165 /* cgen_ifld attribute accessor macros.  */
00166 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00167 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00168 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00169 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00170 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00171 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00172 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00173 
00174 /* Enum declaration for ip2k ifield types.  */
00175 typedef enum ifield_type {
00176   IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG
00177  , IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3
00178  , IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8
00179  , IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB
00180  , IP2K_F_PAGE3, IP2K_F_MAX
00181 } IFIELD_TYPE;
00182 
00183 #define MAX_IFLD ((int) IP2K_F_MAX)
00184 
00185 /* Hardware attribute indices.  */
00186 
00187 /* Enum declaration for cgen_hw attrs.  */
00188 typedef enum cgen_hw_attr {
00189   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00190  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00191 } CGEN_HW_ATTR;
00192 
00193 /* Number of non-boolean elements in cgen_hw_attr.  */
00194 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00195 
00196 /* cgen_hw attribute accessor macros.  */
00197 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00198 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00199 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00200 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00201 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00202 
00203 /* Enum declaration for ip2k hardware types.  */
00204 typedef enum cgen_hw_type {
00205   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00206  , HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK
00207  , HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT
00208  , HW_H_PC, HW_MAX
00209 } CGEN_HW_TYPE;
00210 
00211 #define MAX_HW ((int) HW_MAX)
00212 
00213 /* Operand attribute indices.  */
00214 
00215 /* Enum declaration for cgen_operand attrs.  */
00216 typedef enum cgen_operand_attr {
00217   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00218  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00219  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00220 } CGEN_OPERAND_ATTR;
00221 
00222 /* Number of non-boolean elements in cgen_operand_attr.  */
00223 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00224 
00225 /* cgen_operand attribute accessor macros.  */
00226 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00227 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00228 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00229 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00230 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00231 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00232 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00233 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00234 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00235 
00236 /* Enum declaration for ip2k operand types.  */
00237 typedef enum cgen_operand_type {
00238   IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8
00239  , IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L
00240  , IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT
00241  , IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX
00242 } CGEN_OPERAND_TYPE;
00243 
00244 /* Number of operands types.  */
00245 #define MAX_OPERANDS 13
00246 
00247 /* Maximum number of operands referenced by any insn.  */
00248 #define MAX_OPERAND_INSTANCES 8
00249 
00250 /* Insn attribute indices.  */
00251 
00252 /* Enum declaration for cgen_insn attrs.  */
00253 typedef enum cgen_insn_attr {
00254   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00255  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00256  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
00257  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
00258 } CGEN_INSN_ATTR;
00259 
00260 /* Number of non-boolean elements in cgen_insn_attr.  */
00261 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00262 
00263 /* cgen_insn attribute accessor macros.  */
00264 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00265 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00266 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00267 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00268 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00269 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00270 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00271 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00272 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00273 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00274 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00275 #define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0)
00276 #define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0)
00277 
00278 /* cgen.h uses things we just defined.  */
00279 #include "opcode/cgen.h"
00280 
00281 extern const struct cgen_ifld ip2k_cgen_ifld_table[];
00282 
00283 /* Attributes.  */
00284 extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[];
00285 extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[];
00286 extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[];
00287 extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[];
00288 
00289 /* Hardware decls.  */
00290 
00291 
00292 extern const CGEN_HW_ENTRY ip2k_cgen_hw_table[];
00293 
00294 
00295 
00296 #endif /* IP2K_CPU_H */