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cgen.h
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00001 /* Header file for targets using CGEN: Cpu tools GENerator.
00002 
00003 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
00004 Free Software Foundation, Inc.
00005 
00006 This file is part of GDB, the GNU debugger, and the GNU Binutils.
00007 
00008 This program is free software; you can redistribute it and/or modify
00009 it under the terms of the GNU General Public License as published by
00010 the Free Software Foundation; either version 2 of the License, or
00011 (at your option) any later version.
00012 
00013 This program is distributed in the hope that it will be useful,
00014 but WITHOUT ANY WARRANTY; without even the implied warranty of
00015 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016 GNU General Public License for more details.
00017 
00018 You should have received a copy of the GNU General Public License along
00019 with this program; if not, write to the Free Software Foundation, Inc.,
00020 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00021 
00022 #ifndef CGEN_H
00023 #define CGEN_H
00024 
00025 #include "symcat.h"
00026 #include "cgen-bitset.h"
00027 /* ??? This file requires bfd.h but only to get bfd_vma.
00028    Seems like an awful lot to require just to get such a fundamental type.
00029    Perhaps the definition of bfd_vma can be moved outside of bfd.h.
00030    Or perhaps one could duplicate its definition in another file.
00031    Until such time, this file conditionally compiles definitions that require
00032    bfd_vma using __BFD_H_SEEN__.  */
00033 
00034 /* Enums must be defined before they can be used.
00035    Allow them to be used in struct definitions, even though the enum must
00036    be defined elsewhere.
00037    If CGEN_ARCH isn't defined, this file is being included by something other
00038    than <arch>-desc.h.  */
00039 
00040 /* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S.
00041    The lack of spaces in the arg list is important for non-stdc systems.
00042    This file is included by <arch>-desc.h.
00043    It can be included independently of <arch>-desc.h, in which case the arch
00044    dependent portions will be declared as "unknown_cgen_foo".  */
00045 
00046 #ifndef CGEN_SYM
00047 #define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
00048 #endif
00049 
00050 /* This file contains the static (unchanging) pieces and as much other stuff
00051    as we can reasonably put here.  It's generally cleaner to put stuff here
00052    rather than having it machine generated if possible.  */
00053 
00054 /* The assembler syntax is made up of expressions (duh...).
00055    At the lowest level the values are mnemonics, register names, numbers, etc.
00056    Above that are subexpressions, if any (an example might be the
00057    "effective address" in m68k cpus).  Subexpressions are wip.
00058    At the second highest level are the insns themselves.  Above that are
00059    pseudo-insns, synthetic insns, and macros, if any.  */
00060 
00061 /* Lots of cpu's have a fixed insn size, or one which rarely changes,
00062    and it's generally easier to handle these by treating the insn as an
00063    integer type, rather than an array of characters.  So we allow targets
00064    to control this.  When an integer type the value is in host byte order,
00065    when an array of characters the value is in target byte order.  */
00066 
00067 typedef unsigned int CGEN_INSN_INT;
00068 #if CGEN_INT_INSN_P
00069 typedef CGEN_INSN_INT CGEN_INSN_BYTES;
00070 typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR;
00071 #else
00072 typedef unsigned char *CGEN_INSN_BYTES;
00073 typedef unsigned char *CGEN_INSN_BYTES_PTR;
00074 #endif
00075 
00076 #ifdef __GNUC__
00077 #define CGEN_INLINE __inline__
00078 #else
00079 #define CGEN_INLINE
00080 #endif
00081 
00082 enum cgen_endian
00083 {
00084   CGEN_ENDIAN_UNKNOWN,
00085   CGEN_ENDIAN_LITTLE,
00086   CGEN_ENDIAN_BIG
00087 };
00088 
00089 /* Forward decl.  */
00090 
00091 typedef struct cgen_insn CGEN_INSN;
00092 
00093 /* Opaque pointer version for use by external world.  */
00094 
00095 typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
00096 
00097 /* Attributes.
00098    Attributes are used to describe various random things associated with
00099    an object (ifield, hardware, operand, insn, whatever) and are specified
00100    as name/value pairs.
00101    Integer attributes computed at compile time are currently all that's
00102    supported, though adding string attributes and run-time computation is
00103    straightforward.  Integer attribute values are always host int's
00104    (signed or unsigned).  For portability, this means 32 bits.
00105    Integer attributes are further categorized as boolean, bitset, integer,
00106    and enum types.  Boolean attributes appear frequently enough that they're
00107    recorded in one host int.  This limits the maximum number of boolean
00108    attributes to 32, though that's a *lot* of attributes.  */
00109 
00110 /* Type of attribute values.  */
00111 
00112 typedef CGEN_BITSET     CGEN_ATTR_VALUE_BITSET_TYPE;
00113 typedef int             CGEN_ATTR_VALUE_ENUM_TYPE;
00114 typedef union
00115 {
00116   CGEN_ATTR_VALUE_BITSET_TYPE bitset;
00117   CGEN_ATTR_VALUE_ENUM_TYPE   nonbitset;
00118 } CGEN_ATTR_VALUE_TYPE;
00119 
00120 /* Struct to record attribute information.  */
00121 
00122 typedef struct
00123 {
00124   /* Boolean attributes.  */
00125   unsigned int bool;
00126   /* Non-boolean integer attributes.  */
00127   CGEN_ATTR_VALUE_TYPE nonbool[1];
00128 } CGEN_ATTR;
00129 
00130 /* Define a structure member for attributes with N non-boolean entries.
00131    There is no maximum number of non-boolean attributes.
00132    There is a maximum of 32 boolean attributes (since they are all recorded
00133    in one host int).  */
00134 
00135 #define CGEN_ATTR_TYPE(n) \
00136 struct { unsigned int bool; \
00137         CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
00138 
00139 /* Return the boolean attributes.  */
00140 
00141 #define CGEN_ATTR_BOOLS(a) ((a)->bool)
00142 
00143 /* Non-boolean attribute numbers are offset by this much.  */
00144 
00145 #define CGEN_ATTR_NBOOL_OFFSET 32
00146 
00147 /* Given a boolean attribute number, return its mask.  */
00148 
00149 #define CGEN_ATTR_MASK(attr) (1 << (attr))
00150 
00151 /* Return the value of boolean attribute ATTR in ATTRS.  */
00152 
00153 #define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
00154 
00155 /* Return value of attribute ATTR in ATTR_TABLE for OBJ.
00156    OBJ is a pointer to the entity that has the attributes
00157    (??? not used at present but is reserved for future purposes - eventually
00158    the goal is to allow recording attributes in source form and computing
00159    them lazily at runtime, not sure of the details yet).  */
00160 
00161 #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
00162 ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
00163  ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
00164  : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
00165 #define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
00166  ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
00167 
00168 /* Attribute name/value tables.
00169    These are used to assist parsing of descriptions at run-time.  */
00170 
00171 typedef struct
00172 {
00173   const char * name;
00174   unsigned value;
00175 } CGEN_ATTR_ENTRY;
00176 
00177 /* For each domain (ifld,hw,operand,insn), list of attributes.  */
00178 
00179 typedef struct
00180 {
00181   const char * name;
00182   const CGEN_ATTR_ENTRY * dfault;
00183   const CGEN_ATTR_ENTRY * vals;
00184 } CGEN_ATTR_TABLE;
00185 
00186 /* Instruction set variants.  */
00187 
00188 typedef struct {
00189   const char *name;
00190 
00191   /* Default instruction size (in bits).
00192      This is used by the assembler when it encounters an unknown insn.  */
00193   unsigned int default_insn_bitsize;
00194 
00195   /* Base instruction size (in bits).
00196      For non-LIW cpus this is generally the length of the smallest insn.
00197      For LIW cpus its wip (work-in-progress).  For the m32r its 32.  */
00198   unsigned int base_insn_bitsize;
00199 
00200   /* Minimum/maximum instruction size (in bits).  */
00201   unsigned int min_insn_bitsize;
00202   unsigned int max_insn_bitsize;
00203 } CGEN_ISA;
00204 
00205 /* Machine variants.  */
00206 
00207 typedef struct {
00208   const char *name;
00209   /* The argument to bfd_arch_info->scan.  */
00210   const char *bfd_name;
00211   /* one of enum mach_attr */
00212   int num;
00213   /* parameter from mach->cpu */
00214   unsigned int insn_chunk_bitsize;
00215 } CGEN_MACH;
00216 
00217 /* Parse result (also extraction result).
00218 
00219    The result of parsing an insn is stored here.
00220    To generate the actual insn, this is passed to the insert handler.
00221    When printing an insn, the result of extraction is stored here.
00222    To print the insn, this is passed to the print handler.
00223 
00224    It is machine generated so we don't define it here,
00225    but we do need a forward decl for the handler fns.
00226 
00227    There is one member for each possible field in the insn.
00228    The type depends on the field.
00229    Also recorded here is the computed length of the insn for architectures
00230    where it varies.
00231 */
00232 
00233 typedef struct cgen_fields CGEN_FIELDS;
00234 
00235 /* Total length of the insn, as recorded in the `fields' struct.  */
00236 /* ??? The field insert handler has lots of opportunities for optimization
00237    if it ever gets inlined.  On architectures where insns all have the same
00238    size, may wish to detect that and make this macro a constant - to allow
00239    further optimizations.  */
00240 
00241 #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
00242 
00243 /* Extraction support for variable length insn sets.  */
00244 
00245 /* When disassembling we don't know the number of bytes to read at the start.
00246    So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest
00247    are read when needed.  This struct controls this.  It is basically the
00248    disassemble_info stuff, except that we provide a cache for values already
00249    read (since bytes can typically be read several times to fetch multiple
00250    operands that may be in them), and that extraction of fields is needed
00251    in contexts other than disassembly.  */
00252 
00253 typedef struct {
00254   /* A pointer to the disassemble_info struct.
00255      We don't require dis-asm.h so we use void * for the type here.
00256      If NULL, BYTES is full of valid data (VALID == -1).  */
00257   void *dis_info;
00258   /* Points to a working buffer of sufficient size.  */
00259   unsigned char *insn_bytes;
00260   /* Mask of bytes that are valid in INSN_BYTES.  */
00261   unsigned int valid;
00262 } CGEN_EXTRACT_INFO;
00263 
00264 /* Associated with each insn or expression is a set of "handlers" for
00265    performing operations like parsing, printing, etc.  These require a bfd_vma
00266    value to be passed around but we don't want all applications to need bfd.h.
00267    So this stuff is only provided if bfd.h has been included.  */
00268 
00269 /* Parse handler.
00270    CD is a cpu table descriptor.
00271    INSN is a pointer to a struct describing the insn being parsed.
00272    STRP is a pointer to a pointer to the text being parsed.
00273    FIELDS is a pointer to a cgen_fields struct in which the results are placed.
00274    If the expression is successfully parsed, *STRP is updated.
00275    If not it is left alone.
00276    The result is NULL if success or an error message.  */
00277 typedef const char * (cgen_parse_fn)
00278   (CGEN_CPU_DESC, const CGEN_INSN *insn_,
00279    const char **strp_, CGEN_FIELDS *fields_);
00280 
00281 /* Insert handler.
00282    CD is a cpu table descriptor.
00283    INSN is a pointer to a struct describing the insn being parsed.
00284    FIELDS is a pointer to a cgen_fields struct from which the values
00285    are fetched.
00286    INSNP is a pointer to a buffer in which to place the insn.
00287    PC is the pc value of the insn.
00288    The result is an error message or NULL if success.  */
00289 
00290 #ifdef __BFD_H_SEEN__
00291 typedef const char * (cgen_insert_fn)
00292   (CGEN_CPU_DESC, const CGEN_INSN *insn_,
00293    CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_,
00294    bfd_vma pc_);
00295 #else
00296 typedef const char * (cgen_insert_fn) ();
00297 #endif
00298 
00299 /* Extract handler.
00300    CD is a cpu table descriptor.
00301    INSN is a pointer to a struct describing the insn being parsed.
00302    The second argument is a pointer to a struct controlling extraction
00303    (only used for variable length insns).
00304    EX_INFO is a pointer to a struct for controlling reading of further
00305    bytes for the insn.
00306    BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order).
00307    FIELDS is a pointer to a cgen_fields struct in which the results are placed.
00308    PC is the pc value of the insn.
00309    The result is the length of the insn in bits or zero if not recognized.  */
00310 
00311 #ifdef __BFD_H_SEEN__
00312 typedef int (cgen_extract_fn)
00313   (CGEN_CPU_DESC, const CGEN_INSN *insn_,
00314    CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_,
00315    CGEN_FIELDS *fields_, bfd_vma pc_);
00316 #else
00317 typedef int (cgen_extract_fn) ();
00318 #endif
00319 
00320 /* Print handler.
00321    CD is a cpu table descriptor.
00322    INFO is a pointer to the disassembly info.
00323    Eg: disassemble_info.  It's defined as `PTR' so this file can be included
00324    without dis-asm.h.
00325    INSN is a pointer to a struct describing the insn being printed.
00326    FIELDS is a pointer to a cgen_fields struct.
00327    PC is the pc value of the insn.
00328    LEN is the length of the insn, in bits.  */
00329 
00330 #ifdef __BFD_H_SEEN__
00331 typedef void (cgen_print_fn)
00332   (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_,
00333    CGEN_FIELDS *fields_, bfd_vma pc_, int len_);
00334 #else
00335 typedef void (cgen_print_fn) ();
00336 #endif
00337 
00338 /* Parse/insert/extract/print handlers.
00339 
00340    Indices into the handler tables.
00341    We could use pointers here instead, but 90% of them are generally identical
00342    and that's a lot of redundant data.  Making these unsigned char indices
00343    into tables of pointers saves a bit of space.
00344    Using indices also keeps assembler code out of the disassembler and
00345    vice versa.  */
00346 
00347 struct cgen_opcode_handler
00348 {
00349   unsigned char parse, insert, extract, print;
00350 };
00351 
00352 /* Assembler interface.
00353 
00354    The interface to the assembler is intended to be clean in the sense that
00355    libopcodes.a is a standalone entity and could be used with any assembler.
00356    Not that one would necessarily want to do that but rather that it helps
00357    keep a clean interface.  The interface will obviously be slanted towards
00358    GAS, but at least it's a start.
00359    ??? Note that one possible user of the assembler besides GAS is GDB.
00360 
00361    Parsing is controlled by the assembler which calls
00362    CGEN_SYM (assemble_insn).  If it can parse and build the entire insn
00363    it doesn't call back to the assembler.  If it needs/wants to call back
00364    to the assembler, cgen_parse_operand_fn is called which can either
00365 
00366    - return a number to be inserted in the insn
00367    - return a "register" value to be inserted
00368      (the register might not be a register per pe)
00369    - queue the argument and return a marker saying the expression has been
00370      queued (eg: a fix-up)
00371    - return an error message indicating the expression wasn't recognizable
00372 
00373    The result is an error message or NULL for success.
00374    The parsed value is stored in the bfd_vma *.  */
00375 
00376 /* Values for indicating what the caller wants.  */
00377 
00378 enum cgen_parse_operand_type
00379 {
00380   CGEN_PARSE_OPERAND_INIT,
00381   CGEN_PARSE_OPERAND_INTEGER,
00382   CGEN_PARSE_OPERAND_ADDRESS,
00383   CGEN_PARSE_OPERAND_SYMBOLIC
00384 };
00385 
00386 /* Values for indicating what was parsed.  */
00387 
00388 enum cgen_parse_operand_result
00389 {
00390   CGEN_PARSE_OPERAND_RESULT_NUMBER,
00391   CGEN_PARSE_OPERAND_RESULT_REGISTER,
00392   CGEN_PARSE_OPERAND_RESULT_QUEUED,
00393   CGEN_PARSE_OPERAND_RESULT_ERROR
00394 };
00395 
00396 #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
00397 typedef const char * (cgen_parse_operand_fn)
00398   (CGEN_CPU_DESC,
00399    enum cgen_parse_operand_type, const char **, int, int,
00400    enum cgen_parse_operand_result *, bfd_vma *);
00401 #else
00402 typedef const char * (cgen_parse_operand_fn) ();
00403 #endif
00404 
00405 /* Set the cgen_parse_operand_fn callback.  */
00406 
00407 extern void cgen_set_parse_operand_fn
00408   (CGEN_CPU_DESC, cgen_parse_operand_fn);
00409 
00410 /* Called before trying to match a table entry with the insn.  */
00411 
00412 extern void cgen_init_parse_operand (CGEN_CPU_DESC);
00413 
00414 /* Operand values (keywords, integers, symbols, etc.)  */
00415 
00416 /* Types of assembler elements.  */
00417 
00418 enum cgen_asm_type
00419 {
00420   CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX
00421 };
00422 
00423 #ifndef CGEN_ARCH
00424 enum cgen_hw_type { CGEN_HW_MAX };
00425 #endif
00426 
00427 /* List of hardware elements.  */
00428 
00429 typedef struct
00430 {
00431   char *name;
00432   enum cgen_hw_type type;
00433   /* There is currently no example where both index specs and value specs
00434      are required, so for now both are clumped under "asm_data".  */
00435   enum cgen_asm_type asm_type;
00436   void *asm_data;
00437 #ifndef CGEN_HW_NBOOL_ATTRS
00438 #define CGEN_HW_NBOOL_ATTRS 1
00439 #endif
00440   CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs;
00441 #define CGEN_HW_ATTRS(hw) (&(hw)->attrs)
00442 } CGEN_HW_ENTRY;
00443 
00444 /* Return value of attribute ATTR in HW.  */
00445 
00446 #define CGEN_HW_ATTR_VALUE(hw, attr) \
00447 CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
00448 
00449 /* Table of hardware elements for selected mach, computed at runtime.
00450    enum cgen_hw_type is an index into this table (specifically `entries').  */
00451 
00452 typedef struct {
00453   /* Pointer to null terminated table of all compiled in entries.  */
00454   const CGEN_HW_ENTRY *init_entries;
00455   unsigned int entry_size; /* since the attribute member is variable sized */
00456   /* Array of all entries, initial and run-time added.  */
00457   const CGEN_HW_ENTRY **entries;
00458   /* Number of elements in `entries'.  */
00459   unsigned int num_entries;
00460   /* For now, xrealloc is called each time a new entry is added at runtime.
00461      ??? May wish to keep track of some slop to reduce the number of calls to
00462      xrealloc, except that there's unlikely to be many and not expected to be
00463      in speed critical code.  */
00464 } CGEN_HW_TABLE;
00465 
00466 extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name
00467   (CGEN_CPU_DESC, const char *);
00468 extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num
00469   (CGEN_CPU_DESC, unsigned int);
00470 
00471 /* This struct is used to describe things like register names, etc.  */
00472 
00473 typedef struct cgen_keyword_entry
00474 {
00475   /* Name (as in register name).  */
00476   char * name;
00477 
00478   /* Value (as in register number).
00479      The value cannot be -1 as that is used to indicate "not found".
00480      IDEA: Have "FUNCTION" attribute? [function is called to fetch value].  */
00481   int value;
00482 
00483   /* Attributes.
00484      This should, but technically needn't, appear last.  It is a variable sized
00485      array in that one architecture may have 1 nonbool attribute and another
00486      may have more.  Having this last means the non-architecture specific code
00487      needn't care.  The goal is to eventually record
00488      attributes in their raw form, evaluate them at run-time, and cache the
00489      values, so this worry will go away anyway.  */
00490   /* ??? Moving this last should be done by treating keywords like insn lists
00491      and moving the `next' fields into a CGEN_KEYWORD_LIST struct.  */
00492   /* FIXME: Not used yet.  */
00493 #ifndef CGEN_KEYWORD_NBOOL_ATTRS
00494 #define CGEN_KEYWORD_NBOOL_ATTRS 1
00495 #endif
00496   CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs;
00497 
00498   /* ??? Putting these here means compiled in entries can't be const.
00499      Not a really big deal, but something to consider.  */
00500   /* Next name hash table entry.  */
00501   struct cgen_keyword_entry *next_name;
00502   /* Next value hash table entry.  */
00503   struct cgen_keyword_entry *next_value;
00504 } CGEN_KEYWORD_ENTRY;
00505 
00506 /* Top level struct for describing a set of related keywords
00507    (e.g. register names).
00508 
00509    This struct supports run-time entry of new values, and hashed lookups.  */
00510 
00511 typedef struct cgen_keyword
00512 {
00513   /* Pointer to initial [compiled in] values.  */
00514   CGEN_KEYWORD_ENTRY *init_entries;
00515   
00516   /* Number of entries in `init_entries'.  */
00517   unsigned int num_init_entries;
00518   
00519   /* Hash table used for name lookup.  */
00520   CGEN_KEYWORD_ENTRY **name_hash_table;
00521   
00522   /* Hash table used for value lookup.  */
00523   CGEN_KEYWORD_ENTRY **value_hash_table;
00524   
00525   /* Number of entries in the hash_tables.  */
00526   unsigned int hash_table_size;
00527   
00528   /* Pointer to null keyword "" entry if present.  */
00529   const CGEN_KEYWORD_ENTRY *null_entry;
00530 
00531   /* String containing non-alphanumeric characters used
00532      in keywords.  
00533      At present, the highest number of entries used is 1.  */
00534   char nonalpha_chars[8];
00535 } CGEN_KEYWORD;
00536 
00537 /* Structure used for searching.  */
00538 
00539 typedef struct
00540 {
00541   /* Table being searched.  */
00542   const CGEN_KEYWORD *table;
00543   
00544   /* Specification of what is being searched for.  */
00545   const char *spec;
00546   
00547   /* Current index in hash table.  */
00548   unsigned int current_hash;
00549   
00550   /* Current element in current hash chain.  */
00551   CGEN_KEYWORD_ENTRY *current_entry;
00552 } CGEN_KEYWORD_SEARCH;
00553 
00554 /* Lookup a keyword from its name.  */
00555 
00556 const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name
00557   (CGEN_KEYWORD *, const char *);
00558 
00559 /* Lookup a keyword from its value.  */
00560 
00561 const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value
00562   (CGEN_KEYWORD *, int);
00563 
00564 /* Add a keyword.  */
00565 
00566 void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *);
00567 
00568 /* Keyword searching.
00569    This can be used to retrieve every keyword, or a subset.  */
00570 
00571 CGEN_KEYWORD_SEARCH cgen_keyword_search_init
00572   (CGEN_KEYWORD *, const char *);
00573 const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next
00574   (CGEN_KEYWORD_SEARCH *);
00575 
00576 /* Operand value support routines.  */
00577 
00578 extern const char *cgen_parse_keyword
00579   (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
00580 #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
00581 extern const char *cgen_parse_signed_integer
00582   (CGEN_CPU_DESC, const char **, int, long *);
00583 extern const char *cgen_parse_unsigned_integer
00584   (CGEN_CPU_DESC, const char **, int, unsigned long *);
00585 extern const char *cgen_parse_address
00586   (CGEN_CPU_DESC, const char **, int, int,
00587    enum cgen_parse_operand_result *, bfd_vma *);
00588 extern const char *cgen_validate_signed_integer
00589   (long, long, long);
00590 extern const char *cgen_validate_unsigned_integer
00591   (unsigned long, unsigned long, unsigned long);
00592 #endif
00593 
00594 /* Operand modes.  */
00595 
00596 /* ??? This duplicates the values in arch.h.  Revisit.
00597    These however need the CGEN_ prefix [as does everything in this file].  */
00598 /* ??? Targets may need to add their own modes so we may wish to move this
00599    to <arch>-opc.h, or add a hook.  */
00600 
00601 enum cgen_mode {
00602   CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */
00603   CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI,
00604   CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI,
00605   CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF,
00606   CGEN_MODE_TARGET_MAX,
00607   CGEN_MODE_INT, CGEN_MODE_UINT,
00608   CGEN_MODE_MAX
00609 };
00610 
00611 /* FIXME: Until simulator is updated.  */
00612 
00613 #define CGEN_MODE_VM CGEN_MODE_VOID
00614 
00615 /* Operands.  */
00616 
00617 #ifndef CGEN_ARCH
00618 enum cgen_operand_type { CGEN_OPERAND_MAX };
00619 #endif
00620 
00621 /* "nil" indicator for the operand instance table */
00622 #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
00623 
00624 /* A tree of these structs represents the multi-ifield
00625    structure of an operand's hw-index value, if it exists.  */
00626 
00627 struct cgen_ifld;
00628 
00629 typedef struct cgen_maybe_multi_ifield
00630 {
00631   int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
00632               n: indexed by array of more cgen_maybe_multi_ifields.  */
00633   union
00634   {
00635     const void *p;
00636     const struct cgen_maybe_multi_ifield * multi;
00637     const struct cgen_ifld * leaf;
00638   } val;
00639 }
00640 CGEN_MAYBE_MULTI_IFLD;
00641 
00642 /* This struct defines each entry in the operand table.  */
00643 
00644 typedef struct
00645 {
00646   /* Name as it appears in the syntax string.  */
00647   char *name;
00648 
00649   /* Operand type.  */
00650   enum cgen_operand_type type;
00651 
00652   /* The hardware element associated with this operand.  */
00653   enum cgen_hw_type hw_type;
00654 
00655   /* FIXME: We don't yet record ifield definitions, which we should.
00656      When we do it might make sense to delete start/length (since they will
00657      be duplicated in the ifield's definition) and replace them with a
00658      pointer to the ifield entry.  */
00659 
00660   /* Bit position.
00661      This is just a hint, and may be unused in more complex operands.
00662      May be unused for a modifier.  */
00663   unsigned char start;
00664 
00665   /* The number of bits in the operand.
00666      This is just a hint, and may be unused in more complex operands.
00667      May be unused for a modifier.  */
00668   unsigned char length;
00669 
00670   /* The (possibly-multi) ifield used as an index for this operand, if it
00671      is indexed by a field at all. This substitutes / extends the start and
00672      length fields above, but unsure at this time whether they are used
00673      anywhere.  */
00674   CGEN_MAYBE_MULTI_IFLD index_fields;
00675 #if 0 /* ??? Interesting idea but relocs tend to get too complicated,
00676         and ABI dependent, for simple table lookups to work.  */
00677   /* Ideally this would be the internal (external?) reloc type.  */
00678   int reloc_type;
00679 #endif
00680 
00681   /* Attributes.
00682      This should, but technically needn't, appear last.  It is a variable sized
00683      array in that one architecture may have 1 nonbool attribute and another
00684      may have more.  Having this last means the non-architecture specific code
00685      needn't care, now or tomorrow.  The goal is to eventually record
00686      attributes in their raw form, evaluate them at run-time, and cache the
00687      values, so this worry will go away anyway.  */
00688 #ifndef CGEN_OPERAND_NBOOL_ATTRS
00689 #define CGEN_OPERAND_NBOOL_ATTRS 1
00690 #endif
00691   CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs;
00692 #define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
00693 } CGEN_OPERAND;
00694 
00695 /* Return value of attribute ATTR in OPERAND.  */
00696 
00697 #define CGEN_OPERAND_ATTR_VALUE(operand, attr) \
00698 CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
00699 
00700 /* Table of operands for selected mach/isa, computed at runtime.
00701    enum cgen_operand_type is an index into this table (specifically
00702    `entries').  */
00703 
00704 typedef struct {
00705   /* Pointer to null terminated table of all compiled in entries.  */
00706   const CGEN_OPERAND *init_entries;
00707   unsigned int entry_size; /* since the attribute member is variable sized */
00708   /* Array of all entries, initial and run-time added.  */
00709   const CGEN_OPERAND **entries;
00710   /* Number of elements in `entries'.  */
00711   unsigned int num_entries;
00712   /* For now, xrealloc is called each time a new entry is added at runtime.
00713      ??? May wish to keep track of some slop to reduce the number of calls to
00714      xrealloc, except that there's unlikely to be many and not expected to be
00715      in speed critical code.  */
00716 } CGEN_OPERAND_TABLE;
00717 
00718 extern const CGEN_OPERAND * cgen_operand_lookup_by_name
00719   (CGEN_CPU_DESC, const char *);
00720 extern const CGEN_OPERAND * cgen_operand_lookup_by_num
00721   (CGEN_CPU_DESC, int);
00722 
00723 /* Instruction operand instances.
00724 
00725    For each instruction, a list of the hardware elements that are read and
00726    written are recorded.  */
00727 
00728 /* The type of the instance.  */
00729 
00730 enum cgen_opinst_type {
00731   /* End of table marker.  */
00732   CGEN_OPINST_END = 0,
00733   CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT
00734 };
00735 
00736 typedef struct
00737 {
00738   /* Input or output indicator.  */
00739   enum cgen_opinst_type type;
00740 
00741   /* Name of operand.  */
00742   const char *name;
00743 
00744   /* The hardware element referenced.  */
00745   enum cgen_hw_type hw_type;
00746 
00747   /* The mode in which the operand is being used.  */
00748   enum cgen_mode mode;
00749 
00750   /* The operand table entry CGEN_OPERAND_NIL if there is none
00751      (i.e. an explicit hardware reference).  */
00752   enum cgen_operand_type op_type;
00753 
00754   /* If `operand' is "nil", the index (e.g. into array of registers).  */
00755   int index;
00756 
00757   /* Attributes.
00758      ??? This perhaps should be a real attribute struct but there's
00759      no current need, so we save a bit of space and just have a set of
00760      flags.  The interface is such that this can easily be made attributes
00761      should it prove useful.  */
00762   unsigned int attrs;
00763 #define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs)
00764 /* Return value of attribute ATTR in OPINST.  */
00765 #define CGEN_OPINST_ATTR(opinst, attr) \
00766 ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
00767 /* Operand is conditionally referenced (read/written).  */
00768 #define CGEN_OPINST_COND_REF 1
00769 } CGEN_OPINST;
00770 
00771 /* Syntax string.
00772 
00773    Each insn format and subexpression has one of these.
00774 
00775    The syntax "string" consists of characters (n > 0 && n < 128), and operand
00776    values (n >= 128), and is terminated by 0.  Operand values are 128 + index
00777    into the operand table.  The operand table doesn't exist in C, per se, as
00778    the data is recorded in the parse/insert/extract/print switch statements. */
00779 
00780 /* This should be at least as large as necessary for any target. */
00781 #define CGEN_MAX_SYNTAX_ELEMENTS 48
00782 
00783 /* A target may know its own precise maximum.  Assert that it falls below
00784    the above limit. */
00785 #ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
00786 #if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
00787 #error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
00788 #endif
00789 #endif
00790 
00791 typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
00792 
00793 typedef struct
00794 {
00795   CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS];
00796 } CGEN_SYNTAX;
00797 
00798 #define CGEN_SYNTAX_STRING(syn) (syn->syntax)
00799 #define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
00800 #define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
00801 #define CGEN_SYNTAX_FIELD(c) ((c) - 128)
00802 #define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
00803 
00804 /* ??? I can't currently think of any case where the mnemonic doesn't come
00805    first [and if one ever doesn't building the hash tables will be tricky].
00806    However, we treat mnemonics as just another operand of the instruction.
00807    A value of 1 means "this is where the mnemonic appears".  1 isn't
00808    special other than it's a non-printable ASCII char.  */
00809 
00810 #define CGEN_SYNTAX_MNEMONIC       1
00811 #define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
00812 
00813 /* Instruction fields.
00814 
00815    ??? We currently don't allow adding fields at run-time.
00816    Easy to fix when needed.  */
00817 
00818 typedef struct cgen_ifld {
00819   /* Enum of ifield.  */
00820   int num;
00821 #define CGEN_IFLD_NUM(f) ((f)->num)
00822 
00823   /* Name of the field, distinguishes it from all other fields.  */
00824   const char *name;
00825 #define CGEN_IFLD_NAME(f) ((f)->name)
00826 
00827   /* Default offset, in bits, from the start of the insn to the word
00828      containing the field.  */
00829   int word_offset;
00830 #define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset)
00831 
00832   /* Default length of the word containing the field.  */
00833   int word_size;
00834 #define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size)
00835 
00836   /* Default starting bit number.
00837      Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P.  */
00838   int start;
00839 #define CGEN_IFLD_START(f) ((f)->start)
00840 
00841   /* Length of the field, in bits.  */
00842   int length;
00843 #define CGEN_IFLD_LENGTH(f) ((f)->length)
00844 
00845 #ifndef CGEN_IFLD_NBOOL_ATTRS
00846 #define CGEN_IFLD_NBOOL_ATTRS 1
00847 #endif
00848   CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs;
00849 #define CGEN_IFLD_ATTRS(f) (&(f)->attrs)
00850 } CGEN_IFLD;
00851 
00852 /* Return value of attribute ATTR in IFLD.  */
00853 #define CGEN_IFLD_ATTR_VALUE(ifld, attr) \
00854 CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
00855 
00856 /* Instruction data.  */
00857 
00858 /* Instruction formats.
00859 
00860    Instructions are grouped by format.  Associated with an instruction is its
00861    format.  Each insn's opcode table entry contains a format table entry.
00862    ??? There is usually very few formats compared with the number of insns,
00863    so one can reduce the size of the opcode table by recording the format table
00864    as a separate entity.  Given that we currently don't, format table entries
00865    are also distinguished by their operands.  This increases the size of the
00866    table, but reduces the number of tables.  It's all minutiae anyway so it
00867    doesn't really matter [at this point in time].
00868 
00869    ??? Support for variable length ISA's is wip.  */
00870 
00871 /* Accompanying each iformat description is a list of its fields.  */
00872 
00873 typedef struct {
00874   const CGEN_IFLD *ifld;
00875 #define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
00876 } CGEN_IFMT_IFLD;
00877 
00878 /* This should be at least as large as necessary for any target. */
00879 #define CGEN_MAX_IFMT_OPERANDS 16
00880 
00881 /* A target may know its own precise maximum.  Assert that it falls below
00882    the above limit. */
00883 #ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
00884 #if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
00885 #error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
00886 #endif
00887 #endif
00888 
00889 
00890 typedef struct
00891 {
00892   /* Length that MASK and VALUE have been calculated to
00893      [VALUE is recorded elsewhere].
00894      Normally it is base_insn_bitsize.  On [V]LIW architectures where the base
00895      insn size may be larger than the size of an insn, this field is less than
00896      base_insn_bitsize.  */
00897   unsigned char mask_length;
00898 #define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length)
00899 
00900   /* Total length of instruction, in bits.  */
00901   unsigned char length;
00902 #define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length)
00903 
00904   /* Mask to apply to the first MASK_LENGTH bits.
00905      Each insn's value is stored with the insn.
00906      The first step in recognizing an insn for disassembly is
00907      (opcode & mask) == value.  */
00908   CGEN_INSN_INT mask;
00909 #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
00910 
00911   /* Instruction fields.
00912      +1 for trailing NULL.  */
00913   CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1];
00914 #define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds)
00915 } CGEN_IFMT;
00916 
00917 /* Instruction values.  */
00918 
00919 typedef struct
00920 {
00921   /* The opcode portion of the base insn.  */
00922   CGEN_INSN_INT base_value;
00923 
00924 #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS
00925   /* Extra opcode values beyond base_value.  */
00926   unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS];
00927 #endif
00928 } CGEN_IVALUE;
00929 
00930 /* Instruction opcode table.
00931    This contains the syntax and format data of an instruction.  */
00932 
00933 /* ??? Some ports already have an opcode table yet still need to use the rest
00934    of what cgen_insn has.  Plus keeping the opcode data with the operand
00935    instance data can create a pretty big file.  So we keep them separately.
00936    Not sure this is a good idea in the long run.  */
00937 
00938 typedef struct
00939 {
00940   /* Indices into parse/insert/extract/print handler tables.  */
00941   struct cgen_opcode_handler handlers;
00942 #define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
00943 
00944   /* Syntax string.  */
00945   CGEN_SYNTAX syntax;
00946 #define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
00947 
00948   /* Format entry.  */
00949   const CGEN_IFMT *format;
00950 #define CGEN_OPCODE_FORMAT(opc) ((opc)->format)
00951 #define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
00952 #define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
00953 #define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
00954 
00955   /* Instruction opcode value.  */
00956   CGEN_IVALUE value;
00957 #define CGEN_OPCODE_VALUE(opc) (& (opc)->value)
00958 #define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value)
00959 #define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
00960 } CGEN_OPCODE;
00961 
00962 /* Instruction attributes.
00963    This is made a published type as applications can cache a pointer to
00964    the attributes for speed.  */
00965 
00966 #ifndef CGEN_INSN_NBOOL_ATTRS
00967 #define CGEN_INSN_NBOOL_ATTRS 1
00968 #endif
00969 typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
00970 
00971 /* Enum of architecture independent attributes.  */
00972 
00973 #ifndef CGEN_ARCH
00974 /* ??? Numbers here are recorded in two places.  */
00975 typedef enum cgen_insn_attr {
00976   CGEN_INSN_ALIAS = 0
00977 } CGEN_INSN_ATTR;
00978 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
00979 #endif
00980 
00981 /* This struct defines each entry in the instruction table.  */
00982 
00983 typedef struct
00984 {
00985   /* Each real instruction is enumerated.  */
00986   /* ??? This may go away in time.  */
00987   int num;
00988 #define CGEN_INSN_NUM(insn) ((insn)->base->num)
00989 
00990   /* Name of entry (that distinguishes it from all other entries).  */
00991   /* ??? If mnemonics have operands, try to print full mnemonic.  */
00992   const char *name;
00993 #define CGEN_INSN_NAME(insn) ((insn)->base->name)
00994 
00995   /* Mnemonic.  This is used when parsing and printing the insn.
00996      In the case of insns that have operands on the mnemonics, this is
00997      only the constant part.  E.g. for conditional execution of an `add' insn,
00998      where the full mnemonic is addeq, addne, etc., and the condition is
00999      treated as an operand, this is only "add".  */
01000   const char *mnemonic;
01001 #define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic)
01002 
01003   /* Total length of instruction, in bits.  */
01004   int bitsize;
01005 #define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize)
01006 
01007 #if 0 /* ??? Disabled for now as there is a problem with embedded newlines
01008         and the table is already pretty big.  Should perhaps be moved
01009         to a file of its own.  */
01010   /* Semantics, as RTL.  */
01011   /* ??? Plain text or bytecodes?  */
01012   /* ??? Note that the operand instance table could be computed at run-time
01013      if we parse this and cache the results.  Something to eventually do.  */
01014   const char *rtx;
01015 #define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
01016 #endif
01017 
01018   /* Attributes.
01019      This must appear last.  It is a variable sized array in that one
01020      architecture may have 1 nonbool attribute and another may have more.
01021      Having this last means the non-architecture specific code needn't
01022      care.  The goal is to eventually record attributes in their raw form,
01023      evaluate them at run-time, and cache the values, so this worry will go
01024      away anyway.  */
01025   CGEN_INSN_ATTR_TYPE attrs;
01026 #define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs)
01027 /* Return value of attribute ATTR in INSN.  */
01028 #define CGEN_INSN_ATTR_VALUE(insn, attr) \
01029 CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
01030 #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
01031   CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
01032 } CGEN_IBASE;
01033 
01034 /* Return non-zero if INSN is the "invalid" insn marker.  */
01035 
01036 #define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0)
01037 
01038 /* Main struct contain instruction information.
01039    BASE is always present, the rest is present only if asked for.  */
01040 
01041 struct cgen_insn
01042 {
01043   /* ??? May be of use to put a type indicator here.
01044      Then this struct could different info for different classes of insns.  */
01045   /* ??? A speedup can be had by moving `base' into this struct.
01046      Maybe later.  */
01047   const CGEN_IBASE *base;
01048   const CGEN_OPCODE *opcode;
01049   const CGEN_OPINST *opinst;
01050 
01051   /* Regex to disambiguate overloaded opcodes */
01052   void *rx;
01053 #define CGEN_INSN_RX(insn) ((insn)->rx)
01054 #define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
01055 };
01056 
01057 /* Instruction lists.
01058    This is used for adding new entries and for creating the hash lists.  */
01059 
01060 typedef struct cgen_insn_list
01061 {
01062   struct cgen_insn_list *next;
01063   const CGEN_INSN *insn;
01064 } CGEN_INSN_LIST;
01065 
01066 /* Table of instructions.  */
01067 
01068 typedef struct
01069 {
01070   const CGEN_INSN *init_entries;
01071   unsigned int entry_size; /* since the attribute member is variable sized */
01072   unsigned int num_init_entries;
01073   CGEN_INSN_LIST *new_entries;
01074 } CGEN_INSN_TABLE;
01075 
01076 /* Return number of instructions.  This includes any added at run-time.  */
01077 
01078 extern int cgen_insn_count (CGEN_CPU_DESC);
01079 extern int cgen_macro_insn_count (CGEN_CPU_DESC);
01080 
01081 /* Macros to access the other insn elements not recorded in CGEN_IBASE.  */
01082 
01083 /* Fetch INSN's operand instance table.  */
01084 /* ??? Doesn't handle insns added at runtime.  */
01085 #define CGEN_INSN_OPERANDS(insn) ((insn)->opinst)
01086 
01087 /* Return INSN's opcode table entry.  */
01088 #define CGEN_INSN_OPCODE(insn) ((insn)->opcode)
01089 
01090 /* Return INSN's handler data.  */
01091 #define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
01092 
01093 /* Return INSN's syntax.  */
01094 #define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
01095 
01096 /* Return size of base mask in bits.  */
01097 #define CGEN_INSN_MASK_BITSIZE(insn) \
01098   CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
01099 
01100 /* Return mask of base part of INSN.  */
01101 #define CGEN_INSN_BASE_MASK(insn) \
01102   CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
01103 
01104 /* Return value of base part of INSN.  */
01105 #define CGEN_INSN_BASE_VALUE(insn) \
01106   CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
01107 
01108 /* Standard way to test whether INSN is supported by MACH.
01109    MACH is one of enum mach_attr.
01110    The "|1" is because the base mach is always selected.  */
01111 #define CGEN_INSN_MACH_HAS_P(insn, mach) \
01112 ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
01113 
01114 /* Macro instructions.
01115    Macro insns aren't real insns, they map to one or more real insns.
01116    E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or
01117    some such.
01118 
01119    Macro insns can expand to nothing (e.g. a nop that is optimized away).
01120    This is useful in multi-insn macros that build a constant in a register.
01121    Of course this isn't the default behaviour and must be explicitly enabled.
01122 
01123    Assembly of macro-insns is relatively straightforward.  Disassembly isn't.
01124    However, disassembly of at least some kinds of macro insns is important
01125    in order that the disassembled code preserve the readability of the original
01126    insn.  What is attempted here is to disassemble all "simple" macro-insns,
01127    where "simple" is currently defined to mean "expands to one real insn".
01128 
01129    Simple macro-insns are handled specially.  They are emitted as ALIAS's
01130    of real insns.  This simplifies their handling since there's usually more
01131    of them than any other kind of macro-insn, and proper disassembly of them
01132    falls out for free.  */
01133 
01134 /* For each macro-insn there may be multiple expansion possibilities,
01135    depending on the arguments.  This structure is accessed via the `data'
01136    member of CGEN_INSN.  */
01137 
01138 typedef struct cgen_minsn_expansion {
01139   /* Function to do the expansion.
01140      If the expansion fails (e.g. "no match") NULL is returned.
01141      Space for the expansion is obtained with malloc.
01142      It is up to the caller to free it.  */
01143   const char * (* fn)
01144      (const struct cgen_minsn_expansion *,
01145       const char *, const char **, int *,
01146       CGEN_OPERAND **);
01147 #define CGEN_MIEXPN_FN(ex) ((ex)->fn)
01148 
01149   /* Instruction(s) the macro expands to.
01150      The format of STR is defined by FN.
01151      It is typically the assembly code of the real insn, but it could also be
01152      the original Scheme expression or a tokenized form of it (with FN being
01153      an appropriate interpreter).  */
01154   const char * str;
01155 #define CGEN_MIEXPN_STR(ex) ((ex)->str)
01156 } CGEN_MINSN_EXPANSION;
01157 
01158 /* Normal expander.
01159    When supported, this function will convert the input string to another
01160    string and the parser will be invoked recursively.  The output string
01161    may contain further macro invocations.  */
01162 
01163 extern const char * cgen_expand_macro_insn
01164   (CGEN_CPU_DESC, const struct cgen_minsn_expansion *,
01165    const char *, const char **, int *, CGEN_OPERAND **);
01166 
01167 /* The assembler insn table is hashed based on some function of the mnemonic
01168    (the actually hashing done is up to the target, but we provide a few
01169    examples like the first letter or a function of the entire mnemonic).  */
01170 
01171 extern CGEN_INSN_LIST * cgen_asm_lookup_insn
01172   (CGEN_CPU_DESC, const char *);
01173 #define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string))
01174 #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
01175 
01176 /* The disassembler insn table is hashed based on some function of machine
01177    instruction (the actually hashing done is up to the target).  */
01178 
01179 extern CGEN_INSN_LIST * cgen_dis_lookup_insn
01180   (CGEN_CPU_DESC, const char *, CGEN_INSN_INT);
01181 /* FIXME: delete these two */
01182 #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value))
01183 #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
01184 
01185 /* The CPU description.
01186    A copy of this is created when the cpu table is "opened".
01187    All global state information is recorded here.
01188    Access macros are provided for "public" members.  */
01189 
01190 typedef struct cgen_cpu_desc
01191 {
01192   /* Bitmap of selected machine(s) (a la BFD machine number).  */
01193   int machs;
01194 
01195   /* Bitmap of selected isa(s).  */
01196   CGEN_BITSET *isas;
01197 #define CGEN_CPU_ISAS(cd) ((cd)->isas)
01198 
01199   /* Current endian.  */
01200   enum cgen_endian endian;
01201 #define CGEN_CPU_ENDIAN(cd) ((cd)->endian)
01202 
01203   /* Current insn endian.  */
01204   enum cgen_endian insn_endian;
01205 #define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian)
01206 
01207   /* Word size (in bits).  */
01208   /* ??? Or maybe maximum word size - might we ever need to allow a cpu table
01209      to be opened for both sparc32/sparc64?
01210      ??? Another alternative is to create a table of selected machs and
01211      lazily fetch the data from there.  */
01212   unsigned int word_bitsize;
01213 
01214   /* Instruction chunk size (in bits), for purposes of endianness
01215      conversion.  */
01216   unsigned int insn_chunk_bitsize;
01217 
01218   /* Indicator if sizes are unknown.
01219      This is used by default_insn_bitsize,base_insn_bitsize if there is a
01220      difference between the selected isa's.  */
01221 #define CGEN_SIZE_UNKNOWN 65535
01222 
01223   /* Default instruction size (in bits).
01224      This is used by the assembler when it encounters an unknown insn.  */
01225   unsigned int default_insn_bitsize;
01226 
01227   /* Base instruction size (in bits).
01228      For non-LIW cpus this is generally the length of the smallest insn.
01229      For LIW cpus its wip (work-in-progress).  For the m32r its 32.  */
01230   unsigned int base_insn_bitsize;
01231 
01232   /* Minimum/maximum instruction size (in bits).  */
01233   unsigned int min_insn_bitsize;
01234   unsigned int max_insn_bitsize;
01235 
01236   /* Instruction set variants.  */
01237   const CGEN_ISA *isa_table;
01238 
01239   /* Machine variants.  */
01240   const CGEN_MACH *mach_table;
01241 
01242   /* Hardware elements.  */
01243   CGEN_HW_TABLE hw_table;
01244 
01245   /* Instruction fields.  */
01246   const CGEN_IFLD *ifld_table;
01247 
01248   /* Operands.  */
01249   CGEN_OPERAND_TABLE operand_table;
01250 
01251   /* Main instruction table.  */
01252   CGEN_INSN_TABLE insn_table;
01253 #define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table)
01254 
01255   /* Macro instructions are defined separately and are combined with real
01256      insns during hash table computation.  */
01257   CGEN_INSN_TABLE macro_insn_table;
01258 
01259   /* Copy of CGEN_INT_INSN_P.  */
01260   int int_insn_p;
01261 
01262   /* Called to rebuild the tables after something has changed.  */
01263   void (*rebuild_tables) (CGEN_CPU_DESC);
01264 
01265   /* Operand parser callback.  */
01266   cgen_parse_operand_fn * parse_operand_fn;
01267 
01268   /* Parse/insert/extract/print cover fns for operands.  */
01269   const char * (*parse_operand)
01270     (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_);
01271 #ifdef __BFD_H_SEEN__
01272   const char * (*insert_operand)
01273     (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_,
01274      CGEN_INSN_BYTES_PTR, bfd_vma pc_);
01275   int (*extract_operand)
01276     (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
01277      CGEN_FIELDS *fields_, bfd_vma pc_);
01278   void (*print_operand)
01279     (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_,
01280      void const *attrs_, bfd_vma pc_, int length_);
01281 #else
01282   const char * (*insert_operand) ();
01283   int (*extract_operand) ();
01284   void (*print_operand) ();
01285 #endif
01286 #define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand)
01287 #define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand)
01288 #define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand)
01289 #define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand)
01290 
01291   /* Size of CGEN_FIELDS struct.  */
01292   unsigned int sizeof_fields;
01293 #define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields)
01294 
01295   /* Set the bitsize field.  */
01296   void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_);
01297 #define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize)
01298 
01299   /* CGEN_FIELDS accessors.  */
01300   int (*get_int_operand)
01301     (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
01302   void (*set_int_operand)
01303     (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_);
01304 #ifdef __BFD_H_SEEN__
01305   bfd_vma (*get_vma_operand)
01306     (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
01307   void (*set_vma_operand)
01308     (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_);
01309 #else
01310   long (*get_vma_operand) ();
01311   void (*set_vma_operand) ();
01312 #endif
01313 #define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand)
01314 #define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand)
01315 #define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand)
01316 #define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand)
01317 
01318   /* Instruction parse/insert/extract/print handlers.  */
01319   /* FIXME: make these types uppercase.  */
01320   cgen_parse_fn * const *parse_handlers;
01321   cgen_insert_fn * const *insert_handlers;
01322   cgen_extract_fn * const *extract_handlers;
01323   cgen_print_fn * const *print_handlers;
01324 #define CGEN_PARSE_FN(cd, insn)   (cd->parse_handlers[(insn)->opcode->handlers.parse])
01325 #define CGEN_INSERT_FN(cd, insn)  (cd->insert_handlers[(insn)->opcode->handlers.insert])
01326 #define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract])
01327 #define CGEN_PRINT_FN(cd, insn)   (cd->print_handlers[(insn)->opcode->handlers.print])
01328 
01329   /* Return non-zero if insn should be added to hash table.  */
01330   int (* asm_hash_p) (const CGEN_INSN *);
01331 
01332   /* Assembler hash function.  */
01333   unsigned int (* asm_hash) (const char *);
01334 
01335   /* Number of entries in assembler hash table.  */
01336   unsigned int asm_hash_size;
01337 
01338   /* Return non-zero if insn should be added to hash table.  */
01339   int (* dis_hash_p) (const CGEN_INSN *);
01340 
01341   /* Disassembler hash function.  */
01342   unsigned int (* dis_hash) (const char *, CGEN_INSN_INT);
01343 
01344   /* Number of entries in disassembler hash table.  */
01345   unsigned int dis_hash_size;
01346 
01347   /* Assembler instruction hash table.  */
01348   CGEN_INSN_LIST **asm_hash_table;
01349   CGEN_INSN_LIST *asm_hash_table_entries;
01350 
01351   /* Disassembler instruction hash table.  */
01352   CGEN_INSN_LIST **dis_hash_table;
01353   CGEN_INSN_LIST *dis_hash_table_entries;
01354 
01355   /* This field could be turned into a bitfield if room for other flags is needed.  */
01356   unsigned int signed_overflow_ok_p;
01357        
01358 } CGEN_CPU_TABLE;
01359 
01360 /* wip */
01361 #ifndef CGEN_WORD_ENDIAN
01362 #define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd)
01363 #endif
01364 #ifndef CGEN_INSN_WORD_ENDIAN
01365 #define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd)
01366 #endif
01367 
01368 /* Prototypes of major functions.  */
01369 /* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC.
01370    Not the init fns though, as that would drag in things that mightn't be
01371    used and might not even exist.  */
01372 
01373 /* Argument types to cpu_open.  */
01374 
01375 enum cgen_cpu_open_arg {
01376   CGEN_CPU_OPEN_END,
01377   /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified".  */
01378   CGEN_CPU_OPEN_ISAS,
01379   /* Select machine(s), arg is bitmap or 0 meaning "unspecified".  */
01380   CGEN_CPU_OPEN_MACHS,
01381   /* Select machine, arg is mach's bfd name.
01382      Multiple machines can be specified by repeated use.  */
01383   CGEN_CPU_OPEN_BFDMACH,
01384   /* Select endian, arg is CGEN_ENDIAN_*.  */
01385   CGEN_CPU_OPEN_ENDIAN
01386 };
01387 
01388 /* Open a cpu descriptor table for use.
01389    ??? We only support ISO C stdargs here, not K&R.
01390    Laziness, plus experiment to see if anything requires K&R - eventually
01391    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01392 
01393 extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...);
01394 
01395 /* Cover fn to handle simple case.  */
01396 
01397 extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1)
01398    (const char *mach_name_, enum cgen_endian endian_);
01399 
01400 /* Close it.  */
01401 
01402 extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC);
01403 
01404 /* Initialize the opcode table for use.
01405    Called by init_asm/init_dis.  */
01406 
01407 extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_);
01408 
01409 /* build the insn selection regex.
01410    called by init_opcode_table */
01411 
01412 extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_);
01413 
01414 /* Initialize the ibld table for use.
01415    Called by init_asm/init_dis.  */
01416 
01417 extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_);
01418 
01419 /* Initialize an cpu table for assembler or disassembler use.
01420    These must be called immediately after cpu_open.  */
01421 
01422 extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC);
01423 extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC);
01424 
01425 /* Initialize the operand instance table for use.  */
01426 
01427 extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_);
01428 
01429 /* Assemble an instruction.  */
01430 
01431 extern const CGEN_INSN * CGEN_SYM (assemble_insn)
01432   (CGEN_CPU_DESC, const char *, CGEN_FIELDS *,
01433    CGEN_INSN_BYTES_PTR, char **);
01434 
01435 extern const CGEN_KEYWORD CGEN_SYM (operand_mach);
01436 extern int CGEN_SYM (get_mach) (const char *);
01437 
01438 /* Operand index computation.  */
01439 extern const CGEN_INSN * cgen_lookup_insn
01440   (CGEN_CPU_DESC, const CGEN_INSN * insn_,
01441    CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
01442    int length_, CGEN_FIELDS *fields_, int alias_p_);
01443 extern void cgen_get_insn_operands
01444   (CGEN_CPU_DESC, const CGEN_INSN * insn_,
01445    const CGEN_FIELDS *fields_, int *indices_);
01446 extern const CGEN_INSN * cgen_lookup_get_insn_operands
01447   (CGEN_CPU_DESC, const CGEN_INSN *insn_,
01448    CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
01449    int length_, int *indices_, CGEN_FIELDS *fields_);
01450 
01451 /* Cover fns to bfd_get/set.  */
01452 
01453 extern CGEN_INSN_INT cgen_get_insn_value
01454   (CGEN_CPU_DESC, unsigned char *, int);
01455 extern void cgen_put_insn_value
01456   (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
01457 
01458 /* Read in a cpu description file.
01459    ??? For future concerns, including adding instructions to the assembler/
01460    disassembler at run-time.  */
01461 
01462 extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_);
01463 
01464 /* Allow signed overflow of instruction fields.  */
01465 extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC);
01466 
01467 /* Generate an error message if a signed field in an instruction overflows.  */
01468 extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC);
01469 
01470 /* Will an error message be generated if a signed field in an instruction overflows ? */
01471 extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC);
01472 
01473 #endif /* CGEN_H */