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cell-binutils  2.17cvs20070401
Classes | Defines | Typedefs | Enumerations | Functions
cgen.h File Reference
#include "symcat.h"
#include "cgen-bitset.h"
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Classes

union  CGEN_ATTR_VALUE_TYPE
struct  CGEN_ATTR
struct  CGEN_ATTR_ENTRY
struct  CGEN_ATTR_TABLE
struct  CGEN_ISA
struct  CGEN_MACH
struct  CGEN_EXTRACT_INFO
struct  cgen_opcode_handler
struct  CGEN_HW_ENTRY
struct  CGEN_HW_TABLE
struct  cgen_keyword_entry
struct  cgen_keyword
struct  CGEN_KEYWORD_SEARCH
struct  cgen_maybe_multi_ifield
struct  CGEN_OPERAND
struct  CGEN_OPERAND_TABLE
struct  CGEN_OPINST
struct  CGEN_SYNTAX
struct  cgen_ifld
struct  CGEN_IFMT_IFLD
struct  CGEN_IFMT
struct  CGEN_IVALUE
struct  CGEN_OPCODE
struct  CGEN_IBASE
struct  cgen_insn
struct  cgen_insn_list
struct  CGEN_INSN_TABLE
struct  cgen_minsn_expansion
struct  cgen_cpu_desc
union  cgen_maybe_multi_ifield.val

Defines

#define CGEN_SYM(s)   CONCAT3 (unknown,_cgen_,s)
#define CGEN_INLINE
#define CGEN_ATTR_TYPE(n)
#define CGEN_ATTR_BOOLS(a)   ((a)->bool)
#define CGEN_ATTR_NBOOL_OFFSET   32
#define CGEN_ATTR_MASK(attr)   (1 << (attr))
#define CGEN_BOOL_ATTR(attrs, attr)   ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
#define CGEN_ATTR_VALUE(obj, attr_table, attr)
#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr)   ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
#define CGEN_FIELDS_BITSIZE(fields)   ((fields)->length)
#define CGEN_HW_NBOOL_ATTRS   1
#define CGEN_HW_ATTRS(hw)   (&(hw)->attrs)
#define CGEN_HW_ATTR_VALUE(hw, attr)   CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
#define CGEN_KEYWORD_NBOOL_ATTRS   1
#define CGEN_MODE_VM   CGEN_MODE_VOID
#define CGEN_OPERAND_NIL   CGEN_OPERAND_MAX
#define CGEN_OPERAND_NBOOL_ATTRS   1
#define CGEN_OPERAND_ATTRS(operand)   (&(operand)->attrs)
#define CGEN_OPERAND_ATTR_VALUE(operand, attr)   CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
#define CGEN_OPINST_ATTRS(opinst)   ((opinst)->attrs)
#define CGEN_OPINST_ATTR(opinst, attr)   ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
#define CGEN_OPINST_COND_REF   1
#define CGEN_MAX_SYNTAX_ELEMENTS   48
#define CGEN_SYNTAX_STRING(syn)   (syn->syntax)
#define CGEN_SYNTAX_CHAR_P(c)   ((c) < 128)
#define CGEN_SYNTAX_CHAR(c)   ((unsigned char)c)
#define CGEN_SYNTAX_FIELD(c)   ((c) - 128)
#define CGEN_SYNTAX_MAKE_FIELD(c)   ((c) + 128)
#define CGEN_SYNTAX_MNEMONIC   1
#define CGEN_SYNTAX_MNEMONIC_P(ch)   ((ch) == CGEN_SYNTAX_MNEMONIC)
#define CGEN_IFLD_NUM(f)   ((f)->num)
#define CGEN_IFLD_NAME(f)   ((f)->name)
#define CGEN_IFLD_WORD_OFFSET(f)   ((f)->word_offset)
#define CGEN_IFLD_WORD_SIZE(f)   ((f)->word_size)
#define CGEN_IFLD_START(f)   ((f)->start)
#define CGEN_IFLD_LENGTH(f)   ((f)->length)
#define CGEN_IFLD_NBOOL_ATTRS   1
#define CGEN_IFLD_ATTRS(f)   (&(f)->attrs)
#define CGEN_IFLD_ATTR_VALUE(ifld, attr)   CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
#define CGEN_IFMT_IFLD_IFLD(ii)   ((ii)->ifld)
#define CGEN_MAX_IFMT_OPERANDS   16
#define CGEN_IFMT_MASK_LENGTH(ifmt)   ((ifmt)->mask_length)
#define CGEN_IFMT_LENGTH(ifmt)   ((ifmt)->length)
#define CGEN_IFMT_MASK(ifmt)   ((ifmt)->mask)
#define CGEN_IFMT_IFLDS(ifmt)   ((ifmt)->iflds)
#define CGEN_OPCODE_HANDLERS(opc)   (& (opc)->handlers)
#define CGEN_OPCODE_SYNTAX(opc)   (& (opc)->syntax)
#define CGEN_OPCODE_FORMAT(opc)   ((opc)->format)
#define CGEN_OPCODE_MASK_BITSIZE(opc)   CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
#define CGEN_OPCODE_BITSIZE(opc)   CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
#define CGEN_OPCODE_IFLDS(opc)   CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
#define CGEN_OPCODE_VALUE(opc)   (& (opc)->value)
#define CGEN_OPCODE_BASE_VALUE(opc)   (CGEN_OPCODE_VALUE (opc)->base_value)
#define CGEN_OPCODE_BASE_MASK(opc)   CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
#define CGEN_INSN_NBOOL_ATTRS   1
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs)   ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
#define CGEN_INSN_NUM(insn)   ((insn)->base->num)
#define CGEN_INSN_NAME(insn)   ((insn)->base->name)
#define CGEN_INSN_MNEMONIC(insn)   ((insn)->base->mnemonic)
#define CGEN_INSN_BITSIZE(insn)   ((insn)->base->bitsize)
#define CGEN_INSN_ATTRS(insn)   (&(insn)->base->attrs)
#define CGEN_INSN_ATTR_VALUE(insn, attr)   CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr)   CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
#define CGEN_INSN_INVALID_P(insn)   (CGEN_INSN_MNEMONIC (insn) == 0)
#define CGEN_INSN_RX(insn)   ((insn)->rx)
#define CGEN_MAX_RX_ELEMENTS   (CGEN_MAX_SYNTAX_ELEMENTS * 5)
#define CGEN_INSN_OPERANDS(insn)   ((insn)->opinst)
#define CGEN_INSN_OPCODE(insn)   ((insn)->opcode)
#define CGEN_INSN_HANDLERS(insn)   CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
#define CGEN_INSN_SYNTAX(insn)   CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
#define CGEN_INSN_MASK_BITSIZE(insn)   CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
#define CGEN_INSN_BASE_MASK(insn)   CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
#define CGEN_INSN_BASE_VALUE(insn)   CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
#define CGEN_INSN_MACH_HAS_P(insn, mach)   ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
#define CGEN_MIEXPN_FN(ex)   ((ex)->fn)
#define CGEN_MIEXPN_STR(ex)   ((ex)->str)
#define CGEN_ASM_LOOKUP_INSN(cd, string)   cgen_asm_lookup_insn ((cd), (string))
#define CGEN_ASM_NEXT_INSN(insn)   ((insn)->next)
#define CGEN_DIS_LOOKUP_INSN(cd, buf, value)   cgen_dis_lookup_insn ((cd), (buf), (value))
#define CGEN_DIS_NEXT_INSN(insn)   ((insn)->next)
#define CGEN_CPU_ISAS(cd)   ((cd)->isas)
#define CGEN_CPU_ENDIAN(cd)   ((cd)->endian)
#define CGEN_CPU_INSN_ENDIAN(cd)   ((cd)->insn_endian)
#define CGEN_SIZE_UNKNOWN   65535
#define CGEN_CPU_INSN_TABLE(cd)   (& (cd)->insn_table)
#define CGEN_CPU_PARSE_OPERAND(cd)   ((cd)->parse_operand)
#define CGEN_CPU_INSERT_OPERAND(cd)   ((cd)->insert_operand)
#define CGEN_CPU_EXTRACT_OPERAND(cd)   ((cd)->extract_operand)
#define CGEN_CPU_PRINT_OPERAND(cd)   ((cd)->print_operand)
#define CGEN_CPU_SIZEOF_FIELDS(cd)   ((cd)->sizeof_fields)
#define CGEN_CPU_SET_FIELDS_BITSIZE(cd)   ((cd)->set_fields_bitsize)
#define CGEN_CPU_GET_INT_OPERAND(cd)   ((cd)->get_int_operand)
#define CGEN_CPU_SET_INT_OPERAND(cd)   ((cd)->set_int_operand)
#define CGEN_CPU_GET_VMA_OPERAND(cd)   ((cd)->get_vma_operand)
#define CGEN_CPU_SET_VMA_OPERAND(cd)   ((cd)->set_vma_operand)
#define CGEN_PARSE_FN(cd, insn)   (cd->parse_handlers[(insn)->opcode->handlers.parse])
#define CGEN_INSERT_FN(cd, insn)   (cd->insert_handlers[(insn)->opcode->handlers.insert])
#define CGEN_EXTRACT_FN(cd, insn)   (cd->extract_handlers[(insn)->opcode->handlers.extract])
#define CGEN_PRINT_FN(cd, insn)   (cd->print_handlers[(insn)->opcode->handlers.print])
#define CGEN_WORD_ENDIAN(cd)   CGEN_CPU_ENDIAN (cd)
#define CGEN_INSN_WORD_ENDIAN(cd)   CGEN_CPU_INSN_ENDIAN (cd)

Typedefs

typedef unsigned int CGEN_INSN_INT
typedef unsigned char * CGEN_INSN_BYTES
typedef unsigned char * CGEN_INSN_BYTES_PTR
typedef struct cgen_insn
typedef struct cgen_cpu_descCGEN_CPU_DESC
typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE
typedef int CGEN_ATTR_VALUE_ENUM_TYPE
typedef struct cgen_fields
typedef const char *( cgen_parse_fn )(CGEN_CPU_DESC, const CGEN_INSN *insn_, const char **strp_, CGEN_FIELDS *fields_)
typedef const char *( cgen_insert_fn )()
typedef intcgen_extract_fn )()
typedef void( cgen_print_fn )()
typedef const char *( cgen_parse_operand_fn )()
typedef struct cgen_keyword_entry CGEN_KEYWORD_ENTRY
typedef struct cgen_keyword CGEN_KEYWORD
typedef struct
cgen_maybe_multi_ifield 
CGEN_MAYBE_MULTI_IFLD
typedef unsigned short CGEN_SYNTAX_CHAR_TYPE
typedef struct cgen_ifld CGEN_IFLD
typedef enum cgen_insn_attr CGEN_INSN_ATTR
typedef struct cgen_insn_list CGEN_INSN_LIST
typedef struct cgen_minsn_expansion CGEN_MINSN_EXPANSION
typedef struct cgen_cpu_desc CGEN_CPU_TABLE

Enumerations

enum  cgen_endian { CGEN_ENDIAN_UNKNOWN, CGEN_ENDIAN_LITTLE, CGEN_ENDIAN_BIG }
enum  cgen_parse_operand_type { CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER, CGEN_PARSE_OPERAND_ADDRESS, CGEN_PARSE_OPERAND_SYMBOLIC }
enum  cgen_parse_operand_result { CGEN_PARSE_OPERAND_RESULT_NUMBER, CGEN_PARSE_OPERAND_RESULT_REGISTER, CGEN_PARSE_OPERAND_RESULT_QUEUED, CGEN_PARSE_OPERAND_RESULT_ERROR }
enum  cgen_asm_type { CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX }
enum  cgen_hw_type {
  CGEN_HW_MAX, HW_H_MEMORY, HW_H_SINT, HW_H_UINT,
  HW_H_ADDR, HW_H_IADDR, HW_H_PC, HW_H_GR,
  HW_H_CR, HW_H_DR, HW_H_PS, HW_H_R13,
  HW_H_R14, HW_H_R15, HW_H_NBIT, HW_H_ZBIT,
  HW_H_VBIT, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT,
  HW_H_TBIT, HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR,
  HW_H_SCR, HW_H_ILM, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_RELOC_ANN, HW_H_PC, HW_H_PSR_IMPLE, HW_H_PSR_VER,
  HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM, HW_H_PSR_BE,
  HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM, HW_H_PSR_PIL,
  HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S, HW_H_TBR_TBA,
  HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET, HW_H_GR,
  HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO, HW_H_FR,
  HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO,
  HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3,
  HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG,
  HW_H_ACC40S, HW_H_ACC40U, HW_H_IACC0, HW_H_ICCR,
  HW_H_FCCR, HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN,
  HW_H_HINT_NOT_TAKEN, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_SPR,
  HW_H_REGISTERS, HW_H_STACK, HW_H_PABITS, HW_H_ZBIT,
  HW_H_CBIT, HW_H_DCBIT, HW_H_PC, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI,
  HW_H_GR_HI, HW_H_GR_SI, HW_H_GR_EXT_QI, HW_H_GR_EXT_HI,
  HW_H_R0L, HW_H_R0H, HW_H_R1L, HW_H_R1H,
  HW_H_R0, HW_H_R1, HW_H_R2, HW_H_R3,
  HW_H_R0L_R0H, HW_H_R2R0, HW_H_R3R1, HW_H_R1R2R0,
  HW_H_AR, HW_H_AR_QI, HW_H_AR_HI, HW_H_AR_SI,
  HW_H_A0, HW_H_A1, HW_H_SB, HW_H_FB,
  HW_H_SP, HW_H_SBIT, HW_H_ZBIT, HW_H_OBIT,
  HW_H_CBIT, HW_H_UBIT, HW_H_IBIT, HW_H_BBIT,
  HW_H_DBIT, HW_H_DCT0, HW_H_DCT1, HW_H_SVF,
  HW_H_DRC0, HW_H_DRC1, HW_H_DMD0, HW_H_DMD1,
  HW_H_INTB, HW_H_SVP, HW_H_VCT, HW_H_ISP,
  HW_H_DMA0, HW_H_DMA1, HW_H_DRA0, HW_H_DRA1,
  HW_H_DSA0, HW_H_DSA1, HW_H_COND16, HW_H_COND16C,
  HW_H_COND16J, HW_H_COND16J_5, HW_H_COND32, HW_H_CR1_32,
  HW_H_CR2_32, HW_H_CR3_32, HW_H_CR_16, HW_H_FLAGS,
  HW_H_SHIMM, HW_H_BIT_INDEX, HW_H_SRC_INDEX, HW_H_DST_INDEX,
  HW_H_SRC_INDIRECT, HW_H_DST_INDIRECT, HW_H_NONE, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16,
  HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM,
  HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW,
  HW_H_BBPSW, HW_H_LOCK, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GPR, HW_H_CSR, HW_H_CR64,
  HW_H_CR, HW_H_CCR, HW_H_CR_FMAX, HW_H_CCR_FMAX,
  HW_H_FMAX_COMPARE_I_P, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_SPR,
  HW_H_PC, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_PC,
  HW_H_GR, HW_H_SR, HW_H_HI16, HW_H_LO16,
  HW_H_CBIT, HW_H_DELAY_INSN, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GR, HW_H_EXT, HW_H_PSW,
  HW_H_GRB, HW_H_CC, HW_H_ECC, HW_H_GRB8,
  HW_H_R8, HW_H_REGMEM8, HW_H_REGDIV8, HW_H_R0,
  HW_H_R01, HW_H_REGBMEM8, HW_H_MEMGR8, HW_H_COND,
  HW_H_CBIT, HW_H_SGTDIS, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GR, HW_H_RB, HW_H_RBJ,
  HW_H_RPSW, HW_H_Z8, HW_H_Z16, HW_H_CY,
  HW_H_HC, HW_H_OV, HW_H_PT, HW_H_S,
  HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX
}
enum  cgen_mode {
  CGEN_MODE_VOID, CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI,
  CGEN_MODE_SI, CGEN_MODE_DI, CGEN_MODE_UBI, CGEN_MODE_UQI,
  CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, CGEN_MODE_SF,
  CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, CGEN_MODE_TARGET_MAX,
  CGEN_MODE_INT, CGEN_MODE_UINT, CGEN_MODE_MAX
}
enum  cgen_operand_type {
  CGEN_OPERAND_MAX, FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ,
  FR30_OPERAND_RIC, FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ,
  FR30_OPERAND_RS1, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14,
  FR30_OPERAND_R15, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C,
  FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8,
  FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10,
  FR30_OPERAND_I32, FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8,
  FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12,
  FR30_OPERAND_REGLIST_LOW_LD, FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST,
  FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT,
  FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT,
  FR30_OPERAND_TBIT, FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR,
  FR30_OPERAND_SCR, FR30_OPERAND_ILM, FR30_OPERAND_MAX, FRV_OPERAND_PC,
  FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ, FRV_OPERAND_GRK,
  FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK, FRV_OPERAND_ACC40SI,
  FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK, FRV_OPERAND_ACCGI,
  FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ, FRV_OPERAND_CPRK,
  FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ, FRV_OPERAND_FRINTK,
  FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK, FRV_OPERAND_FRKHI,
  FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ, FRV_OPERAND_FRDOUBLEK,
  FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT, FRV_OPERAND_CRJ_FLOAT,
  FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1, FRV_OPERAND_ICCI_2,
  FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2, FRV_OPERAND_FCCI_3,
  FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10, FRV_OPERAND_U16,
  FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1, FRV_OPERAND_U6,
  FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND, FRV_OPERAND_HINT,
  FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI, FRV_OPERAND_LOCK,
  FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16, FRV_OPERAND_LRAE,
  FRV_OPERAND_LRAD, FRV_OPERAND_LRAS, FRV_OPERAND_TLBPROPX, FRV_OPERAND_TLBPRL,
  FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN,
  FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12,
  FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16,
  FRV_OPERAND_LABEL24, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS,
  FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA,
  FRV_OPERAND_TBR_TT, FRV_OPERAND_LDANN, FRV_OPERAND_LDDANN, FRV_OPERAND_CALLANN,
  FRV_OPERAND_MAX, IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR,
  IP2K_OPERAND_LIT8, IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H,
  IP2K_OPERAND_ADDR16L, IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT,
  IP2K_OPERAND_CBIT, IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX, IQ2000_OPERAND_PC,
  IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD, IQ2000_OPERAND_RD_RS,
  IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT, IQ2000_OPERAND_IMM,
  IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG, IQ2000_OPERAND_MASK,
  IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT, IQ2000_OPERAND__INDEX,
  IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y, IQ2000_OPERAND_CAM_Z,
  IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z, IQ2000_OPERAND_CM_4Z,
  IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM, IQ2000_OPERAND_HI16,
  IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10, IQ2000_OPERAND_MAX,
  M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI,
  M32C_OPERAND_SRC32RNUNPREFIXEDHI, M32C_OPERAND_SRC32RNUNPREFIXEDSI, M32C_OPERAND_SRC32RNPREFIXEDQI, M32C_OPERAND_SRC32RNPREFIXEDHI,
  M32C_OPERAND_SRC32RNPREFIXEDSI, M32C_OPERAND_SRC16AN, M32C_OPERAND_SRC16ANQI, M32C_OPERAND_SRC16ANHI,
  M32C_OPERAND_SRC32ANUNPREFIXED, M32C_OPERAND_SRC32ANUNPREFIXEDQI, M32C_OPERAND_SRC32ANUNPREFIXEDHI, M32C_OPERAND_SRC32ANUNPREFIXEDSI,
  M32C_OPERAND_SRC32ANPREFIXED, M32C_OPERAND_SRC32ANPREFIXEDQI, M32C_OPERAND_SRC32ANPREFIXEDHI, M32C_OPERAND_SRC32ANPREFIXEDSI,
  M32C_OPERAND_DST16RNQI, M32C_OPERAND_DST16RNHI, M32C_OPERAND_DST16RNSI, M32C_OPERAND_DST16RNEXTQI,
  M32C_OPERAND_DST32R0QI_S, M32C_OPERAND_DST32R0HI_S, M32C_OPERAND_DST32RNUNPREFIXEDQI, M32C_OPERAND_DST32RNUNPREFIXEDHI,
  M32C_OPERAND_DST32RNUNPREFIXEDSI, M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDQI,
  M32C_OPERAND_DST32RNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDSI, M32C_OPERAND_DST16RNQI_S, M32C_OPERAND_DST16ANQI_S,
  M32C_OPERAND_BIT16RN, M32C_OPERAND_BIT32RNPREFIXED, M32C_OPERAND_BIT32RNUNPREFIXED, M32C_OPERAND_R0,
  M32C_OPERAND_R1, M32C_OPERAND_R2, M32C_OPERAND_R3, M32C_OPERAND_R0L,
  M32C_OPERAND_R0H, M32C_OPERAND_R2R0, M32C_OPERAND_R3R1, M32C_OPERAND_R1R2R0,
  M32C_OPERAND_DST16AN, M32C_OPERAND_DST16ANQI, M32C_OPERAND_DST16ANHI, M32C_OPERAND_DST16ANSI,
  M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI,
  M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI,
  M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED,
  M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB,
  M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP,
  M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6,
  M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_S24,
  M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16,
  M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16,
  M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24,
  M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16,
  M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16,
  M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16,
  M32C_OPERAND_DSP_40_U20, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8,
  M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U20, M32C_OPERAND_DSP_48_U24,
  M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI,
  M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4,
  M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI,
  M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI,
  M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI,
  M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI,
  M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI,
  M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BIT3_S,
  M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8,
  M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED,
  M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED,
  M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED,
  M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8,
  M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8,
  M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT,
  M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT,
  M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24,
  M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32,
  M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5,
  M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16,
  M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32,
  M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z,
  M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G, M32C_OPERAND_X,
  M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX,
  M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI,
  M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI,
  M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI,
  M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_20_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI,
  M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI,
  M32C_OPERAND_SRC16_16_20_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI,
  M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI,
  M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI,
  M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI,
  M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI,
  M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI,
  M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI,
  M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI,
  M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI,
  M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI,
  M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI,
  M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI,
  M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI,
  M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI,
  M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI,
  M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI,
  M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI,
  M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED,
  M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT,
  M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE,
  M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED,
  M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED,
  M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED,
  M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED,
  M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED,
  M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED,
  M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI,
  M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI,
  M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI,
  M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI,
  M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI,
  M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI,
  M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI,
  M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI,
  M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI,
  M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI,
  M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_16SA_QI, M32C_OPERAND_DST16_16_20AR_QI,
  M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_16SA_HI,
  M32C_OPERAND_DST16_16_20AR_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI,
  M32C_OPERAND_DST16_16_16SA_SI, M32C_OPERAND_DST16_16_20AR_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI,
  M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI,
  M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI,
  M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI,
  M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI,
  M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI,
  M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI,
  M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI,
  M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC,
  M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED,
  M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED,
  M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8,
  M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI,
  M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI,
  M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S,
  M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX, M32R_OPERAND_PC,
  M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1, M32R_OPERAND_SRC2,
  M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8, M32R_OPERAND_SIMM16,
  M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM8,
  M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS,
  M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16,
  M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16,
  M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX,
  MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM,
  MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC,
  MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL,
  MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S,
  MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP,
  MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0,
  MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW,
  MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG,
  MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP,
  MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN,
  MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64,
  MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2,
  MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2,
  MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16,
  MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8,
  MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3,
  MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2,
  MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4,
  MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4,
  MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD,
  MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT,
  MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR,
  MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX, MT_OPERAND_PC,
  MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR, MT_OPERAND_FRDRRR,
  MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O, MT_OPERAND_RC,
  MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC, MT_OPERAND_COLNUM,
  MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2, MT_OPERAND_RC1,
  MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL, MT_OPERAND_DUP,
  MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE, MT_OPERAND_MASK,
  MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE, MT_OPERAND_MASK1,
  MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA, MT_OPERAND_WR,
  MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM, MT_OPERAND_A23,
  MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR, MT_OPERAND_LENGTH,
  MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB, MT_OPERAND_MODE,
  MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR, MT_OPERAND_LOOPSIZE,
  MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL, MT_OPERAND_CB2SEL,
  MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX, OPENRISC_OPERAND_PC,
  OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16, OPENRISC_OPERAND_UIMM_16,
  OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5, OPENRISC_OPERAND_RD,
  OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23, OPENRISC_OPERAND_OP_F_3,
  OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC, OPENRISC_OPERAND_MAX,
  XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI,
  XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1,
  XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2,
  XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8,
  XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8,
  XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8,
  XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR,
  XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1,
  XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2,
  XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01,
  XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY,
  XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT,
  XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM,
  XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16,
  XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH,
  XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF,
  XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX, XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8,
  XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY, XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV,
  XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S, XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM,
  XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS, XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ,
  XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2, XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2,
  XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B, XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8,
  XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12, XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8,
  XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2, XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12,
  XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24, XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW,
  XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0, XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2,
  XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX
}
enum  cgen_opinst_type { CGEN_OPINST_END = 0, CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT }
enum  cgen_insn_attr {
  CGEN_INSN_ALIAS = 0, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT,
  CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS,
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI,
  CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED,
  CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING,
  CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO,
  CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT,
  CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN,
  CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN,
  CGEN_INSN_LOAD_DELAY, CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD,
  CGEN_INSN_USES_RS, CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS,
  CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS,
  CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI,
  CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS,
  CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_ISA, CGEN_INSN_RL_TYPE, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS,
  CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI,
  CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS,
  CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL, CGEN_INSN_SPECIAL_M32R,
  CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL,
  CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT,
  CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB,
  CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN, CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN,
  CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN,
  CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN,
  CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP,
  CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP,
  CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY,
  CGEN_INSN_MEMORY_ACCESS, CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN,
  CGEN_INSN_JAL_HAZARD, CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1,
  CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL,
  CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT,
  CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB,
  CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS,
  CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS,
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI,
  CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED,
  CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
}
enum  cgen_cpu_open_arg {
  CGEN_CPU_OPEN_END, CGEN_CPU_OPEN_ISAS, CGEN_CPU_OPEN_MACHS, CGEN_CPU_OPEN_BFDMACH,
  CGEN_CPU_OPEN_ENDIAN
}

Functions

void cgen_set_parse_operand_fn (CGEN_CPU_DESC, cgen_parse_operand_fn)
void cgen_init_parse_operand (CGEN_CPU_DESC)
const CGEN_HW_ENTRYcgen_hw_lookup_by_name (CGEN_CPU_DESC, const char *)
const CGEN_HW_ENTRYcgen_hw_lookup_by_num (CGEN_CPU_DESC, unsigned int)
const CGEN_KEYWORD_ENTRYcgen_keyword_lookup_name (CGEN_KEYWORD *, const char *)
const CGEN_KEYWORD_ENTRYcgen_keyword_lookup_value (CGEN_KEYWORD *, int)
void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *)
CGEN_KEYWORD_SEARCH cgen_keyword_search_init (CGEN_KEYWORD *, const char *)
const CGEN_KEYWORD_ENTRYcgen_keyword_search_next (CGEN_KEYWORD_SEARCH *)
const char * cgen_parse_keyword (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)
const CGEN_OPERANDcgen_operand_lookup_by_name (CGEN_CPU_DESC, const char *)
const CGEN_OPERANDcgen_operand_lookup_by_num (CGEN_CPU_DESC, int)
typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE
int cgen_insn_count (CGEN_CPU_DESC)
int cgen_macro_insn_count (CGEN_CPU_DESC)
const char * cgen_expand_macro_insn (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, const char *, const char **, int *, CGEN_OPERAND **)
CGEN_INSN_LISTcgen_asm_lookup_insn (CGEN_CPU_DESC, const char *)
CGEN_INSN_LISTcgen_dis_lookup_insn (CGEN_CPU_DESC, const char *, CGEN_INSN_INT)
CGEN_CPU_DESC CGEN_SYM() cpu_open (enum cgen_cpu_open_arg,...)
CGEN_CPU_DESC CGEN_SYM() cpu_open_1 (const char *mach_name_, enum cgen_endian endian_)
void CGEN_SYM() cpu_close (CGEN_CPU_DESC)
void CGEN_SYM() init_opcode_table (CGEN_CPU_DESC cd_)
char *CGEN_SYM() build_insn_regex (CGEN_INSN *insn_)
void CGEN_SYM() init_ibld_table (CGEN_CPU_DESC cd_)
void CGEN_SYM() init_asm (CGEN_CPU_DESC)
void CGEN_SYM() init_dis (CGEN_CPU_DESC)
void CGEN_SYM() init_opinst_table (CGEN_CPU_DESC cd_)
const CGEN_INSN *CGEN_SYM() assemble_insn (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, char **)
const CGEN_KEYWORD CGEN_SYM (operand_mach)
int CGEN_SYM() get_mach (const char *)
const CGEN_INSN * cgen_lookup_insn (CGEN_CPU_DESC, const CGEN_INSN *insn_, CGEN_INSN_INT int_value_, unsigned char *bytes_value_, int length_, CGEN_FIELDS *fields_, int alias_p_)
void cgen_get_insn_operands (CGEN_CPU_DESC, const CGEN_INSN *insn_, const CGEN_FIELDS *fields_, int *indices_)
const CGEN_INSN * cgen_lookup_get_insn_operands (CGEN_CPU_DESC, const CGEN_INSN *insn_, CGEN_INSN_INT int_value_, unsigned char *bytes_value_, int length_, int *indices_, CGEN_FIELDS *fields_)
CGEN_INSN_INT cgen_get_insn_value (CGEN_CPU_DESC, unsigned char *, int)
void cgen_put_insn_value (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT)
const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char *filename_)
void cgen_set_signed_overflow_ok (CGEN_CPU_DESC)
void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC)
unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC)

Class Documentation

union CGEN_ATTR_VALUE_TYPE

Definition at line 114 of file cgen.h.

Collaboration diagram for CGEN_ATTR_VALUE_TYPE:
Class Members
CGEN_ATTR_VALUE_BITSET_TYPE bitset
CGEN_ATTR_VALUE_ENUM_TYPE nonbitset
struct CGEN_ATTR

Definition at line 122 of file cgen.h.

Collaboration diagram for CGEN_ATTR:
Class Members
unsigned int bool
CGEN_ATTR_VALUE_TYPE nonbool
struct CGEN_ATTR_ENTRY

Definition at line 171 of file cgen.h.

Class Members
const char * name
unsigned value
struct CGEN_ATTR_TABLE

Definition at line 179 of file cgen.h.

Collaboration diagram for CGEN_ATTR_TABLE:
Class Members
const CGEN_ATTR_ENTRY * dfault
const char * name
const CGEN_ATTR_ENTRY * vals
struct CGEN_ISA

Definition at line 188 of file cgen.h.

Class Members
unsigned int base_insn_bitsize
unsigned int default_insn_bitsize
unsigned int max_insn_bitsize
unsigned int min_insn_bitsize
const char * name
struct CGEN_MACH

Definition at line 207 of file cgen.h.

Class Members
const char * bfd_name
unsigned int insn_chunk_bitsize
const char * name
int num
struct CGEN_EXTRACT_INFO

Definition at line 253 of file cgen.h.

Class Members
void * dis_info
unsigned char * insn_bytes
unsigned int valid
struct cgen_opcode_handler

Definition at line 347 of file cgen.h.

Class Members
unsigned char extract
unsigned char insert
unsigned char parse
unsigned char print
struct CGEN_HW_ENTRY

Definition at line 429 of file cgen.h.

Class Members
char * name
struct CGEN_HW_TABLE

Definition at line 452 of file cgen.h.

Collaboration diagram for CGEN_HW_TABLE:
Class Members
const CGEN_HW_ENTRY ** entries
unsigned int entry_size
const CGEN_HW_ENTRY * init_entries
unsigned int num_entries
struct cgen_keyword

Definition at line 511 of file cgen.h.

Collaboration diagram for cgen_keyword:
Class Members
unsigned int hash_table_size
CGEN_KEYWORD_ENTRY * init_entries
CGEN_KEYWORD_ENTRY ** name_hash_table
char nonalpha_chars
const CGEN_KEYWORD_ENTRY * null_entry
unsigned int num_init_entries
CGEN_KEYWORD_ENTRY ** value_hash_table
struct CGEN_KEYWORD_SEARCH

Definition at line 539 of file cgen.h.

Collaboration diagram for CGEN_KEYWORD_SEARCH:
Class Members
CGEN_KEYWORD_ENTRY * current_entry
unsigned int current_hash
const char * spec
const CGEN_KEYWORD * table
struct cgen_maybe_multi_ifield

Definition at line 629 of file cgen.h.

Class Members
int count
union cgen_maybe_multi_ifield val
struct CGEN_OPERAND

Definition at line 644 of file cgen.h.

Class Members
char * name
struct CGEN_OPERAND_TABLE

Definition at line 704 of file cgen.h.

Collaboration diagram for CGEN_OPERAND_TABLE:
Class Members
const CGEN_OPERAND ** entries
unsigned int entry_size
const CGEN_OPERAND * init_entries
unsigned int num_entries
struct CGEN_OPINST

Definition at line 736 of file cgen.h.

struct CGEN_SYNTAX

Definition at line 793 of file cgen.h.

Class Members
CGEN_SYNTAX_CHAR_TYPE syntax
struct CGEN_IFMT_IFLD

Definition at line 873 of file cgen.h.

Collaboration diagram for CGEN_IFMT_IFLD:
Class Members
const CGEN_IFLD * ifld
struct CGEN_IFMT

Definition at line 890 of file cgen.h.

Collaboration diagram for CGEN_IFMT:
Class Members
CGEN_IFMT_IFLD iflds
unsigned char length
CGEN_INSN_INT mask
unsigned char mask_length
struct CGEN_IVALUE

Definition at line 919 of file cgen.h.

Class Members
CGEN_INSN_INT base_value
struct CGEN_OPCODE

Definition at line 938 of file cgen.h.

Collaboration diagram for CGEN_OPCODE:
Class Members
const CGEN_IFMT * format
CGEN_SYNTAX syntax
CGEN_IVALUE value
struct CGEN_IBASE

Definition at line 983 of file cgen.h.

Class Members
CGEN_INSN_ATTR_TYPE attrs
int bitsize
const char * mnemonic
const char * name
int num
struct cgen_insn

Definition at line 1041 of file cgen.h.

Collaboration diagram for cgen_insn:
Class Members
const CGEN_IBASE * base
const CGEN_OPCODE * opcode
const CGEN_OPINST * opinst
void * rx
struct cgen_insn_list

Definition at line 1060 of file cgen.h.

Collaboration diagram for cgen_insn_list:
Class Members
const CGEN_INSN * insn
struct cgen_insn_list * next
struct CGEN_INSN_TABLE

Definition at line 1068 of file cgen.h.

Collaboration diagram for CGEN_INSN_TABLE:
Class Members
unsigned int entry_size
const CGEN_INSN * init_entries
CGEN_INSN_LIST * new_entries
unsigned int num_init_entries
union cgen_maybe_multi_ifield.val

Definition at line 633 of file cgen.h.

Class Members
struct cgen_ifld * leaf
struct cgen_maybe_multi_ifield * multi
const void * p

Define Documentation

#define CGEN_ASM_LOOKUP_INSN (   cd,
  string 
)    cgen_asm_lookup_insn ((cd), (string))

Definition at line 1173 of file cgen.h.

#define CGEN_ASM_NEXT_INSN (   insn)    ((insn)->next)

Definition at line 1174 of file cgen.h.

#define CGEN_ATTR_BOOLS (   a)    ((a)->bool)

Definition at line 141 of file cgen.h.

#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE (   attrs)    ((attrs)->bool & (1 << CGEN_INSN_ALIAS))

Definition at line 978 of file cgen.h.

#define CGEN_ATTR_MASK (   attr)    (1 << (attr))

Definition at line 149 of file cgen.h.

#define CGEN_ATTR_NBOOL_OFFSET   32

Definition at line 145 of file cgen.h.

#define CGEN_ATTR_TYPE (   n)
Value:
struct { unsigned int bool; \
	 CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }

Definition at line 135 of file cgen.h.

#define CGEN_ATTR_VALUE (   obj,
  attr_table,
  attr 
)
Value:
((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
 ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
 : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))

Definition at line 161 of file cgen.h.

#define CGEN_BITSET_ATTR_VALUE (   obj,
  attr_table,
  attr 
)    ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)

Definition at line 165 of file cgen.h.

#define CGEN_BOOL_ATTR (   attrs,
  attr 
)    ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)

Definition at line 153 of file cgen.h.

#define CGEN_CPU_ENDIAN (   cd)    ((cd)->endian)

Definition at line 1201 of file cgen.h.

#define CGEN_CPU_EXTRACT_OPERAND (   cd)    ((cd)->extract_operand)

Definition at line 1288 of file cgen.h.

#define CGEN_CPU_GET_INT_OPERAND (   cd)    ((cd)->get_int_operand)

Definition at line 1313 of file cgen.h.

#define CGEN_CPU_GET_VMA_OPERAND (   cd)    ((cd)->get_vma_operand)

Definition at line 1315 of file cgen.h.

#define CGEN_CPU_INSERT_OPERAND (   cd)    ((cd)->insert_operand)

Definition at line 1287 of file cgen.h.

#define CGEN_CPU_INSN_ENDIAN (   cd)    ((cd)->insn_endian)

Definition at line 1205 of file cgen.h.

#define CGEN_CPU_INSN_TABLE (   cd)    (& (cd)->insn_table)

Definition at line 1253 of file cgen.h.

#define CGEN_CPU_ISAS (   cd)    ((cd)->isas)

Definition at line 1197 of file cgen.h.

#define CGEN_CPU_PARSE_OPERAND (   cd)    ((cd)->parse_operand)

Definition at line 1286 of file cgen.h.

#define CGEN_CPU_PRINT_OPERAND (   cd)    ((cd)->print_operand)

Definition at line 1289 of file cgen.h.

#define CGEN_CPU_SET_FIELDS_BITSIZE (   cd)    ((cd)->set_fields_bitsize)

Definition at line 1297 of file cgen.h.

#define CGEN_CPU_SET_INT_OPERAND (   cd)    ((cd)->set_int_operand)

Definition at line 1314 of file cgen.h.

#define CGEN_CPU_SET_VMA_OPERAND (   cd)    ((cd)->set_vma_operand)

Definition at line 1316 of file cgen.h.

#define CGEN_CPU_SIZEOF_FIELDS (   cd)    ((cd)->sizeof_fields)

Definition at line 1293 of file cgen.h.

#define CGEN_DIS_LOOKUP_INSN (   cd,
  buf,
  value 
)    cgen_dis_lookup_insn ((cd), (buf), (value))

Definition at line 1182 of file cgen.h.

#define CGEN_DIS_NEXT_INSN (   insn)    ((insn)->next)

Definition at line 1183 of file cgen.h.

#define CGEN_EXTRACT_FN (   cd,
  insn 
)    (cd->extract_handlers[(insn)->opcode->handlers.extract])

Definition at line 1326 of file cgen.h.

#define CGEN_FIELDS_BITSIZE (   fields)    ((fields)->length)

Definition at line 241 of file cgen.h.

#define CGEN_HW_ATTR_VALUE (   hw,
  attr 
)    CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))

Definition at line 446 of file cgen.h.

#define CGEN_HW_ATTRS (   hw)    (&(hw)->attrs)
#define CGEN_HW_NBOOL_ATTRS   1
#define CGEN_IFLD_ATTR_VALUE (   ifld,
  attr 
)    CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))

Definition at line 853 of file cgen.h.

#define CGEN_IFLD_ATTRS (   f)    (&(f)->attrs)

Definition at line 849 of file cgen.h.

#define CGEN_IFLD_LENGTH (   f)    ((f)->length)

Definition at line 843 of file cgen.h.

#define CGEN_IFLD_NAME (   f)    ((f)->name)

Definition at line 825 of file cgen.h.

#define CGEN_IFLD_NBOOL_ATTRS   1

Definition at line 846 of file cgen.h.

#define CGEN_IFLD_NUM (   f)    ((f)->num)

Definition at line 821 of file cgen.h.

#define CGEN_IFLD_START (   f)    ((f)->start)

Definition at line 839 of file cgen.h.

#define CGEN_IFLD_WORD_OFFSET (   f)    ((f)->word_offset)

Definition at line 830 of file cgen.h.

#define CGEN_IFLD_WORD_SIZE (   f)    ((f)->word_size)

Definition at line 834 of file cgen.h.

#define CGEN_IFMT_IFLD_IFLD (   ii)    ((ii)->ifld)

Definition at line 875 of file cgen.h.

#define CGEN_IFMT_IFLDS (   ifmt)    ((ifmt)->iflds)

Definition at line 914 of file cgen.h.

#define CGEN_IFMT_LENGTH (   ifmt)    ((ifmt)->length)

Definition at line 902 of file cgen.h.

#define CGEN_IFMT_MASK (   ifmt)    ((ifmt)->mask)

Definition at line 909 of file cgen.h.

#define CGEN_IFMT_MASK_LENGTH (   ifmt)    ((ifmt)->mask_length)

Definition at line 898 of file cgen.h.

#define CGEN_INLINE

Definition at line 79 of file cgen.h.

#define CGEN_INSERT_FN (   cd,
  insn 
)    (cd->insert_handlers[(insn)->opcode->handlers.insert])

Definition at line 1325 of file cgen.h.

#define CGEN_INSN_ATTR_VALUE (   insn,
  attr 
)    CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))

Definition at line 1028 of file cgen.h.

#define CGEN_INSN_ATTRS (   insn)    (&(insn)->base->attrs)

Definition at line 1026 of file cgen.h.

Definition at line 1101 of file cgen.h.

Definition at line 1105 of file cgen.h.

#define CGEN_INSN_BITSET_ATTR_VALUE (   insn,
  attr 
)    CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))

Definition at line 1030 of file cgen.h.

#define CGEN_INSN_BITSIZE (   insn)    ((insn)->base->bitsize)

Definition at line 1005 of file cgen.h.

Definition at line 1091 of file cgen.h.

#define CGEN_INSN_INVALID_P (   insn)    (CGEN_INSN_MNEMONIC (insn) == 0)

Definition at line 1036 of file cgen.h.

#define CGEN_INSN_MACH_HAS_P (   insn,
  mach 
)    ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)

Definition at line 1111 of file cgen.h.

Definition at line 1097 of file cgen.h.

#define CGEN_INSN_MNEMONIC (   insn)    ((insn)->base->mnemonic)

Definition at line 1001 of file cgen.h.

#define CGEN_INSN_NAME (   insn)    ((insn)->base->name)

Definition at line 993 of file cgen.h.

#define CGEN_INSN_NBOOL_ATTRS   1

Definition at line 967 of file cgen.h.

#define CGEN_INSN_NUM (   insn)    ((insn)->base->num)

Definition at line 988 of file cgen.h.

#define CGEN_INSN_OPCODE (   insn)    ((insn)->opcode)

Definition at line 1088 of file cgen.h.

#define CGEN_INSN_OPERANDS (   insn)    ((insn)->opinst)

Definition at line 1085 of file cgen.h.

#define CGEN_INSN_RX (   insn)    ((insn)->rx)

Definition at line 1053 of file cgen.h.

Definition at line 1094 of file cgen.h.

#define CGEN_INSN_WORD_ENDIAN (   cd)    CGEN_CPU_INSN_ENDIAN (cd)

Definition at line 1365 of file cgen.h.

#define CGEN_KEYWORD_NBOOL_ATTRS   1

Definition at line 494 of file cgen.h.

#define CGEN_MAX_IFMT_OPERANDS   16

Definition at line 879 of file cgen.h.

Definition at line 1054 of file cgen.h.

#define CGEN_MAX_SYNTAX_ELEMENTS   48

Definition at line 781 of file cgen.h.

#define CGEN_MIEXPN_FN (   ex)    ((ex)->fn)

Definition at line 1147 of file cgen.h.

#define CGEN_MIEXPN_STR (   ex)    ((ex)->str)

Definition at line 1155 of file cgen.h.

Definition at line 613 of file cgen.h.

Definition at line 959 of file cgen.h.

#define CGEN_OPCODE_BASE_VALUE (   opc)    (CGEN_OPCODE_VALUE (opc)->base_value)

Definition at line 958 of file cgen.h.

Definition at line 952 of file cgen.h.

#define CGEN_OPCODE_FORMAT (   opc)    ((opc)->format)

Definition at line 950 of file cgen.h.

#define CGEN_OPCODE_HANDLERS (   opc)    (& (opc)->handlers)

Definition at line 942 of file cgen.h.

Definition at line 953 of file cgen.h.

Definition at line 951 of file cgen.h.

#define CGEN_OPCODE_SYNTAX (   opc)    (& (opc)->syntax)

Definition at line 946 of file cgen.h.

#define CGEN_OPCODE_VALUE (   opc)    (& (opc)->value)

Definition at line 957 of file cgen.h.

#define CGEN_OPERAND_ATTR_VALUE (   operand,
  attr 
)    CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))

Definition at line 697 of file cgen.h.

#define CGEN_OPERAND_ATTRS (   operand)    (&(operand)->attrs)
#define CGEN_OPERAND_NBOOL_ATTRS   1

Definition at line 622 of file cgen.h.

#define CGEN_OPINST_ATTR (   opinst,
  attr 
)    ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
#define CGEN_OPINST_ATTRS (   opinst)    ((opinst)->attrs)
#define CGEN_OPINST_COND_REF   1
#define CGEN_PARSE_FN (   cd,
  insn 
)    (cd->parse_handlers[(insn)->opcode->handlers.parse])

Definition at line 1324 of file cgen.h.

#define CGEN_PRINT_FN (   cd,
  insn 
)    (cd->print_handlers[(insn)->opcode->handlers.print])

Definition at line 1327 of file cgen.h.

#define CGEN_SIZE_UNKNOWN   65535

Definition at line 1221 of file cgen.h.

#define CGEN_SYM (   s)    CONCAT3 (unknown,_cgen_,s)

Definition at line 47 of file cgen.h.

#define CGEN_SYNTAX_CHAR (   c)    ((unsigned char)c)

Definition at line 800 of file cgen.h.

#define CGEN_SYNTAX_CHAR_P (   c)    ((c) < 128)

Definition at line 799 of file cgen.h.

#define CGEN_SYNTAX_FIELD (   c)    ((c) - 128)

Definition at line 801 of file cgen.h.

#define CGEN_SYNTAX_MAKE_FIELD (   c)    ((c) + 128)

Definition at line 802 of file cgen.h.

#define CGEN_SYNTAX_MNEMONIC   1

Definition at line 810 of file cgen.h.

#define CGEN_SYNTAX_MNEMONIC_P (   ch)    ((ch) == CGEN_SYNTAX_MNEMONIC)

Definition at line 811 of file cgen.h.

#define CGEN_SYNTAX_STRING (   syn)    (syn->syntax)

Definition at line 798 of file cgen.h.

#define CGEN_WORD_ENDIAN (   cd)    CGEN_CPU_ENDIAN (cd)

Definition at line 1362 of file cgen.h.


Typedef Documentation

Definition at line 112 of file cgen.h.

Definition at line 113 of file cgen.h.

Definition at line 95 of file cgen.h.

typedef int( cgen_extract_fn)()

Definition at line 317 of file cgen.h.

Definition at line 233 of file cgen.h.

typedef const char*( cgen_insert_fn)()

Definition at line 296 of file cgen.h.

typedef struct cgen_insn

Definition at line 91 of file cgen.h.

typedef unsigned char* CGEN_INSN_BYTES

Definition at line 72 of file cgen.h.

Definition at line 73 of file cgen.h.

Definition at line 67 of file cgen.h.

typedef const char*( cgen_parse_fn)(CGEN_CPU_DESC, const CGEN_INSN *insn_, const char **strp_, CGEN_FIELDS *fields_)

Definition at line 278 of file cgen.h.

typedef const char*( cgen_parse_operand_fn)()

Definition at line 402 of file cgen.h.

typedef void( cgen_print_fn)()

Definition at line 335 of file cgen.h.

Definition at line 791 of file cgen.h.


Enumeration Type Documentation

Enumerator:
CGEN_ASM_NONE 
CGEN_ASM_KEYWORD 
CGEN_ASM_MAX 

Definition at line 418 of file cgen.h.

Enumerator:
CGEN_CPU_OPEN_END 
CGEN_CPU_OPEN_ISAS 
CGEN_CPU_OPEN_MACHS 
CGEN_CPU_OPEN_BFDMACH 
CGEN_CPU_OPEN_ENDIAN 

Definition at line 1375 of file cgen.h.

                       {
  CGEN_CPU_OPEN_END,
  /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified".  */
  CGEN_CPU_OPEN_ISAS,
  /* Select machine(s), arg is bitmap or 0 meaning "unspecified".  */
  CGEN_CPU_OPEN_MACHS,
  /* Select machine, arg is mach's bfd name.
     Multiple machines can be specified by repeated use.  */
  CGEN_CPU_OPEN_BFDMACH,
  /* Select endian, arg is CGEN_ENDIAN_*.  */
  CGEN_CPU_OPEN_ENDIAN
};
Enumerator:
CGEN_ENDIAN_UNKNOWN 
CGEN_ENDIAN_LITTLE 
CGEN_ENDIAN_BIG 

Definition at line 82 of file cgen.h.

Enumerator:
CGEN_HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_CR 
HW_H_DR 
HW_H_PS 
HW_H_R13 
HW_H_R14 
HW_H_R15 
HW_H_NBIT 
HW_H_ZBIT 
HW_H_VBIT 
HW_H_CBIT 
HW_H_IBIT 
HW_H_SBIT 
HW_H_TBIT 
HW_H_D0BIT 
HW_H_D1BIT 
HW_H_CCR 
HW_H_SCR 
HW_H_ILM 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_RELOC_ANN 
HW_H_PC 
HW_H_PSR_IMPLE 
HW_H_PSR_VER 
HW_H_PSR_ICE 
HW_H_PSR_NEM 
HW_H_PSR_CM 
HW_H_PSR_BE 
HW_H_PSR_ESR 
HW_H_PSR_EF 
HW_H_PSR_EM 
HW_H_PSR_PIL 
HW_H_PSR_PS 
HW_H_PSR_ET 
HW_H_PSR_S 
HW_H_TBR_TBA 
HW_H_TBR_TT 
HW_H_BPSR_BS 
HW_H_BPSR_BET 
HW_H_GR 
HW_H_GR_DOUBLE 
HW_H_GR_HI 
HW_H_GR_LO 
HW_H_FR 
HW_H_FR_DOUBLE 
HW_H_FR_INT 
HW_H_FR_HI 
HW_H_FR_LO 
HW_H_FR_0 
HW_H_FR_1 
HW_H_FR_2 
HW_H_FR_3 
HW_H_CPR 
HW_H_CPR_DOUBLE 
HW_H_SPR 
HW_H_ACCG 
HW_H_ACC40S 
HW_H_ACC40U 
HW_H_IACC0 
HW_H_ICCR 
HW_H_FCCR 
HW_H_CCCR 
HW_H_PACK 
HW_H_HINT_TAKEN 
HW_H_HINT_NOT_TAKEN 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_SPR 
HW_H_REGISTERS 
HW_H_STACK 
HW_H_PABITS 
HW_H_ZBIT 
HW_H_CBIT 
HW_H_DCBIT 
HW_H_PC 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_GR_QI 
HW_H_GR_HI 
HW_H_GR_SI 
HW_H_GR_EXT_QI 
HW_H_GR_EXT_HI 
HW_H_R0L 
HW_H_R0H 
HW_H_R1L 
HW_H_R1H 
HW_H_R0 
HW_H_R1 
HW_H_R2 
HW_H_R3 
HW_H_R0L_R0H 
HW_H_R2R0 
HW_H_R3R1 
HW_H_R1R2R0 
HW_H_AR 
HW_H_AR_QI 
HW_H_AR_HI 
HW_H_AR_SI 
HW_H_A0 
HW_H_A1 
HW_H_SB 
HW_H_FB 
HW_H_SP 
HW_H_SBIT 
HW_H_ZBIT 
HW_H_OBIT 
HW_H_CBIT 
HW_H_UBIT 
HW_H_IBIT 
HW_H_BBIT 
HW_H_DBIT 
HW_H_DCT0 
HW_H_DCT1 
HW_H_SVF 
HW_H_DRC0 
HW_H_DRC1 
HW_H_DMD0 
HW_H_DMD1 
HW_H_INTB 
HW_H_SVP 
HW_H_VCT 
HW_H_ISP 
HW_H_DMA0 
HW_H_DMA1 
HW_H_DRA0 
HW_H_DRA1 
HW_H_DSA0 
HW_H_DSA1 
HW_H_COND16 
HW_H_COND16C 
HW_H_COND16J 
HW_H_COND16J_5 
HW_H_COND32 
HW_H_CR1_32 
HW_H_CR2_32 
HW_H_CR3_32 
HW_H_CR_16 
HW_H_FLAGS 
HW_H_SHIMM 
HW_H_BIT_INDEX 
HW_H_SRC_INDEX 
HW_H_DST_INDEX 
HW_H_SRC_INDIRECT 
HW_H_DST_INDIRECT 
HW_H_NONE 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_HI16 
HW_H_SLO16 
HW_H_ULO16 
HW_H_GR 
HW_H_CR 
HW_H_ACCUM 
HW_H_ACCUMS 
HW_H_COND 
HW_H_PSW 
HW_H_BPSW 
HW_H_BBPSW 
HW_H_LOCK 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GPR 
HW_H_CSR 
HW_H_CR64 
HW_H_CR 
HW_H_CCR 
HW_H_CR_FMAX 
HW_H_CCR_FMAX 
HW_H_FMAX_COMPARE_I_P 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_SPR 
HW_H_PC 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_SR 
HW_H_HI16 
HW_H_LO16 
HW_H_CBIT 
HW_H_DELAY_INSN 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_EXT 
HW_H_PSW 
HW_H_GRB 
HW_H_CC 
HW_H_ECC 
HW_H_GRB8 
HW_H_R8 
HW_H_REGMEM8 
HW_H_REGDIV8 
HW_H_R0 
HW_H_R01 
HW_H_REGBMEM8 
HW_H_MEMGR8 
HW_H_COND 
HW_H_CBIT 
HW_H_SGTDIS 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_RB 
HW_H_RBJ 
HW_H_RPSW 
HW_H_Z8 
HW_H_Z16 
HW_H_CY 
HW_H_HC 
HW_H_OV 
HW_H_PT 
HW_H_S 
HW_H_BRANCHCOND 
HW_H_WORDSIZE 
HW_MAX 

Definition at line 424 of file cgen.h.

Enumerator:
CGEN_INSN_ALIAS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_NOT_IN_DELAY_SLOT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_PRIVILEGED 
CGEN_INSN_NON_EXCEPTING 
CGEN_INSN_CONDITIONAL 
CGEN_INSN_FR_ACCESS 
CGEN_INSN_PRESERVE_OVF 
CGEN_INSN_AUDIO 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_UNIT 
CGEN_INSN_FR400_MAJOR 
CGEN_INSN_FR450_MAJOR 
CGEN_INSN_FR500_MAJOR 
CGEN_INSN_FR550_MAJOR 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_EXT_SKIP_INSN 
CGEN_INSN_SKIPA 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_YIELD_INSN 
CGEN_INSN_LOAD_DELAY 
CGEN_INSN_EVEN_REG_NUM 
CGEN_INSN_UNSUPPORTED 
CGEN_INSN_USES_RD 
CGEN_INSN_USES_RS 
CGEN_INSN_USES_RT 
CGEN_INSN_USES_R31 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_ISA 
CGEN_INSN_RL_TYPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_FILL_SLOT 
CGEN_INSN_SPECIAL 
CGEN_INSN_SPECIAL_M32R 
CGEN_INSN_SPECIAL_FLOAT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_PIPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_OPTIONAL_BIT_INSN 
CGEN_INSN_OPTIONAL_MUL_INSN 
CGEN_INSN_OPTIONAL_DIV_INSN 
CGEN_INSN_OPTIONAL_DEBUG_INSN 
CGEN_INSN_OPTIONAL_LDZ_INSN 
CGEN_INSN_OPTIONAL_ABS_INSN 
CGEN_INSN_OPTIONAL_AVE_INSN 
CGEN_INSN_OPTIONAL_MINMAX_INSN 
CGEN_INSN_OPTIONAL_CLIP_INSN 
CGEN_INSN_OPTIONAL_SAT_INSN 
CGEN_INSN_OPTIONAL_UCI_INSN 
CGEN_INSN_OPTIONAL_DSP_INSN 
CGEN_INSN_OPTIONAL_CP_INSN 
CGEN_INSN_OPTIONAL_CP64_INSN 
CGEN_INSN_OPTIONAL_VLIW64 
CGEN_INSN_MAY_TRAP 
CGEN_INSN_VLIW_ALONE 
CGEN_INSN_VLIW_NO_CORE_NOP 
CGEN_INSN_VLIW_NO_COP_NOP 
CGEN_INSN_VLIW64_NO_MATCHING_NOP 
CGEN_INSN_VLIW32_NO_MATCHING_NOP 
CGEN_INSN_VOLATILE 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_ISA 
CGEN_INSN_LATENCY 
CGEN_INSN_CONFIG 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_LOAD_DELAY 
CGEN_INSN_MEMORY_ACCESS 
CGEN_INSN_AL_INSN 
CGEN_INSN_IO_INSN 
CGEN_INSN_BR_INSN 
CGEN_INSN_JAL_HAZARD 
CGEN_INSN_USES_FRDR 
CGEN_INSN_USES_FRDRRR 
CGEN_INSN_USES_FRSR1 
CGEN_INSN_USES_FRSR2 
CGEN_INSN_SKIPA 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_NOT_IN_DELAY_SLOT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_PIPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 

Definition at line 975 of file cgen.h.

enum cgen_mode
Enumerator:
CGEN_MODE_VOID 
CGEN_MODE_BI 
CGEN_MODE_QI 
CGEN_MODE_HI 
CGEN_MODE_SI 
CGEN_MODE_DI 
CGEN_MODE_UBI 
CGEN_MODE_UQI 
CGEN_MODE_UHI 
CGEN_MODE_USI 
CGEN_MODE_UDI 
CGEN_MODE_SF 
CGEN_MODE_DF 
CGEN_MODE_XF 
CGEN_MODE_TF 
CGEN_MODE_TARGET_MAX 
CGEN_MODE_INT 
CGEN_MODE_UINT 
CGEN_MODE_MAX 

Definition at line 601 of file cgen.h.

Enumerator:
CGEN_OPERAND_MAX 
FR30_OPERAND_PC 
FR30_OPERAND_RI 
FR30_OPERAND_RJ 
FR30_OPERAND_RIC 
FR30_OPERAND_RJC 
FR30_OPERAND_CRI 
FR30_OPERAND_CRJ 
FR30_OPERAND_RS1 
FR30_OPERAND_RS2 
FR30_OPERAND_R13 
FR30_OPERAND_R14 
FR30_OPERAND_R15 
FR30_OPERAND_PS 
FR30_OPERAND_U4 
FR30_OPERAND_U4C 
FR30_OPERAND_U8 
FR30_OPERAND_I8 
FR30_OPERAND_UDISP6 
FR30_OPERAND_DISP8 
FR30_OPERAND_DISP9 
FR30_OPERAND_DISP10 
FR30_OPERAND_S10 
FR30_OPERAND_U10 
FR30_OPERAND_I32 
FR30_OPERAND_M4 
FR30_OPERAND_I20 
FR30_OPERAND_DIR8 
FR30_OPERAND_DIR9 
FR30_OPERAND_DIR10 
FR30_OPERAND_LABEL9 
FR30_OPERAND_LABEL12 
FR30_OPERAND_REGLIST_LOW_LD 
FR30_OPERAND_REGLIST_HI_LD 
FR30_OPERAND_REGLIST_LOW_ST 
FR30_OPERAND_REGLIST_HI_ST 
FR30_OPERAND_CC 
FR30_OPERAND_CCC 
FR30_OPERAND_NBIT 
FR30_OPERAND_VBIT 
FR30_OPERAND_ZBIT 
FR30_OPERAND_CBIT 
FR30_OPERAND_IBIT 
FR30_OPERAND_SBIT 
FR30_OPERAND_TBIT 
FR30_OPERAND_D0BIT 
FR30_OPERAND_D1BIT 
FR30_OPERAND_CCR 
FR30_OPERAND_SCR 
FR30_OPERAND_ILM 
FR30_OPERAND_MAX 
FRV_OPERAND_PC 
FRV_OPERAND_PACK 
FRV_OPERAND_GRI 
FRV_OPERAND_GRJ 
FRV_OPERAND_GRK 
FRV_OPERAND_GRKHI 
FRV_OPERAND_GRKLO 
FRV_OPERAND_GRDOUBLEK 
FRV_OPERAND_ACC40SI 
FRV_OPERAND_ACC40UI 
FRV_OPERAND_ACC40SK 
FRV_OPERAND_ACC40UK 
FRV_OPERAND_ACCGI 
FRV_OPERAND_ACCGK 
FRV_OPERAND_CPRI 
FRV_OPERAND_CPRJ 
FRV_OPERAND_CPRK 
FRV_OPERAND_CPRDOUBLEK 
FRV_OPERAND_FRINTI 
FRV_OPERAND_FRINTJ 
FRV_OPERAND_FRINTK 
FRV_OPERAND_FRI 
FRV_OPERAND_FRJ 
FRV_OPERAND_FRK 
FRV_OPERAND_FRKHI 
FRV_OPERAND_FRKLO 
FRV_OPERAND_FRDOUBLEI 
FRV_OPERAND_FRDOUBLEJ 
FRV_OPERAND_FRDOUBLEK 
FRV_OPERAND_CRI 
FRV_OPERAND_CRJ 
FRV_OPERAND_CRJ_INT 
FRV_OPERAND_CRJ_FLOAT 
FRV_OPERAND_CRK 
FRV_OPERAND_CCI 
FRV_OPERAND_ICCI_1 
FRV_OPERAND_ICCI_2 
FRV_OPERAND_ICCI_3 
FRV_OPERAND_FCCI_1 
FRV_OPERAND_FCCI_2 
FRV_OPERAND_FCCI_3 
FRV_OPERAND_FCCK 
FRV_OPERAND_EIR 
FRV_OPERAND_S10 
FRV_OPERAND_U16 
FRV_OPERAND_S16 
FRV_OPERAND_S6 
FRV_OPERAND_S6_1 
FRV_OPERAND_U6 
FRV_OPERAND_S5 
FRV_OPERAND_COND 
FRV_OPERAND_CCOND 
FRV_OPERAND_HINT 
FRV_OPERAND_HINT_TAKEN 
FRV_OPERAND_HINT_NOT_TAKEN 
FRV_OPERAND_LI 
FRV_OPERAND_LOCK 
FRV_OPERAND_DEBUG 
FRV_OPERAND_AE 
FRV_OPERAND_LABEL16 
FRV_OPERAND_LRAE 
FRV_OPERAND_LRAD 
FRV_OPERAND_LRAS 
FRV_OPERAND_TLBPROPX 
FRV_OPERAND_TLBPRL 
FRV_OPERAND_A0 
FRV_OPERAND_A1 
FRV_OPERAND_FRINTIEVEN 
FRV_OPERAND_FRINTJEVEN 
FRV_OPERAND_FRINTKEVEN 
FRV_OPERAND_D12 
FRV_OPERAND_S12 
FRV_OPERAND_U12 
FRV_OPERAND_SPR 
FRV_OPERAND_ULO16 
FRV_OPERAND_SLO16 
FRV_OPERAND_UHI16 
FRV_OPERAND_LABEL24 
FRV_OPERAND_PSR_ESR 
FRV_OPERAND_PSR_S 
FRV_OPERAND_PSR_PS 
FRV_OPERAND_PSR_ET 
FRV_OPERAND_BPSR_BS 
FRV_OPERAND_BPSR_BET 
FRV_OPERAND_TBR_TBA 
FRV_OPERAND_TBR_TT 
FRV_OPERAND_LDANN 
FRV_OPERAND_LDDANN 
FRV_OPERAND_CALLANN 
FRV_OPERAND_MAX 
IP2K_OPERAND_PC 
IP2K_OPERAND_ADDR16CJP 
IP2K_OPERAND_FR 
IP2K_OPERAND_LIT8 
IP2K_OPERAND_BITNO 
IP2K_OPERAND_ADDR16P 
IP2K_OPERAND_ADDR16H 
IP2K_OPERAND_ADDR16L 
IP2K_OPERAND_RETI3 
IP2K_OPERAND_PABITS 
IP2K_OPERAND_ZBIT 
IP2K_OPERAND_CBIT 
IP2K_OPERAND_DCBIT 
IP2K_OPERAND_MAX 
IQ2000_OPERAND_PC 
IQ2000_OPERAND_RS 
IQ2000_OPERAND_RT 
IQ2000_OPERAND_RD 
IQ2000_OPERAND_RD_RS 
IQ2000_OPERAND_RD_RT 
IQ2000_OPERAND_RT_RS 
IQ2000_OPERAND_SHAMT 
IQ2000_OPERAND_IMM 
IQ2000_OPERAND_OFFSET 
IQ2000_OPERAND_BASEOFF 
IQ2000_OPERAND_JMPTARG 
IQ2000_OPERAND_MASK 
IQ2000_OPERAND_MASKQ10 
IQ2000_OPERAND_MASKL 
IQ2000_OPERAND_COUNT 
IQ2000_OPERAND__INDEX 
IQ2000_OPERAND_EXECODE 
IQ2000_OPERAND_BYTECOUNT 
IQ2000_OPERAND_CAM_Y 
IQ2000_OPERAND_CAM_Z 
IQ2000_OPERAND_CM_3FUNC 
IQ2000_OPERAND_CM_4FUNC 
IQ2000_OPERAND_CM_3Z 
IQ2000_OPERAND_CM_4Z 
IQ2000_OPERAND_BASE 
IQ2000_OPERAND_MASKR 
IQ2000_OPERAND_BITNUM 
IQ2000_OPERAND_HI16 
IQ2000_OPERAND_LO16 
IQ2000_OPERAND_MLO16 
IQ2000_OPERAND_JMPTARGQ10 
IQ2000_OPERAND_MAX 
M32C_OPERAND_PC 
M32C_OPERAND_SRC16RNQI 
M32C_OPERAND_SRC16RNHI 
M32C_OPERAND_SRC32RNUNPREFIXEDQI 
M32C_OPERAND_SRC32RNUNPREFIXEDHI 
M32C_OPERAND_SRC32RNUNPREFIXEDSI 
M32C_OPERAND_SRC32RNPREFIXEDQI 
M32C_OPERAND_SRC32RNPREFIXEDHI 
M32C_OPERAND_SRC32RNPREFIXEDSI 
M32C_OPERAND_SRC16AN 
M32C_OPERAND_SRC16ANQI 
M32C_OPERAND_SRC16ANHI 
M32C_OPERAND_SRC32ANUNPREFIXED 
M32C_OPERAND_SRC32ANUNPREFIXEDQI 
M32C_OPERAND_SRC32ANUNPREFIXEDHI 
M32C_OPERAND_SRC32ANUNPREFIXEDSI 
M32C_OPERAND_SRC32ANPREFIXED 
M32C_OPERAND_SRC32ANPREFIXEDQI 
M32C_OPERAND_SRC32ANPREFIXEDHI 
M32C_OPERAND_SRC32ANPREFIXEDSI 
M32C_OPERAND_DST16RNQI 
M32C_OPERAND_DST16RNHI 
M32C_OPERAND_DST16RNSI 
M32C_OPERAND_DST16RNEXTQI 
M32C_OPERAND_DST32R0QI_S 
M32C_OPERAND_DST32R0HI_S 
M32C_OPERAND_DST32RNUNPREFIXEDQI 
M32C_OPERAND_DST32RNUNPREFIXEDHI 
M32C_OPERAND_DST32RNUNPREFIXEDSI 
M32C_OPERAND_DST32RNEXTUNPREFIXEDQI 
M32C_OPERAND_DST32RNEXTUNPREFIXEDHI 
M32C_OPERAND_DST32RNPREFIXEDQI 
M32C_OPERAND_DST32RNPREFIXEDHI 
M32C_OPERAND_DST32RNPREFIXEDSI 
M32C_OPERAND_DST16RNQI_S 
M32C_OPERAND_DST16ANQI_S 
M32C_OPERAND_BIT16RN 
M32C_OPERAND_BIT32RNPREFIXED 
M32C_OPERAND_BIT32RNUNPREFIXED 
M32C_OPERAND_R0 
M32C_OPERAND_R1 
M32C_OPERAND_R2 
M32C_OPERAND_R3 
M32C_OPERAND_R0L 
M32C_OPERAND_R0H 
M32C_OPERAND_R2R0 
M32C_OPERAND_R3R1 
M32C_OPERAND_R1R2R0 
M32C_OPERAND_DST16AN 
M32C_OPERAND_DST16ANQI 
M32C_OPERAND_DST16ANHI 
M32C_OPERAND_DST16ANSI 
M32C_OPERAND_DST16AN_S 
M32C_OPERAND_DST32ANUNPREFIXED 
M32C_OPERAND_DST32ANUNPREFIXEDQI 
M32C_OPERAND_DST32ANUNPREFIXEDHI 
M32C_OPERAND_DST32ANUNPREFIXEDSI 
M32C_OPERAND_DST32ANEXTUNPREFIXED 
M32C_OPERAND_DST32ANPREFIXED 
M32C_OPERAND_DST32ANPREFIXEDQI 
M32C_OPERAND_DST32ANPREFIXEDHI 
M32C_OPERAND_DST32ANPREFIXEDSI 
M32C_OPERAND_BIT16AN 
M32C_OPERAND_BIT32ANPREFIXED 
M32C_OPERAND_BIT32ANUNPREFIXED 
M32C_OPERAND_A0 
M32C_OPERAND_A1 
M32C_OPERAND_SB 
M32C_OPERAND_FB 
M32C_OPERAND_SP 
M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL 
M32C_OPERAND_REGSETPOP 
M32C_OPERAND_REGSETPUSH 
M32C_OPERAND_RN16_PUSH_S 
M32C_OPERAND_AN16_PUSH_S 
M32C_OPERAND_DSP_8_U6 
M32C_OPERAND_DSP_8_U8 
M32C_OPERAND_DSP_8_U16 
M32C_OPERAND_DSP_8_S8 
M32C_OPERAND_DSP_8_S24 
M32C_OPERAND_DSP_8_U24 
M32C_OPERAND_DSP_10_U6 
M32C_OPERAND_DSP_16_U8 
M32C_OPERAND_DSP_16_U16 
M32C_OPERAND_DSP_16_U20 
M32C_OPERAND_DSP_16_U24 
M32C_OPERAND_DSP_16_S8 
M32C_OPERAND_DSP_16_S16 
M32C_OPERAND_DSP_24_U8 
M32C_OPERAND_DSP_24_U16 
M32C_OPERAND_DSP_24_U20 
M32C_OPERAND_DSP_24_U24 
M32C_OPERAND_DSP_24_S8 
M32C_OPERAND_DSP_24_S16 
M32C_OPERAND_DSP_32_U8 
M32C_OPERAND_DSP_32_U16 
M32C_OPERAND_DSP_32_U24 
M32C_OPERAND_DSP_32_U20 
M32C_OPERAND_DSP_32_S8 
M32C_OPERAND_DSP_32_S16 
M32C_OPERAND_DSP_40_U8 
M32C_OPERAND_DSP_40_S8 
M32C_OPERAND_DSP_40_U16 
M32C_OPERAND_DSP_40_S16 
M32C_OPERAND_DSP_40_U20 
M32C_OPERAND_DSP_40_U24 
M32C_OPERAND_DSP_48_U8 
M32C_OPERAND_DSP_48_S8 
M32C_OPERAND_DSP_48_U16 
M32C_OPERAND_DSP_48_S16 
M32C_OPERAND_DSP_48_U20 
M32C_OPERAND_DSP_48_U24 
M32C_OPERAND_IMM_8_S4 
M32C_OPERAND_IMM_8_S4N 
M32C_OPERAND_IMM_SH_8_S4 
M32C_OPERAND_IMM_8_QI 
M32C_OPERAND_IMM_8_HI 
M32C_OPERAND_IMM_12_S4 
M32C_OPERAND_IMM_12_S4N 
M32C_OPERAND_IMM_SH_12_S4 
M32C_OPERAND_IMM_13_U3 
M32C_OPERAND_IMM_20_S4 
M32C_OPERAND_IMM_SH_20_S4 
M32C_OPERAND_IMM_16_QI 
M32C_OPERAND_IMM_16_HI 
M32C_OPERAND_IMM_16_SI 
M32C_OPERAND_IMM_24_QI 
M32C_OPERAND_IMM_24_HI 
M32C_OPERAND_IMM_24_SI 
M32C_OPERAND_IMM_32_QI 
M32C_OPERAND_IMM_32_SI 
M32C_OPERAND_IMM_32_HI 
M32C_OPERAND_IMM_40_QI 
M32C_OPERAND_IMM_40_HI 
M32C_OPERAND_IMM_40_SI 
M32C_OPERAND_IMM_48_QI 
M32C_OPERAND_IMM_48_HI 
M32C_OPERAND_IMM_48_SI 
M32C_OPERAND_IMM_56_QI 
M32C_OPERAND_IMM_56_HI 
M32C_OPERAND_IMM_64_HI 
M32C_OPERAND_IMM1_S 
M32C_OPERAND_IMM3_S 
M32C_OPERAND_BIT3_S 
M32C_OPERAND_BITNO16R 
M32C_OPERAND_BITNO32PREFIXED 
M32C_OPERAND_BITNO32UNPREFIXED 
M32C_OPERAND_BITBASE16_16_U8 
M32C_OPERAND_BITBASE16_16_S8 
M32C_OPERAND_BITBASE16_16_U16 
M32C_OPERAND_BITBASE16_8_U11_S 
M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED 
M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED 
M32C_OPERAND_BITBASE32_24_U11_PREFIXED 
M32C_OPERAND_BITBASE32_24_S11_PREFIXED 
M32C_OPERAND_BITBASE32_24_U19_PREFIXED 
M32C_OPERAND_BITBASE32_24_S19_PREFIXED 
M32C_OPERAND_BITBASE32_24_U27_PREFIXED 
M32C_OPERAND_LAB_5_3 
M32C_OPERAND_LAB32_JMP_S 
M32C_OPERAND_LAB_8_8 
M32C_OPERAND_LAB_8_16 
M32C_OPERAND_LAB_8_24 
M32C_OPERAND_LAB_16_8 
M32C_OPERAND_LAB_24_8 
M32C_OPERAND_LAB_32_8 
M32C_OPERAND_LAB_40_8 
M32C_OPERAND_SBIT 
M32C_OPERAND_OBIT 
M32C_OPERAND_ZBIT 
M32C_OPERAND_CBIT 
M32C_OPERAND_UBIT 
M32C_OPERAND_IBIT 
M32C_OPERAND_BBIT 
M32C_OPERAND_DBIT 
M32C_OPERAND_COND16_16 
M32C_OPERAND_COND16_24 
M32C_OPERAND_COND16_32 
M32C_OPERAND_COND32_16 
M32C_OPERAND_COND32_24 
M32C_OPERAND_COND32_32 
M32C_OPERAND_COND32_40 
M32C_OPERAND_COND16C 
M32C_OPERAND_COND16J 
M32C_OPERAND_COND16J5 
M32C_OPERAND_COND32 
M32C_OPERAND_COND32J 
M32C_OPERAND_SCCOND32 
M32C_OPERAND_FLAGS16 
M32C_OPERAND_FLAGS32 
M32C_OPERAND_CR16 
M32C_OPERAND_CR1_UNPREFIXED_32 
M32C_OPERAND_CR1_PREFIXED_32 
M32C_OPERAND_CR2_32 
M32C_OPERAND_CR3_UNPREFIXED_32 
M32C_OPERAND_CR3_PREFIXED_32 
M32C_OPERAND_Z 
M32C_OPERAND_S 
M32C_OPERAND_Q 
M32C_OPERAND_G 
M32C_OPERAND_X 
M32C_OPERAND_SIZE 
M32C_OPERAND_BITINDEX 
M32C_OPERAND_SRCINDEX 
M32C_OPERAND_DSTINDEX 
M32C_OPERAND_NOREMAINDER 
M32C_OPERAND_SRC16_RN_DIRECT_QI 
M32C_OPERAND_SRC16_RN_DIRECT_HI 
M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI 
M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI 
M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI 
M32C_OPERAND_SRC16_AN_DIRECT_QI 
M32C_OPERAND_SRC16_AN_DIRECT_HI 
M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI 
M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI 
M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI 
M32C_OPERAND_SRC16_AN_INDIRECT_QI 
M32C_OPERAND_SRC16_AN_INDIRECT_HI 
M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI 
M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI 
M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI 
M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI 
M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI 
M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI 
M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI 
M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI 
M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI 
M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI 
M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI 
M32C_OPERAND_SRC16_16_20_AN_RELATIVE_QI 
M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI 
M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI 
M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI 
M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI 
M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI 
M32C_OPERAND_SRC16_16_20_AN_RELATIVE_HI 
M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI 
M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI 
M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI 
M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI 
M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI 
M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI 
M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI 
M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI 
M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI 
M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI 
M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_RN_DIRECT_QI 
M32C_OPERAND_DST16_RN_DIRECT_HI 
M32C_OPERAND_DST16_RN_DIRECT_SI 
M32C_OPERAND_DST16_RN_DIRECT_EXT_QI 
M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI 
M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI 
M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI 
M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST16_AN_DIRECT_QI 
M32C_OPERAND_DST16_AN_DIRECT_HI 
M32C_OPERAND_DST16_AN_DIRECT_SI 
M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI 
M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI 
M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI 
M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI 
M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI 
M32C_OPERAND_DST16_AN_INDIRECT_QI 
M32C_OPERAND_DST16_AN_INDIRECT_HI 
M32C_OPERAND_DST16_AN_INDIRECT_SI 
M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI 
M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI 
M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI 
M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI 
M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_16_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_24_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_32_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_40_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI 
M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI 
M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI 
M32C_OPERAND_DST16_48_20_AN_RELATIVE_QI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_16_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_24_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_32_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_40_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI 
M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI 
M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI 
M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI 
M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI 
M32C_OPERAND_DST16_48_20_AN_RELATIVE_HI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_16_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_24_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_32_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_40_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI 
M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI 
M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI 
M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI 
M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI 
M32C_OPERAND_DST16_48_20_AN_RELATIVE_SI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_24_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_32_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_40_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_48_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_24_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_32_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_40_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_48_16_ABSOLUTE_HI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_24_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_32_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_40_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_48_16_ABSOLUTE_SI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI 
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M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI 
M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI 
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M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI 
M32C_OPERAND_BIT16_RN_DIRECT 
M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED 
M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED 
M32C_OPERAND_BIT16_AN_DIRECT 
M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED 
M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED 
M32C_OPERAND_BIT16_AN_INDIRECT 
M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED 
M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED 
M32C_OPERAND_BIT16_16_8_SB_RELATIVE 
M32C_OPERAND_BIT16_16_16_SB_RELATIVE 
M32C_OPERAND_BIT16_16_8_FB_RELATIVE 
M32C_OPERAND_BIT16_16_8_AN_RELATIVE 
M32C_OPERAND_BIT16_16_16_AN_RELATIVE 
M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED 
M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED 
M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED 
M32C_OPERAND_BIT16_11_SB_RELATIVE_S 
M32C_OPERAND_RN16_PUSH_S_DERIVED 
M32C_OPERAND_AN16_PUSH_S_DERIVED 
M32C_OPERAND_BIT16_16_16_ABSOLUTE 
M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED 
M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED 
M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED 
M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED 
M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI 
M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI 
M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI 
M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI 
M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI 
M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED 
M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI 
M32C_OPERAND_DST32_2_S_R0_DIRECT_HI 
M32C_OPERAND_DST32_1_S_A0_DIRECT_HI 
M32C_OPERAND_DST32_1_S_A1_DIRECT_HI 
M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI 
M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI 
M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI 
M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI 
M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI 
M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI 
M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI 
M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI 
M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI 
M32C_OPERAND_SRC16_BASIC_QI 
M32C_OPERAND_SRC16_BASIC_HI 
M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI 
M32C_OPERAND_SRC32_BASIC_PREFIXED_QI 
M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI 
M32C_OPERAND_SRC32_BASIC_PREFIXED_HI 
M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI 
M32C_OPERAND_SRC32_BASIC_PREFIXED_SI 
M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI 
M32C_OPERAND_SRC16_16_8_QI 
M32C_OPERAND_SRC16_16_16_QI 
M32C_OPERAND_SRC16_16_8_HI 
M32C_OPERAND_SRC16_16_16_HI 
M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI 
M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI 
M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI 
M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI 
M32C_OPERAND_SRC32_24_8_PREFIXED_QI 
M32C_OPERAND_SRC32_24_16_PREFIXED_QI 
M32C_OPERAND_SRC32_24_24_PREFIXED_QI 
M32C_OPERAND_SRC32_24_8_PREFIXED_HI 
M32C_OPERAND_SRC32_24_16_PREFIXED_HI 
M32C_OPERAND_SRC32_24_24_PREFIXED_HI 
M32C_OPERAND_SRC32_24_8_PREFIXED_SI 
M32C_OPERAND_SRC32_24_16_PREFIXED_SI 
M32C_OPERAND_SRC32_24_24_PREFIXED_SI 
M32C_OPERAND_DST16_BASIC_QI 
M32C_OPERAND_DST16_BASIC_HI 
M32C_OPERAND_DST16_BASIC_SI 
M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI 
M32C_OPERAND_DST32_BASIC_PREFIXED_QI 
M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI 
M32C_OPERAND_DST32_BASIC_PREFIXED_HI 
M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI 
M32C_OPERAND_DST32_BASIC_PREFIXED_SI 
M32C_OPERAND_DST16_16_QI 
M32C_OPERAND_DST16_16_8_QI 
M32C_OPERAND_DST16_16_16_QI 
M32C_OPERAND_DST16_16_16SA_QI 
M32C_OPERAND_DST16_16_20AR_QI 
M32C_OPERAND_DST16_16_HI 
M32C_OPERAND_DST16_16_8_HI 
M32C_OPERAND_DST16_16_16_HI 
M32C_OPERAND_DST16_16_16SA_HI 
M32C_OPERAND_DST16_16_20AR_HI 
M32C_OPERAND_DST16_16_SI 
M32C_OPERAND_DST16_16_8_SI 
M32C_OPERAND_DST16_16_16_SI 
M32C_OPERAND_DST16_16_16SA_SI 
M32C_OPERAND_DST16_16_20AR_SI 
M32C_OPERAND_DST16_16_EXT_QI 
M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI 
M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI 
M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI 
M32C_OPERAND_DST16_16_MOVA_HI 
M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI 
M32C_OPERAND_DST32_16_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_8_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_16SA_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_24_UNPREFIXED_QI 
M32C_OPERAND_DST32_16_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_8_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_16SA_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_24_UNPREFIXED_HI 
M32C_OPERAND_DST32_16_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_8_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_16SA_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_24_UNPREFIXED_SI 
M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI 
M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI 
M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI 
M32C_OPERAND_DST16_24_QI 
M32C_OPERAND_DST16_24_HI 
M32C_OPERAND_DST32_24_UNPREFIXED_QI 
M32C_OPERAND_DST32_24_PREFIXED_QI 
M32C_OPERAND_DST32_24_8_PREFIXED_QI 
M32C_OPERAND_DST32_24_16_PREFIXED_QI 
M32C_OPERAND_DST32_24_24_PREFIXED_QI 
M32C_OPERAND_DST32_24_UNPREFIXED_HI 
M32C_OPERAND_DST32_24_PREFIXED_HI 
M32C_OPERAND_DST32_24_8_PREFIXED_HI 
M32C_OPERAND_DST32_24_16_PREFIXED_HI 
M32C_OPERAND_DST32_24_24_PREFIXED_HI 
M32C_OPERAND_DST32_24_UNPREFIXED_SI 
M32C_OPERAND_DST32_24_PREFIXED_SI 
M32C_OPERAND_DST32_24_8_PREFIXED_SI 
M32C_OPERAND_DST32_24_16_PREFIXED_SI 
M32C_OPERAND_DST32_24_24_PREFIXED_SI 
M32C_OPERAND_DST16_32_QI 
M32C_OPERAND_DST16_32_HI 
M32C_OPERAND_DST32_32_UNPREFIXED_QI 
M32C_OPERAND_DST32_32_PREFIXED_QI 
M32C_OPERAND_DST32_32_UNPREFIXED_HI 
M32C_OPERAND_DST32_32_PREFIXED_HI 
M32C_OPERAND_DST32_32_UNPREFIXED_SI 
M32C_OPERAND_DST32_32_PREFIXED_SI 
M32C_OPERAND_DST32_40_UNPREFIXED_QI 
M32C_OPERAND_DST32_40_PREFIXED_QI 
M32C_OPERAND_DST32_40_UNPREFIXED_HI 
M32C_OPERAND_DST32_40_PREFIXED_HI 
M32C_OPERAND_DST32_40_UNPREFIXED_SI 
M32C_OPERAND_DST32_40_PREFIXED_SI 
M32C_OPERAND_DST32_48_PREFIXED_QI 
M32C_OPERAND_DST32_48_PREFIXED_HI 
M32C_OPERAND_DST32_48_PREFIXED_SI 
M32C_OPERAND_BIT16_16 
M32C_OPERAND_BIT16_16_BASIC 
M32C_OPERAND_BIT16_16_8 
M32C_OPERAND_BIT16_16_16 
M32C_OPERAND_BIT32_16_UNPREFIXED 
M32C_OPERAND_BIT32_24_PREFIXED 
M32C_OPERAND_BIT32_BASIC_UNPREFIXED 
M32C_OPERAND_BIT32_16_8_UNPREFIXED 
M32C_OPERAND_BIT32_16_16_UNPREFIXED 
M32C_OPERAND_BIT32_16_24_UNPREFIXED 
M32C_OPERAND_SRC16_2_S 
M32C_OPERAND_SRC32_2_S_QI 
M32C_OPERAND_SRC32_2_S_HI 
M32C_OPERAND_DST16_3_S_8 
M32C_OPERAND_DST16_3_S_16 
M32C_OPERAND_SRCDST16_R0L_R0H_S 
M32C_OPERAND_DST32_2_S_BASIC_QI 
M32C_OPERAND_DST32_2_S_BASIC_HI 
M32C_OPERAND_DST32_2_S_8_QI 
M32C_OPERAND_DST32_2_S_16_QI 
M32C_OPERAND_DST32_2_S_8_HI 
M32C_OPERAND_DST32_2_S_16_HI 
M32C_OPERAND_DST32_2_S_8_SI 
M32C_OPERAND_DST32_2_S_16_SI 
M32C_OPERAND_DST32_AN_S 
M32C_OPERAND_BIT16_11_S 
M32C_OPERAND_RN16_PUSH_S_ANYOF 
M32C_OPERAND_AN16_PUSH_S_ANYOF 
M32C_OPERAND_MAX 
M32R_OPERAND_PC 
M32R_OPERAND_SR 
M32R_OPERAND_DR 
M32R_OPERAND_SRC1 
M32R_OPERAND_SRC2 
M32R_OPERAND_SCR 
M32R_OPERAND_DCR 
M32R_OPERAND_SIMM8 
M32R_OPERAND_SIMM16 
M32R_OPERAND_UIMM3 
M32R_OPERAND_UIMM4 
M32R_OPERAND_UIMM5 
M32R_OPERAND_UIMM8 
M32R_OPERAND_UIMM16 
M32R_OPERAND_IMM1 
M32R_OPERAND_ACCD 
M32R_OPERAND_ACCS 
M32R_OPERAND_ACC 
M32R_OPERAND_HASH 
M32R_OPERAND_HI16 
M32R_OPERAND_SLO16 
M32R_OPERAND_ULO16 
M32R_OPERAND_UIMM24 
M32R_OPERAND_DISP8 
M32R_OPERAND_DISP16 
M32R_OPERAND_DISP24 
M32R_OPERAND_CONDBIT 
M32R_OPERAND_ACCUM 
M32R_OPERAND_MAX 
MEP_OPERAND_PC 
MEP_OPERAND_R0 
MEP_OPERAND_RN 
MEP_OPERAND_RM 
MEP_OPERAND_RL 
MEP_OPERAND_RN3 
MEP_OPERAND_RMA 
MEP_OPERAND_RNC 
MEP_OPERAND_RNUC 
MEP_OPERAND_RNS 
MEP_OPERAND_RNUS 
MEP_OPERAND_RNL 
MEP_OPERAND_RNUL 
MEP_OPERAND_RN3C 
MEP_OPERAND_RN3UC 
MEP_OPERAND_RN3S 
MEP_OPERAND_RN3US 
MEP_OPERAND_RN3L 
MEP_OPERAND_RN3UL 
MEP_OPERAND_LP 
MEP_OPERAND_SAR 
MEP_OPERAND_HI 
MEP_OPERAND_LO 
MEP_OPERAND_MB0 
MEP_OPERAND_ME0 
MEP_OPERAND_MB1 
MEP_OPERAND_ME1 
MEP_OPERAND_PSW 
MEP_OPERAND_EPC 
MEP_OPERAND_EXC 
MEP_OPERAND_NPC 
MEP_OPERAND_DBG 
MEP_OPERAND_DEPC 
MEP_OPERAND_OPT 
MEP_OPERAND_R1 
MEP_OPERAND_TP 
MEP_OPERAND_SP 
MEP_OPERAND_TPR 
MEP_OPERAND_SPR 
MEP_OPERAND_CSRN 
MEP_OPERAND_CSRN_IDX 
MEP_OPERAND_CRN64 
MEP_OPERAND_CRN 
MEP_OPERAND_CRNX64 
MEP_OPERAND_CRNX 
MEP_OPERAND_CCRN 
MEP_OPERAND_CCCC 
MEP_OPERAND_PCREL8A2 
MEP_OPERAND_PCREL12A2 
MEP_OPERAND_PCREL17A2 
MEP_OPERAND_PCREL24A2 
MEP_OPERAND_PCABS24A2 
MEP_OPERAND_SDISP16 
MEP_OPERAND_SIMM16 
MEP_OPERAND_UIMM16 
MEP_OPERAND_CODE16 
MEP_OPERAND_UDISP2 
MEP_OPERAND_UIMM2 
MEP_OPERAND_SIMM6 
MEP_OPERAND_SIMM8 
MEP_OPERAND_ADDR24A4 
MEP_OPERAND_CODE24 
MEP_OPERAND_CALLNUM 
MEP_OPERAND_UIMM3 
MEP_OPERAND_UIMM4 
MEP_OPERAND_UIMM5 
MEP_OPERAND_UDISP7 
MEP_OPERAND_UDISP7A2 
MEP_OPERAND_UDISP7A4 
MEP_OPERAND_UIMM7A4 
MEP_OPERAND_UIMM24 
MEP_OPERAND_CIMM4 
MEP_OPERAND_CIMM5 
MEP_OPERAND_CDISP8 
MEP_OPERAND_CDISP8A2 
MEP_OPERAND_CDISP8A4 
MEP_OPERAND_CDISP8A8 
MEP_OPERAND_ZERO 
MEP_OPERAND_CP_FLAG 
MEP_OPERAND_FMAX_FRD 
MEP_OPERAND_FMAX_FRN 
MEP_OPERAND_FMAX_FRM 
MEP_OPERAND_FMAX_FRD_INT 
MEP_OPERAND_FMAX_FRN_INT 
MEP_OPERAND_FMAX_CCRN 
MEP_OPERAND_FMAX_CIRR 
MEP_OPERAND_FMAX_CBCR 
MEP_OPERAND_FMAX_CERR 
MEP_OPERAND_FMAX_RM 
MEP_OPERAND_FMAX_COMPARE_I_P 
MEP_OPERAND_MAX 
MT_OPERAND_PC 
MT_OPERAND_FRSR1 
MT_OPERAND_FRSR2 
MT_OPERAND_FRDR 
MT_OPERAND_FRDRRR 
MT_OPERAND_IMM16 
MT_OPERAND_IMM16Z 
MT_OPERAND_IMM16O 
MT_OPERAND_RC 
MT_OPERAND_RCNUM 
MT_OPERAND_CONTNUM 
MT_OPERAND_RBBC 
MT_OPERAND_COLNUM 
MT_OPERAND_ROWNUM 
MT_OPERAND_ROWNUM1 
MT_OPERAND_ROWNUM2 
MT_OPERAND_RC1 
MT_OPERAND_RC2 
MT_OPERAND_CBRB 
MT_OPERAND_CELL 
MT_OPERAND_DUP 
MT_OPERAND_CTXDISP 
MT_OPERAND_FBDISP 
MT_OPERAND_TYPE 
MT_OPERAND_MASK 
MT_OPERAND_BANKADDR 
MT_OPERAND_INCAMT 
MT_OPERAND_XMODE 
MT_OPERAND_MASK1 
MT_OPERAND_BALL 
MT_OPERAND_BRC 
MT_OPERAND_RDA 
MT_OPERAND_WR 
MT_OPERAND_BALL2 
MT_OPERAND_BRC2 
MT_OPERAND_PERM 
MT_OPERAND_A23 
MT_OPERAND_CR 
MT_OPERAND_CBS 
MT_OPERAND_INCR 
MT_OPERAND_LENGTH 
MT_OPERAND_CBX 
MT_OPERAND_CCB 
MT_OPERAND_CDB 
MT_OPERAND_MODE 
MT_OPERAND_ID 
MT_OPERAND_SIZE 
MT_OPERAND_FBINCR 
MT_OPERAND_LOOPSIZE 
MT_OPERAND_IMM16L 
MT_OPERAND_RC3 
MT_OPERAND_CB1SEL 
MT_OPERAND_CB2SEL 
MT_OPERAND_CB1INCR 
MT_OPERAND_CB2INCR 
MT_OPERAND_MAX 
OPENRISC_OPERAND_PC 
OPENRISC_OPERAND_SR 
OPENRISC_OPERAND_CBIT 
OPENRISC_OPERAND_SIMM_16 
OPENRISC_OPERAND_UIMM_16 
OPENRISC_OPERAND_DISP_26 
OPENRISC_OPERAND_ABS_26 
OPENRISC_OPERAND_UIMM_5 
OPENRISC_OPERAND_RD 
OPENRISC_OPERAND_RA 
OPENRISC_OPERAND_RB 
OPENRISC_OPERAND_OP_F_23 
OPENRISC_OPERAND_OP_F_3 
OPENRISC_OPERAND_HI16 
OPENRISC_OPERAND_LO16 
OPENRISC_OPERAND_UI16NC 
OPENRISC_OPERAND_MAX 
XC16X_OPERAND_PC 
XC16X_OPERAND_SR 
XC16X_OPERAND_DR 
XC16X_OPERAND_DRI 
XC16X_OPERAND_SRB 
XC16X_OPERAND_DRB 
XC16X_OPERAND_SR2 
XC16X_OPERAND_SRC1 
XC16X_OPERAND_SRC2 
XC16X_OPERAND_SRDIV 
XC16X_OPERAND_REGNAM 
XC16X_OPERAND_UIMM2 
XC16X_OPERAND_UIMM3 
XC16X_OPERAND_UIMM4 
XC16X_OPERAND_UIMM7 
XC16X_OPERAND_UIMM8 
XC16X_OPERAND_UIMM16 
XC16X_OPERAND_UPOF16 
XC16X_OPERAND_REG8 
XC16X_OPERAND_REGMEM8 
XC16X_OPERAND_REGBMEM8 
XC16X_OPERAND_REGOFF8 
XC16X_OPERAND_REGHI8 
XC16X_OPERAND_REGB8 
XC16X_OPERAND_GENREG 
XC16X_OPERAND_SEG 
XC16X_OPERAND_SEGHI8 
XC16X_OPERAND_CADDR 
XC16X_OPERAND_REL 
XC16X_OPERAND_RELHI 
XC16X_OPERAND_CONDBIT 
XC16X_OPERAND_BIT1 
XC16X_OPERAND_BIT2 
XC16X_OPERAND_BIT4 
XC16X_OPERAND_LBIT4 
XC16X_OPERAND_LBIT2 
XC16X_OPERAND_BIT8 
XC16X_OPERAND_U4 
XC16X_OPERAND_BITONE 
XC16X_OPERAND_BIT01 
XC16X_OPERAND_COND 
XC16X_OPERAND_ICOND 
XC16X_OPERAND_EXTCOND 
XC16X_OPERAND_MEMORY 
XC16X_OPERAND_MEMGR8 
XC16X_OPERAND_CBIT 
XC16X_OPERAND_QBIT 
XC16X_OPERAND_QLOBIT 
XC16X_OPERAND_QHIBIT 
XC16X_OPERAND_MASK8 
XC16X_OPERAND_MASKLO8 
XC16X_OPERAND_PAGENUM 
XC16X_OPERAND_DATA8 
XC16X_OPERAND_DATAHI8 
XC16X_OPERAND_SGTDISBIT 
XC16X_OPERAND_UPAG16 
XC16X_OPERAND_USEG8 
XC16X_OPERAND_USEG16 
XC16X_OPERAND_USOF16 
XC16X_OPERAND_HASH 
XC16X_OPERAND_DOT 
XC16X_OPERAND_POF 
XC16X_OPERAND_PAG 
XC16X_OPERAND_SOF 
XC16X_OPERAND_SEGM 
XC16X_OPERAND_MAX 
XSTORMY16_OPERAND_PC 
XSTORMY16_OPERAND_PSW_Z8 
XSTORMY16_OPERAND_PSW_Z16 
XSTORMY16_OPERAND_PSW_CY 
XSTORMY16_OPERAND_PSW_HC 
XSTORMY16_OPERAND_PSW_OV 
XSTORMY16_OPERAND_PSW_PT 
XSTORMY16_OPERAND_PSW_S 
XSTORMY16_OPERAND_RD 
XSTORMY16_OPERAND_RDM 
XSTORMY16_OPERAND_RM 
XSTORMY16_OPERAND_RS 
XSTORMY16_OPERAND_RB 
XSTORMY16_OPERAND_RBJ 
XSTORMY16_OPERAND_BCOND2 
XSTORMY16_OPERAND_WS2 
XSTORMY16_OPERAND_BCOND5 
XSTORMY16_OPERAND_IMM2 
XSTORMY16_OPERAND_IMM3 
XSTORMY16_OPERAND_IMM3B 
XSTORMY16_OPERAND_IMM4 
XSTORMY16_OPERAND_IMM8 
XSTORMY16_OPERAND_IMM8SMALL 
XSTORMY16_OPERAND_IMM12 
XSTORMY16_OPERAND_IMM16 
XSTORMY16_OPERAND_LMEM8 
XSTORMY16_OPERAND_HMEM8 
XSTORMY16_OPERAND_REL8_2 
XSTORMY16_OPERAND_REL8_4 
XSTORMY16_OPERAND_REL12 
XSTORMY16_OPERAND_REL12A 
XSTORMY16_OPERAND_ABS24 
XSTORMY16_OPERAND_PSW 
XSTORMY16_OPERAND_RPSW 
XSTORMY16_OPERAND_SP 
XSTORMY16_OPERAND_R0 
XSTORMY16_OPERAND_R1 
XSTORMY16_OPERAND_R2 
XSTORMY16_OPERAND_R8 
XSTORMY16_OPERAND_MAX 

Definition at line 618 of file cgen.h.

Enumerator:
CGEN_OPINST_END 
CGEN_OPINST_INPUT 
CGEN_OPINST_OUTPUT 

Definition at line 730 of file cgen.h.

                      {
  /* End of table marker.  */
  CGEN_OPINST_END = 0,
  CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT
};
Enumerator:
CGEN_PARSE_OPERAND_RESULT_NUMBER 
CGEN_PARSE_OPERAND_RESULT_REGISTER 
CGEN_PARSE_OPERAND_RESULT_QUEUED 
CGEN_PARSE_OPERAND_RESULT_ERROR 

Definition at line 388 of file cgen.h.

Enumerator:
CGEN_PARSE_OPERAND_INIT 
CGEN_PARSE_OPERAND_INTEGER 
CGEN_PARSE_OPERAND_ADDRESS 
CGEN_PARSE_OPERAND_SYMBOLIC 

Definition at line 378 of file cgen.h.


Function Documentation

const CGEN_INSN* CGEN_SYM() assemble_insn ( CGEN_CPU_DESC  ,
const char *  ,
CGEN_FIELDS *  ,
CGEN_INSN_BYTES_PTR  ,
char **   
)
char* CGEN_SYM() build_insn_regex ( CGEN_INSN *  insn_)

Definition at line 177 of file cgen-asm.c.

{
  unsigned int hash;

  if (cd->asm_hash_table == NULL)
    build_asm_hash_table (cd);

  hash = (* cd->asm_hash) (insn);
  return cd->asm_hash_table[hash];
}

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Definition at line 605 of file cgen-opc.c.

{
  cd->signed_overflow_ok_p = 0;
}

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Definition at line 231 of file cgen-dis.c.

{
  unsigned int hash;

  if (cd->dis_hash_table == NULL)
    build_dis_hash_table (cd);

  hash = (* cd->dis_hash) (buf, value);

  return cd->dis_hash_table[hash];
}

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const char* cgen_expand_macro_insn ( CGEN_CPU_DESC  ,
const struct cgen_minsn_expansion ,
const char *  ,
const char **  ,
int ,
CGEN_OPERAND **   
)
void cgen_get_insn_operands ( CGEN_CPU_DESC  ,
const CGEN_INSN *  insn_,
const CGEN_FIELDS *  fields_,
int indices_ 
)

Definition at line 545 of file cgen-opc.c.

{
  const CGEN_OPINST *opinst;
  int i;

  if (insn->opinst == NULL)
    abort ();
  for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst)
    {
      enum cgen_operand_type op_type = opinst->op_type;
      if (op_type == CGEN_OPERAND_NIL)
       indices[i] = opinst->index;
      else
       indices[i] = (*cd->get_int_operand) (cd, op_type, fields);
    }
}

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Definition at line 364 of file cgen-opc.c.

{
  int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG);
  int insn_chunk_bitsize = cd->insn_chunk_bitsize;
  CGEN_INSN_INT value = 0;

  if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length)
    {
      /* We need to divide up the incoming value into insn_chunk_bitsize-length
        segments, and endian-convert them, one at a time. */
      int i;

      /* Enforce divisibility. */ 
      if ((length % insn_chunk_bitsize) != 0)
       abort ();

      for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */
       {
         int index;
         bfd_vma this_value;
         index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */
         this_value = bfd_get_bits (& buf[index / 8], insn_chunk_bitsize, big_p);
         value = (value << insn_chunk_bitsize) | this_value;
       }
    }
  else
    {
      value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG);
    }

  return value;
}

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Definition at line 268 of file cgen-opc.c.

{
  unsigned int i;
  const CGEN_HW_ENTRY **hw = cd->hw_table.entries;

  for (i = 0; i < cd->hw_table.num_entries; ++i)
    if (hw[i] && strcmp (name, hw[i]->name) == 0)
      return hw[i];

  return NULL;
}

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Definition at line 286 of file cgen-opc.c.

{
  unsigned int i;
  const CGEN_HW_ENTRY **hw = cd->hw_table.entries;

  /* ??? This can be speeded up.  */
  for (i = 0; i < cd->hw_table.num_entries; ++i)
    if (hw[i] && hwnum == hw[i]->type)
      return hw[i];

  return NULL;
}

Definition at line 47 of file cgen-asm.c.

{
  /* This tells the callback to re-initialize.  */
  (void) (* cd->parse_operand_fn)
    (cd, CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, NULL, NULL);
}

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Definition at line 335 of file cgen-opc.c.

{
  int count = cd->insn_table.num_init_entries;
  CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries;

  for ( ; rt_insns != NULL; rt_insns = rt_insns->next)
    ++count;

  return count;
}

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Definition at line 110 of file cgen-opc.c.

{
  unsigned int hash;
  size_t i;

  if (kt->name_hash_table == NULL)
    build_keyword_hash_tables (kt);

  hash = hash_keyword_name (kt, ke->name, 0);
  ke->next_name = kt->name_hash_table[hash];
  kt->name_hash_table[hash] = ke;

  hash = hash_keyword_value (kt, ke->value);
  ke->next_value = kt->value_hash_table[hash];
  kt->value_hash_table[hash] = ke;

  if (ke->name[0] == 0)
    kt->null_entry = ke;

  for (i = 1; i < strlen (ke->name); i++)
    if (! ISALNUM (ke->name[i])
       && ! strchr (kt->nonalpha_chars, ke->name[i]))
      {
       size_t idx = strlen (kt->nonalpha_chars);
       
       /* If you hit this limit, please don't just
          increase the size of the field, instead
          look for a better algorithm.  */
       if (idx >= sizeof (kt->nonalpha_chars) - 1)
         abort ();
       kt->nonalpha_chars[idx] = ke->name[i];
       kt->nonalpha_chars[idx+1] = 0;
      }
}

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Definition at line 49 of file cgen-opc.c.

{
  const CGEN_KEYWORD_ENTRY *ke;
  const char *p,*n;

  if (kt->name_hash_table == NULL)
    build_keyword_hash_tables (kt);

  ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)];

  /* We do case insensitive comparisons.
     If that ever becomes a problem, add an attribute that denotes
     "do case sensitive comparisons".  */

  while (ke != NULL)
    {
      n = name;
      p = ke->name;

      while (*p
            && (*p == *n
               || (ISALPHA (*p) && (TOLOWER (*p) == TOLOWER (*n)))))
       ++n, ++p;

      if (!*p && !*n)
       return ke;

      ke = ke->next_name;
    }

  if (kt->null_entry)
    return kt->null_entry;
  return NULL;
}

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Definition at line 88 of file cgen-opc.c.

{
  const CGEN_KEYWORD_ENTRY *ke;

  if (kt->name_hash_table == NULL)
    build_keyword_hash_tables (kt);

  ke = kt->value_hash_table[hash_keyword_value (kt, value)];

  while (ke != NULL)
    {
      if (value == ke->value)
       return ke;
      ke = ke->next_value;
    }

  return NULL;
}

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Definition at line 156 of file cgen-opc.c.

{
  CGEN_KEYWORD_SEARCH search;

  /* FIXME: Need to specify format of params.  */
  if (spec != NULL)
    abort ();

  if (kt->name_hash_table == NULL)
    build_keyword_hash_tables (kt);

  search.table = kt;
  search.spec = spec;
  search.current_hash = 0;
  search.current_entry = NULL;
  return search;
}

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Definition at line 178 of file cgen-opc.c.

{
  /* Has search finished?  */
  if (search->current_hash == search->table->hash_table_size)
    return NULL;

  /* Search in progress?  */
  if (search->current_entry != NULL
      /* Anything left on this hash chain?  */
      && search->current_entry->next_name != NULL)
    {
      search->current_entry = search->current_entry->next_name;
      return search->current_entry;
    }

  /* Move to next hash chain [unless we haven't started yet].  */
  if (search->current_entry != NULL)
    ++search->current_hash;

  while (search->current_hash < search->table->hash_table_size)
    {
      search->current_entry = search->table->name_hash_table[search->current_hash];
      if (search->current_entry != NULL)
       return search->current_entry;
      ++search->current_hash;
    }

  return NULL;
}
const CGEN_INSN* cgen_lookup_get_insn_operands ( CGEN_CPU_DESC  ,
const CGEN_INSN *  insn_,
CGEN_INSN_INT  int_value_,
unsigned char *  bytes_value_,
int  length_,
int indices_,
CGEN_FIELDS *  fields_ 
)

Definition at line 576 of file cgen-opc.c.

{
  /* Pass non-zero for ALIAS_P only if INSN != NULL.
     If INSN == NULL, we want a real insn.  */
  insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value,
                        length, fields, insn != NULL);
  if (! insn)
    return NULL;

  cgen_get_insn_operands (cd, insn, fields, indices);
  return insn;
}

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const CGEN_INSN* cgen_lookup_insn ( CGEN_CPU_DESC  ,
const CGEN_INSN *  insn_,
CGEN_INSN_INT  int_value_,
unsigned char *  bytes_value_,
int  length_,
CGEN_FIELDS *  fields_,
int  alias_p_ 
)

Definition at line 448 of file cgen-opc.c.

{
  unsigned char *buf;
  CGEN_INSN_INT base_insn;
  CGEN_EXTRACT_INFO ex_info;
  CGEN_EXTRACT_INFO *info;

  if (cd->int_insn_p)
    {
      info = NULL;
      buf = (unsigned char *) alloca (cd->max_insn_bitsize / 8);
      cgen_put_insn_value (cd, buf, length, insn_int_value);
      base_insn = insn_int_value;
    }
  else
    {
      info = &ex_info;
      ex_info.dis_info = NULL;
      ex_info.insn_bytes = insn_bytes_value;
      ex_info.valid = -1;
      buf = insn_bytes_value;
      base_insn = cgen_get_insn_value (cd, buf, length);
    }

  if (!insn)
    {
      const CGEN_INSN_LIST *insn_list;

      /* The instructions are stored in hash lists.
        Pick the first one and keep trying until we find the right one.  */

      insn_list = cgen_dis_lookup_insn (cd, (char *) buf, base_insn);
      while (insn_list != NULL)
       {
         insn = insn_list->insn;

         if (alias_p
             /* FIXME: Ensure ALIAS attribute always has same index.  */
             || ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS))
           {
             /* Basic bit mask must be correct.  */
             /* ??? May wish to allow target to defer this check until the
               extract handler.  */
             if ((base_insn & CGEN_INSN_BASE_MASK (insn))
                == CGEN_INSN_BASE_VALUE (insn))
              {
                /* ??? 0 is passed for `pc' */
                int elength = CGEN_EXTRACT_FN (cd, insn)
                  (cd, insn, info, base_insn, fields, (bfd_vma) 0);
                if (elength > 0)
                  {
                    /* sanity check */
                    if (length != 0 && length != elength)
                     abort ();
                    return insn;
                  }
              }
           }

         insn_list = insn_list->next;
       }
    }
  else
    {
      /* Sanity check: can't pass an alias insn if ! alias_p.  */
      if (! alias_p
         && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS))
       abort ();
      /* Sanity check: length must be correct.  */
      if (length != CGEN_INSN_BITSIZE (insn))
       abort ();

      /* ??? 0 is passed for `pc' */
      length = CGEN_EXTRACT_FN (cd, insn)
       (cd, insn, info, base_insn, fields, (bfd_vma) 0);
      /* Sanity check: must succeed.
        Could relax this later if it ever proves useful.  */
      if (length == 0)
       abort ();
      return insn;
    }

  return NULL;
}

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Definition at line 350 of file cgen-opc.c.

{
  int count = cd->macro_insn_table.num_init_entries;
  CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries;

  for ( ; rt_insns != NULL; rt_insns = rt_insns->next)
    ++count;

  return count;
}

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Definition at line 306 of file cgen-opc.c.

{
  unsigned int i;
  const CGEN_OPERAND **op = cd->operand_table.entries;

  for (i = 0; i < cd->operand_table.num_entries; ++i)
    if (op[i] && strcmp (name, op[i]->name) == 0)
      return op[i];

  return NULL;
}

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Definition at line 325 of file cgen-opc.c.

{
  return cd->operand_table.entries[opnum];
}

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const char* cgen_parse_keyword ( CGEN_CPU_DESC  ,
const char **  ,
CGEN_KEYWORD ,
long  
)

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void cgen_put_insn_value ( CGEN_CPU_DESC  ,
unsigned char *  ,
int  ,
CGEN_INSN_INT   
)

Definition at line 400 of file cgen-opc.c.

{
  int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG);
  int insn_chunk_bitsize = cd->insn_chunk_bitsize;

  if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length)
    {
      /* We need to divide up the incoming value into insn_chunk_bitsize-length
        segments, and endian-convert them, one at a time. */
      int i;

      /* Enforce divisibility. */ 
      if ((length % insn_chunk_bitsize) != 0)
       abort ();

      for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */
       {
         int index;
         index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */
         bfd_put_bits ((bfd_vma) value, & buf[index / 8], insn_chunk_bitsize, big_p);
         value >>= insn_chunk_bitsize;
       }
    }
  else
    {
      bfd_put_bits ((bfd_vma) value, buf, length, big_p);
    }
}

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const char* cgen_read_cpu_file ( CGEN_CPU_DESC  ,
const char *  filename_ 
)

Definition at line 39 of file cgen-asm.c.

{
  cd->parse_operand_fn = fn;
}

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Definition at line 598 of file cgen-opc.c.

{
  cd->signed_overflow_ok_p = 1;
}

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Definition at line 612 of file cgen-opc.c.

{
  return cd->signed_overflow_ok_p;
}

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const CGEN_KEYWORD CGEN_SYM ( operand_mach  )
CGEN_CPU_DESC CGEN_SYM() cpu_open ( enum  cgen_cpu_open_arg,
  ... 
)
CGEN_CPU_DESC CGEN_SYM() cpu_open_1 ( const char *  mach_name_,
enum cgen_endian  endian_ 
)
int CGEN_SYM() get_mach ( const char *  )