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cell-binutils  2.17cvs20070401
ia64-opc.h
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00001 /* ia64-opc.h -- IA-64 opcode table.
00002    Copyright 1998, 1999, 2000, 2002, 2005, 2006
00003    Free Software Foundation, Inc.
00004    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
00005 
00006    This file is part of GDB, GAS, and the GNU binutils.
00007 
00008    GDB, GAS, and the GNU binutils are free software; you can redistribute
00009    them and/or modify them under the terms of the GNU General Public
00010    License as published by the Free Software Foundation; either version
00011    2, or (at your option) any later version.
00012 
00013    GDB, GAS, and the GNU binutils are distributed in the hope that they
00014    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016    the GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with this file; see the file COPYING.  If not, write to the
00020    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00021    02110-1301, USA.  */
00022 
00023 #ifndef IA64_OPC_H
00024 #define IA64_OPC_H
00025 
00026 #include "opcode/ia64.h"
00027 
00028 /* define a couple of abbreviations: */
00029 
00030 #define bOp(x)       (((ia64_insn) ((x) & 0xf)) << 37)
00031 #define mOp   bOp (-1)
00032 #define Op(x) bOp (x), mOp
00033 
00034 #define FIRST        IA64_OPCODE_FIRST
00035 #define X_IN_MLX     IA64_OPCODE_X_IN_MLX
00036 #define LAST         IA64_OPCODE_LAST
00037 #define PRIV         IA64_OPCODE_PRIV
00038 #define NO_PRED             IA64_OPCODE_NO_PRED
00039 #define SLOT2        IA64_OPCODE_SLOT2
00040 #define PSEUDO              IA64_OPCODE_PSEUDO
00041 #define F2_EQ_F3     IA64_OPCODE_F2_EQ_F3
00042 #define LEN_EQ_64MCNT       IA64_OPCODE_LEN_EQ_64MCNT
00043 #define MOD_RRBS        IA64_OPCODE_MOD_RRBS
00044 #define POSTINC             IA64_OPCODE_POSTINC
00045 
00046 #define AR_CCV       IA64_OPND_AR_CCV
00047 #define AR_PFS       IA64_OPND_AR_PFS
00048 #define AR_CSD       IA64_OPND_AR_CSD
00049 #define C1    IA64_OPND_C1
00050 #define C8    IA64_OPND_C8
00051 #define C16   IA64_OPND_C16
00052 #define GR0   IA64_OPND_GR0
00053 #define IP    IA64_OPND_IP
00054 #define PR    IA64_OPND_PR
00055 #define PR_ROT       IA64_OPND_PR_ROT
00056 #define PSR   IA64_OPND_PSR
00057 #define PSR_L IA64_OPND_PSR_L
00058 #define PSR_UM       IA64_OPND_PSR_UM
00059 
00060 #define AR3   IA64_OPND_AR3
00061 #define B1    IA64_OPND_B1
00062 #define B2    IA64_OPND_B2
00063 #define CR3   IA64_OPND_CR3
00064 #define F1    IA64_OPND_F1
00065 #define F2    IA64_OPND_F2
00066 #define F3    IA64_OPND_F3
00067 #define F4    IA64_OPND_F4
00068 #define P1    IA64_OPND_P1
00069 #define P2    IA64_OPND_P2
00070 #define R1    IA64_OPND_R1
00071 #define R2    IA64_OPND_R2
00072 #define R3    IA64_OPND_R3
00073 #define R3_2  IA64_OPND_R3_2
00074 
00075 #define CPUID_R3 IA64_OPND_CPUID_R3
00076 #define DBR_R3       IA64_OPND_DBR_R3
00077 #define DTR_R3       IA64_OPND_DTR_R3
00078 #define ITR_R3       IA64_OPND_ITR_R3
00079 #define IBR_R3       IA64_OPND_IBR_R3
00080 #define MR3   IA64_OPND_MR3
00081 #define MSR_R3       IA64_OPND_MSR_R3
00082 #define PKR_R3       IA64_OPND_PKR_R3
00083 #define PMC_R3       IA64_OPND_PMC_R3
00084 #define PMD_R3       IA64_OPND_PMD_R3
00085 #define RR_R3 IA64_OPND_RR_R3
00086 
00087 #define CCNT5 IA64_OPND_CCNT5
00088 #define CNT2a IA64_OPND_CNT2a
00089 #define CNT2b IA64_OPND_CNT2b
00090 #define CNT2c IA64_OPND_CNT2c
00091 #define CNT5  IA64_OPND_CNT5
00092 #define CNT6  IA64_OPND_CNT6
00093 #define CPOS6a       IA64_OPND_CPOS6a
00094 #define CPOS6b       IA64_OPND_CPOS6b
00095 #define CPOS6c       IA64_OPND_CPOS6c
00096 #define IMM1  IA64_OPND_IMM1
00097 #define IMM14 IA64_OPND_IMM14
00098 #define IMM17 IA64_OPND_IMM17
00099 #define IMM22 IA64_OPND_IMM22
00100 #define IMM44 IA64_OPND_IMM44
00101 #define SOF   IA64_OPND_SOF
00102 #define SOL   IA64_OPND_SOL
00103 #define SOR   IA64_OPND_SOR
00104 #define IMM8  IA64_OPND_IMM8
00105 #define IMM8U4       IA64_OPND_IMM8U4
00106 #define IMM8M1       IA64_OPND_IMM8M1
00107 #define IMM8M1U4 IA64_OPND_IMM8M1U4
00108 #define IMM8M1U8 IA64_OPND_IMM8M1U8
00109 #define IMM9a IA64_OPND_IMM9a
00110 #define IMM9b IA64_OPND_IMM9b
00111 #define IMMU2 IA64_OPND_IMMU2
00112 #define IMMU21       IA64_OPND_IMMU21
00113 #define IMMU24       IA64_OPND_IMMU24
00114 #define IMMU62       IA64_OPND_IMMU62
00115 #define IMMU64       IA64_OPND_IMMU64
00116 #define IMMU5b       IA64_OPND_IMMU5b
00117 #define IMMU7a       IA64_OPND_IMMU7a
00118 #define IMMU7b       IA64_OPND_IMMU7b
00119 #define IMMU9 IA64_OPND_IMMU9
00120 #define INC3  IA64_OPND_INC3
00121 #define LEN4  IA64_OPND_LEN4
00122 #define LEN6  IA64_OPND_LEN6
00123 #define MBTYPE4      IA64_OPND_MBTYPE4
00124 #define MHTYPE8      IA64_OPND_MHTYPE8
00125 #define POS6  IA64_OPND_POS6
00126 #define TAG13 IA64_OPND_TAG13
00127 #define TAG13b       IA64_OPND_TAG13b
00128 #define TGT25 IA64_OPND_TGT25
00129 #define TGT25b       IA64_OPND_TGT25b
00130 #define TGT25c       IA64_OPND_TGT25c
00131 #define TGT64   IA64_OPND_TGT64
00132 
00133 #endif